gen/sim: fix import to use litex simulator instead of migen simulator

diff --git a/litex/gen/sim/__init__.py b/litex/gen/sim/__init__.py
index e04060e16eca45720edbd19b4e73a1b6c8317ffd..853486a66909509d3692f35cf9cff1a45ee2f926 100644 (file)
--- a/litex/gen/sim/__init__.py
+++ b/litex/gen/sim/__init__.py
@@ -1 +1 @@
-from migen.sim.core import Simulator, run_simulation, passive
+from litex.gen.sim.core import Simulator, run_simulation, passive

diff --git a/litex/gen/sim/core.py b/litex/gen/sim/core.py
index e3db45f6f1f2fdde3c820af4815da459d4aeb19a..2ba0cebc8bbd0d27a3daf9dd08c5693591a39ea0 100644 (file)
--- a/litex/gen/sim/core.py
+++ b/litex/gen/sim/core.py
@@ -14,7 +14,8 @@ from migen.fhdl.simplify import MemoryToArray
 from migen.fhdl.specials import _MemoryLocation
 from migen.fhdl.module import Module
 from migen.genlib.resetsync import AsyncResetSynchronizer
-from migen.sim.vcd import VCDWriter, DummyVCDWriter
+
+from litex.gen.sim.vcd import VCDWriter, DummyVCDWriter
 
 
 class ClockState: