+2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ AVX Programming Reference (June, 2010)
+ * gas/i386/rdrnd.s: Replace rdrnd with rdrand.
+ * gas/i386/rdrnd-intel.d: Likewise.
+ * gas/i386/rdrnd.d: Likewise.
+ * gas/i386/x86-64-rdrnd-intel.d: Likewise.
+ * gas/i386/x86-64-rdrnd.d: Likewise.
+ * gas/i386/x86-64-rdrnd.s: Likewise.
+
2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
PR gas/10531
Disassembly of section .text:
0+ <foo>:
-[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd bx
-[ ]*[a-f0-9]+: 0f c7 f3 rdrnd ebx
-[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd bx
-[ ]*[a-f0-9]+: 0f c7 f3 rdrnd ebx
+[ ]*[a-f0-9]+: 66 0f c7 f3 rdrand bx
+[ ]*[a-f0-9]+: 0f c7 f3 rdrand ebx
+[ ]*[a-f0-9]+: 66 0f c7 f3 rdrand bx
+[ ]*[a-f0-9]+: 0f c7 f3 rdrand ebx
#pass
Disassembly of section .text:
0+ <foo>:
-[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd %bx
-[ ]*[a-f0-9]+: 0f c7 f3 rdrnd %ebx
-[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd %bx
-[ ]*[a-f0-9]+: 0f c7 f3 rdrnd %ebx
+[ ]*[a-f0-9]+: 66 0f c7 f3 rdrand %bx
+[ ]*[a-f0-9]+: 0f c7 f3 rdrand %ebx
+[ ]*[a-f0-9]+: 66 0f c7 f3 rdrand %bx
+[ ]*[a-f0-9]+: 0f c7 f3 rdrand %ebx
#pass
.text
foo:
- rdrnd %bx
- rdrnd %ebx
+ rdrand %bx
+ rdrand %ebx
.intel_syntax noprefix
- rdrnd bx
- rdrnd ebx
+ rdrand bx
+ rdrand ebx
Disassembly of section .text:
0+ <foo>:
-[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd bx
-[ ]*[a-f0-9]+: 0f c7 f3 rdrnd ebx
-[ ]*[a-f0-9]+: 48 0f c7 f3 rdrnd rbx
-[ ]*[a-f0-9]+: 66 41 0f c7 f0 rdrnd r8w
-[ ]*[a-f0-9]+: 41 0f c7 f0 rdrnd r8d
-[ ]*[a-f0-9]+: 49 0f c7 f0 rdrnd r8
-[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd bx
-[ ]*[a-f0-9]+: 0f c7 f3 rdrnd ebx
-[ ]*[a-f0-9]+: 48 0f c7 f3 rdrnd rbx
-[ ]*[a-f0-9]+: 66 41 0f c7 f0 rdrnd r8w
-[ ]*[a-f0-9]+: 41 0f c7 f0 rdrnd r8d
-[ ]*[a-f0-9]+: 49 0f c7 f0 rdrnd r8
+[ ]*[a-f0-9]+: 66 0f c7 f3 rdrand bx
+[ ]*[a-f0-9]+: 0f c7 f3 rdrand ebx
+[ ]*[a-f0-9]+: 48 0f c7 f3 rdrand rbx
+[ ]*[a-f0-9]+: 66 41 0f c7 f0 rdrand r8w
+[ ]*[a-f0-9]+: 41 0f c7 f0 rdrand r8d
+[ ]*[a-f0-9]+: 49 0f c7 f0 rdrand r8
+[ ]*[a-f0-9]+: 66 0f c7 f3 rdrand bx
+[ ]*[a-f0-9]+: 0f c7 f3 rdrand ebx
+[ ]*[a-f0-9]+: 48 0f c7 f3 rdrand rbx
+[ ]*[a-f0-9]+: 66 41 0f c7 f0 rdrand r8w
+[ ]*[a-f0-9]+: 41 0f c7 f0 rdrand r8d
+[ ]*[a-f0-9]+: 49 0f c7 f0 rdrand r8
#pass
Disassembly of section .text:
0+ <foo>:
-[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd %bx
-[ ]*[a-f0-9]+: 0f c7 f3 rdrnd %ebx
-[ ]*[a-f0-9]+: 48 0f c7 f3 rdrnd %rbx
-[ ]*[a-f0-9]+: 66 41 0f c7 f0 rdrnd %r8w
-[ ]*[a-f0-9]+: 41 0f c7 f0 rdrnd %r8d
-[ ]*[a-f0-9]+: 49 0f c7 f0 rdrnd %r8
-[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd %bx
-[ ]*[a-f0-9]+: 0f c7 f3 rdrnd %ebx
-[ ]*[a-f0-9]+: 48 0f c7 f3 rdrnd %rbx
-[ ]*[a-f0-9]+: 66 41 0f c7 f0 rdrnd %r8w
-[ ]*[a-f0-9]+: 41 0f c7 f0 rdrnd %r8d
-[ ]*[a-f0-9]+: 49 0f c7 f0 rdrnd %r8
+[ ]*[a-f0-9]+: 66 0f c7 f3 rdrand %bx
+[ ]*[a-f0-9]+: 0f c7 f3 rdrand %ebx
+[ ]*[a-f0-9]+: 48 0f c7 f3 rdrand %rbx
+[ ]*[a-f0-9]+: 66 41 0f c7 f0 rdrand %r8w
+[ ]*[a-f0-9]+: 41 0f c7 f0 rdrand %r8d
+[ ]*[a-f0-9]+: 49 0f c7 f0 rdrand %r8
+[ ]*[a-f0-9]+: 66 0f c7 f3 rdrand %bx
+[ ]*[a-f0-9]+: 0f c7 f3 rdrand %ebx
+[ ]*[a-f0-9]+: 48 0f c7 f3 rdrand %rbx
+[ ]*[a-f0-9]+: 66 41 0f c7 f0 rdrand %r8w
+[ ]*[a-f0-9]+: 41 0f c7 f0 rdrand %r8d
+[ ]*[a-f0-9]+: 49 0f c7 f0 rdrand %r8
#pass
.text
foo:
- rdrnd %bx
- rdrnd %ebx
- rdrnd %rbx
- rdrnd %r8w
- rdrnd %r8d
- rdrnd %r8
+ rdrand %bx
+ rdrand %ebx
+ rdrand %rbx
+ rdrand %r8w
+ rdrand %r8d
+ rdrand %r8
.intel_syntax noprefix
- rdrnd bx
- rdrnd ebx
- rdrnd rbx
- rdrnd r8w
- rdrnd r8d
- rdrnd r8
+ rdrand bx
+ rdrand ebx
+ rdrand rbx
+ rdrand r8w
+ rdrand r8d
+ rdrand r8
+2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ AVX Programming Reference (June, 2010)
+ * i386-dis.c (mod_table): Replace rdrnd with rdrand.
+ * i386-opc.tbl: Likewise.
+ * i386-tbl.h: Regenerated.
+
2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.h (CpuFSGSBase): Fix a typo in comments.
{
/* MOD_0FC7_REG_6 */
{ PREFIX_TABLE (PREFIX_0FC7_REG_6) },
- { "rdrnd", { Ev } },
+ { "rdrand", { Ev } },
},
{
/* MOD_0FC7_REG_7 */
rdfsbase, 1, 0xf30fae, 0x0, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
rdgsbase, 1, 0xf30fae, 0x1, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
-rdrnd, 1, 0xfc7, 0x6, 2, CpuRdRnd, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64 }
+rdrand, 1, 0xfc7, 0x6, 2, CpuRdRnd, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64 }
wrfsbase, 1, 0xf30fae, 0x2, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
wrgsbase, 1, 0xf30fae, 0x3, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
vcvtph2ps, 2, 0x6613, None, 1, CpuF16C, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
{ { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } } } },
- { "rdrnd", 1, 0xfc7, 0x6, 2,
+ { "rdrand", 1, 0xfc7, 0x6, 2,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 0, 0, 0, 0, 0 } },