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add RADV
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Thu, 26 Sep 2019 03:40:25 +0000
(
04:40
+0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Thu, 26 Sep 2019 03:40:25 +0000
(
04:40
+0100)
nlnet_2019_amdvlk_port.mdwn
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diff --git
a/nlnet_2019_amdvlk_port.mdwn
b/nlnet_2019_amdvlk_port.mdwn
index 6a804b86c38afdb118a778e5784ff9c870b34596..cd6a389b991f04087e767f05f97f0a44470b28f2 100644
(file)
--- a/
nlnet_2019_amdvlk_port.mdwn
+++ b/
nlnet_2019_amdvlk_port.mdwn
@@
-158,6
+158,10
@@
efforts to introduce "mainline" LLVM patches on an ongoing piecemeal
basis, and at the same time *add our own assembler back-end* into the
same fast-moving target.
+Whereas with RADV it is upstreamed in MESA, and has much wider community
+support, it will need very careful detailed evaluation to ensure that it meets
+the needs of the Libre RISC-V Vector Engine.
+
## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
As mentioned in the 2018 submission, the Libre RISC-V