Convert to use #945

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index a98bc30d97b2dac5775755a94b58f49e4b23faf3..93d9707629c68af42bf67cfa73393b9ed0d18c3b 100644 (file)
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,20 +127,14 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
        assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 21 *)
-`ifdef ABC_MODEL
-    (* whitebox *)
-`endif
+(* abc_box_id = 21, lib_whitebox *)
 module SB_CARRY (output CO, input I0, I1, CI);
        assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
 // Positive Edge SiliconBlue FF Cells
 
-(* abc_box_id = 1, abc_flop *)
-`ifdef ABC_MODEL
-    (* whitebox *)
-`endif
+(* abc_box_id = 1, abc_flop, lib_whitebox *)
 module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
 `ifndef ABC_MODEL
        always @(posedge C)

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 7cedecdffb269c9f188e4837bbfaf91dfa633376..718f9d9e0c454ac9aa70b4c9029564f8688fc8c1 100644 (file)
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
        {
                if (check_label("begin"))
                {
-                       run("read_verilog -wb -D ABC_MODEL +/ice40/cells_sim.v");
+                       run("read_verilog -lib -D ABC_MODEL +/ice40/cells_sim.v");
                        run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
                        run("proc");
                }