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Cleanup
author
Eddie Hung
<eddie@fpgeh.com>
Mon, 17 Jun 2019 22:10:33 +0000
(15:10 -0700)
committer
Eddie Hung
<eddie@fpgeh.com>
Mon, 17 Jun 2019 22:10:33 +0000
(15:10 -0700)
passes/techmap/abc9.cc
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diff --git
a/passes/techmap/abc9.cc
b/passes/techmap/abc9.cc
index 776bceb3bad0cb84e951bbff6a2d5195a7334527..f56350b1dca74f8e619141ab61d0d3f727f4d71c 100644
(file)
--- a/
passes/techmap/abc9.cc
+++ b/
passes/techmap/abc9.cc
@@
-527,7
+527,7
@@
void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
}
RTLIL::Module* box_module = design->module(cell->type);
if (box_module && box_module->attributes.count("\\abc_box_id"))
- boxes.emplace_back(
it->second
);
+ boxes.emplace_back(
cell
);
++it;
}
@@
-629,8
+629,8
@@
void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
}
}
-
for (auto cell : boxes)
-
module->remove(cell);
+ for (auto cell : boxes)
+ module->remove(cell);
// Copy connections (and rename) from mapped_mod to module
for (auto conn : mapped_mod->connections()) {