integration/soc: make DMA slave region cover (at least) the lower 4GB

Assuming we currently support a 32-bit (4GB) physical address space,
ensure that the dma_bus slave covers the entire range, covering any
possible layout of the LiteX SoC memory map (e.g., rocket has MMIO
in a wide range of registers located below 2GB, and DRAM starting at
the 2GB mark, needing DMA accesses to be routed appropriately for the
entire 4GB physical address range).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 40ae46a5159f9f35fea28ab537d51a67a24a2441..4a459ed1058ce0ce0811ed679690fc61a2d2a9a3 100644 (file)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -845,7 +845,7 @@ class SoC(Module):
                     data_width       = self.bus.data_width,
                 )
                 dma_bus = wishbone.Interface(data_width=self.bus.data_width)
-                self.dma_bus.add_slave("dma", slave=dma_bus, region=SoCRegion(origin=0x00000000, size=0x80000000)) # FIXME: size
+                self.dma_bus.add_slave("dma", slave=dma_bus, region=SoCRegion(origin=0x00000000, size=0x100000000)) # FIXME: covers lower 4GB only
                 self.submodules += wishbone.Converter(dma_bus, self.cpu.dma_bus)
 
             # Connect SoCController's reset to CPU reset