ppc/svp64: support divmod2du instruction

diff --git a/gas/testsuite/gas/ppc/divmod2du.d b/gas/testsuite/gas/ppc/divmod2du.d
new file mode 100644 (file)
index 0000000..d5b0ba3
--- /dev/null
+++ b/gas/testsuite/gas/ppc/divmod2du.d
@@ -0,0 +1,16 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*:\s+(13 e0 00 32|32 00 e0 13)\s+maddedu\sr31,r0,r0,r0
+.*:\s+(10 1f 00 32|32 00 1f 10)\s+maddedu\sr0,r31,r0,r0
+.*:\s+(10 00 f8 32|32 f8 00 10)\s+maddedu\sr0,r0,r31,r0
+.*:\s+(10 00 07 f2|f2 07 00 10)\s+maddedu\sr0,r0,r0,r31
+.*:\s+(13 e0 00 3a|3a 00 e0 13)\s+divmod2du\sr31,r0,r0,r0
+.*:\s+(10 1f 00 3a|3a 00 1f 10)\s+divmod2du\sr0,r31,r0,r0
+.*:\s+(10 00 f8 3a|3a f8 00 10)\s+divmod2du\sr0,r0,r31,r0
+.*:\s+(10 00 07 fa|fa 07 00 10)\s+divmod2du\sr0,r0,r0,r31

diff --git a/gas/testsuite/gas/ppc/divmod2du.s b/gas/testsuite/gas/ppc/divmod2du.s
new file mode 100644 (file)
index 0000000..9ff3c24
--- /dev/null
+++ b/gas/testsuite/gas/ppc/divmod2du.s
@@ -0,0 +1,8 @@
+maddedu 31,0,0,0
+maddedu 0,31,0,0
+maddedu 0,0,31,0
+maddedu 0,0,0,31
+divmod2du 31,0,0,0
+divmod2du 0,31,0,0
+divmod2du 0,0,31,0
+divmod2du 0,0,0,31

diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index b1fc7fcb5ce007d1be594e59eb509fd47e0e9e51..db9d31f62831d023c734b2e41afc694f9063ab12 100644 (file)
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -170,3 +170,4 @@ run_dump_test "absd"
 run_dump_test "bmask"
 run_dump_test "fptrans"
 run_dump_test "maddedu"
+run_dump_test "divmod2du"

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index bf7ce6a117b734efff571c7c29ecaea4431fcce2..7fa8866df2ed9083b08244a69d70b3511cb85b39 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -5248,6 +5248,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"ps_mul.",    A  (4,  25,1),  AFRB_MASK,   PPCPS,     0,              {FRT, FRA, FRC}},
 {"maddedu",    VXA(4,  50),    VXA_MASK,    SVP64,     PPCVLE,         {RT, RA, RB, RC}},
 {"maddld",     VXA(4,  51),    VXA_MASK,    POWER9,    0,              {RT, RA, RB, RC}},
+{"divmod2du",  VXA(4,  58),    VXA_MASK,    POWER9,    0,              {RT, RA, RB, RC}},
 {"ps_rsqrte",  A  (4,  26,0), AFRAFRC_MASK, PPCPS,     0,              {FRT, FRB}},
 {"ps_rsqrte.", A  (4,  26,1), AFRAFRC_MASK, PPCPS,     0,              {FRT, FRB}},
 {"ps_msub",    A  (4,  28,0),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},