i965/vec4/dce: improve track of partial flag register writes
authorSamuel Iglesias Gonsálvez <siglesias@igalia.com>
Fri, 17 Mar 2017 10:57:25 +0000 (11:57 +0100)
committerFrancisco Jerez <currojerez@riseup.net>
Fri, 14 Apr 2017 21:56:09 +0000 (14:56 -0700)
This is required for correctness in presence of multiple 4-wide flag
writes (e.g. 4-wide instructions with a conditional mod set) which
update a different portion of the same 8-bit flag subregister.

Right now we keep track of flag dataflow with 8-bit granularity and
consider flag writes to have killed any previous definition of the
same subregister even if the write was less than 8 channels wide,
which can cause live flag register updates to be dead
code-eliminated incorrectly.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
src/intel/compiler/brw_vec4_dead_code_eliminate.cpp

index 5b22a096dd1b6c58072f9a2ddaa0d851a3907355..c09a3d7ebe919e8d763e91e3715a24496b413635 100644 (file)
@@ -121,7 +121,7 @@ vec4_visitor::dead_code_eliminate()
             }
          }
 
-         if (inst->writes_flag() && !inst->predicate) {
+         if (inst->writes_flag() && !inst->predicate && inst->exec_size == 8) {
             for (unsigned c = 0; c < 4; c++)
                BITSET_CLEAR(flag_live, c);
          }