avr.md (*umaddqihi4.2): New insn-and-split.

	* config/avr/avr.md (*umaddqihi4.2): New insn-and-split.

From-SVN: r184919

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5f1d679a9a9e0206b7b71c1d1a18d533a67a808e..06f8dcf68c5b58c5ef0e8898ee100ef9d48965f9 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2012-03-05  Georg-Johann Lay  <avr@gjlay.de>
+
+       * config/avr/avr.md (*umaddqihi4.2): New insn-and-split.
+
 2012-03-04  H.J. Lu  <hongjiu.lu@intel.com>
 
        * config/i386/i386.c (pro_epilogue_adjust_stack): Check Pmode

diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 5cc3e3e4f249d89e5f1df8b4546a0ecca54919cb..bcf21af63127c064a823e324eb016c74088dd568 100644 (file)
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -1692,6 +1692,29 @@
 
 ;; Handle small constants
 
+;; Special case of a += 2*b as frequently seen with accesses to int arrays.
+;; This is shorter, faster than MUL and has lower register pressure.
+
+(define_insn_and_split "*umaddqihi4.2"
+  [(set (match_operand:HI 0 "register_operand"                                  "=r")
+        (plus:HI (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
+                          (const_int 2))
+                 (match_operand:HI 2 "register_operand"                          "r")))]
+  "!reload_completed
+   && !reg_overlap_mentioned_p (operands[0], operands[1])"
+  { gcc_unreachable(); }
+  "&& 1"
+  [(set (match_dup 0)
+        (match_dup 2))
+   ; *addhi3_zero_extend
+   (set (match_dup 0)
+        (plus:HI (zero_extend:HI (match_dup 1))
+                 (match_dup 0)))
+   ; *addhi3_zero_extend
+   (set (match_dup 0)
+        (plus:HI (zero_extend:HI (match_dup 1))
+                 (match_dup 0)))])
+
 ;; "umaddqihi4.uconst"
 ;; "maddqihi4.sconst"
 (define_insn_and_split "*<extend_u>maddqihi4.<extend_su>const"