case AARCH64_OPND_SVE_ZnxN:
case AARCH64_OPND_SVE_ZtxN:
+ case AARCH64_OPND_SME_Zdnx2:
+ case AARCH64_OPND_SME_Zdnx4:
+ case AARCH64_OPND_SME_Znx2:
+ case AARCH64_OPND_SME_Znx4:
reg_type = REG_TYPE_Z;
goto vector_reg_list;
break;
case AARCH64_OPND_SME_ZA_HV_idx_src:
+ case AARCH64_OPND_SME_ZA_HV_idx_srcxN:
case AARCH64_OPND_SME_ZA_HV_idx_dest:
+ case AARCH64_OPND_SME_ZA_HV_idx_destxN:
case AARCH64_OPND_SME_ZA_HV_idx_ldstr:
if (operands[i] == AARCH64_OPND_SME_ZA_HV_idx_ldstr
? !parse_sme_za_hv_tiles_operand_with_braces (&str,
info->imm.value = val;
break;
+ case AARCH64_OPND_SME_ZA_array_off3_0:
+ case AARCH64_OPND_SME_ZA_array_off3_5:
case AARCH64_OPND_SME_ZA_array_off4:
if (!parse_dual_indexed_reg (&str, REG_TYPE_ZA,
&info->indexed_za, &qualifier, 0))
[^:]*: Assembler messages:
[^:]*:5: Error: indexed vector register expected at operand 1 -- `dup v0.b,v1.b\[7\]'
-[^:]*:6: Error: expected a register at operand 1 -- `mov r0.w,r1.w'
+[^:]*:6: Error: expected a register or register list at operand 1 -- `mov r0.w,r1.w'
[^:]*:7: Error: expected an Advanced SIMD vector register at operand 2 -- `dup s0,s1\[3\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za2v\.h\[w12,#0\],p0/m,z0.h'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za4v\.s\[w12,#0\],p0/m,z0.s'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za8v\.d\[w12,#0\],p0/m,z0.d'
-[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `mova za16v\.q\[w12\],p0/m,z0.q'
+[^:]*:[0-9]+: Error: expected a register or register list at operand 1 -- `mova za16v\.q\[w12\],p0/m,z0.q'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `mova za0v\.b\[w15,#16\],p7/m,z31.b'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `mova za1v\.h\[w15,#8\],p7/m,z31.h'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `mova za3v\.s\[w15,#4\],p7/m,z31.s'
--- /dev/null
+#as: -march=armv8-a
+#source: sme2-1-invalid.s
+#error_output: sme2-1-invalid.l
--- /dev/null
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `mov 0,za\.b\[w8,0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 2 -- `mov {z0\.b-z1\.b},0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `mov {z0\.d-z1\.d},za\.q\[w8,0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: mov {z0\.d-z1\.d}, za\.d\[w8, 0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: mov {z0\.b-z1\.b}, za\.b\[w8, 0\]
+[^ :]+:[0-9]+: Info: mov {z0\.h-z1\.h}, za\.h\[w8, 0\]
+[^ :]+:[0-9]+: Info: mov {z0\.s-z1\.s}, za\.s\[w8, 0\]
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.d-z2\.d},za\.d\[w8,0\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 2 -- `mov {z0\.d-z1\.d},za\.d\[w7,0\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 2 -- `mov {z0\.d-z1\.d},za\.d\[w12,0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 2 -- `mov {z0\.d-z1\.d},za\.d\[w8,-1\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 2 -- `mov {z0\.d-z1\.d},za\.d\[w8,8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `mov {z0\.d-z3\.d},za\.q\[w8,0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: mov {z0\.d-z3\.d}, za\.d\[w8, 0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: mov {z0\.b-z3\.b}, za\.b\[w8, 0\]
+[^ :]+:[0-9]+: Info: mov {z0\.h-z3\.h}, za\.h\[w8, 0\]
+[^ :]+:[0-9]+: Info: mov {z0\.s-z3\.s}, za\.s\[w8, 0\]
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.d-z4\.d},za\.d\[w8,0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z2\.d-z5\.d},za\.d\[w8,0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z3\.d-z6\.d},za\.d\[w8,0\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 2 -- `mov {z0\.d-z3\.d},za\.d\[w7,0\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 2 -- `mov {z0\.d-z3\.d},za\.d\[w12,0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 2 -- `mov {z0\.d-z3\.d},za\.d\[w8,-1\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 2 -- `mov {z0\.d-z3\.d},za\.d\[w8,8\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.b-z2\.b},za0h\.b\[w8,0:1\]'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.b-z1\.b},za1h\.b\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.b-z1\.b},za1v\.b\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w11,0:1\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w16,0:1\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,-2:-1\]'
+[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,1:2\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,15:16\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,16:17\]'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,0\]'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,0:2\]'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,0:1,vgx2\]'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,0:1,vgx4\]'
+[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.b-z1\.b},za0\.b\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.h-z2\.h},za0h\.h\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.h-z1\.h},za2h\.h\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.h-z1\.h},za2v\.h\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w11,0:1\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w16,0:1\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,-2:-1\]'
+[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,1:2\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,7:8\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,8:9\]'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,0\]'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,0:2\]'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,0:1,vgx2\]'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,0:1,vgx4\]'
+[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.h-z1\.h},za0\.h\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.s-z2\.s},za0h\.s\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.s-z1\.s},za4h\.s\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.s-z1\.s},za4v\.s\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w11,0:1\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w16,0:1\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,-2:-1\]'
+[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,1:2\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,3:4\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,4:5\]'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,0\]'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,0:2\]'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,0:1,vgx2\]'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,0:1,vgx4\]'
+[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.s-z1\.s},za0\.s\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.d-z2\.d},za0h\.d\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.d-z1\.d},za8h\.d\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.d-z1\.d},za8v\.d\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w11,0:1\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w16,0:1\]'
+[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,-2:-1\]'
+[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,1:2\]'
+[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,2:3\]'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,0\]'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,0:2\]'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,0:1,vgx2\]'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,0:1,vgx4\]'
+[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.d-z1\.d},za0\.d\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.b-z4\.b},za0h\.b\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z2\.b-z5\.b},za0h\.b\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z3\.b-z6\.b},za0h\.b\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.b-z3\.b},za1h\.b\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.b-z3\.b},za1v\.b\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w11,0:3\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w16,0:3\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 12 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,-4:-1\]'
+[^ :]+:[0-9]+: Error: starting offset is not a multiple of 4 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,1:4\]'
+[^ :]+:[0-9]+: Error: starting offset is not a multiple of 4 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,2:5\]'
+[^ :]+:[0-9]+: Error: starting offset is not a multiple of 4 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,3:6\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 12 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,13:16\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 12 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,14:17\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 12 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,15:18\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 12 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,16:19\]'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,0\]'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,0:2\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,0:3,vgx2\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,0:3,vgx4\]'
+[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.b-z3\.b},za0\.b\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.h-z2\.h},za0h\.h\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z2\.h-z5\.h},za0h\.h\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z3\.h-z6\.h},za0h\.h\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.h-z3\.h},za2h\.h\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.h-z3\.h},za2v\.h\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w11,0:3\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w16,0:3\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 4 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,-4:-1\]'
+[^ :]+:[0-9]+: Error: starting offset is not a multiple of 4 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,1:2\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 4 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,5:8\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 4 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,6:9\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 4 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,7:10\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 4 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,8:11\]'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,0\]'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,0:2\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,0:3,vgx2\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,0:3,vgx4\]'
+[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.h-z3\.h},za0\.h\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.s-z2\.s},za0h\.s\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z2\.s-z5\.s},za0h\.s\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z3\.s-z6\.s},za0h\.s\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.s-z3\.s},za4h\.s\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.s-z3\.s},za4v\.s\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w11,0:3\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w16,0:3\]'
+[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,-4:-1\]'
+[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,1:4\]'
+[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,2:5\]'
+[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,3:6\]'
+[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,4:7\]'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,0\]'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,0:2\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,0:3,vgx2\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,0:3,vgx4\]'
+[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.s-z3\.s},za0\.s\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.d-z2\.d},za0h\.d\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z2\.d-z5\.d},za0h\.d\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z3\.d-z6\.d},za0h\.d\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.d-z3\.d},za8h\.d\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.d-z3\.d},za8v\.d\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w11,0:3\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w16,0:3\]'
+[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,-4:-1\]'
+[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,1:4\]'
+[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,2:5\]'
+[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,3:6\]'
+[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,4:7\]'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,0\]'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,0:2\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,0:3,vgx2\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,0:3,vgx4\]'
+[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.d-z3\.d},za0\.d\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `mova 0,za\.b\[w8,0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 2 -- `mova {z0\.b-z1\.b},0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `mova za\.q\[w8,0\],{z0\.q-z1\.q}'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: mova za\.b\[w8, 0\], {z0\.b-z1\.b}
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: mova za\.h\[w8, 0\], {z0\.h-z1\.h}
+[^ :]+:[0-9]+: Info: mova za\.s\[w8, 0\], {z0\.s-z1\.s}
+[^ :]+:[0-9]+: Info: mova za\.d\[w8, 0\], {z0\.d-z1\.d}
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `mova za\.d\[w7,0\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `mova za\.d\[w12,0\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `mova za\.d\[w8,-1\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `mova za\.d\[w8,8\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za\.d\[w8,0\],{z1\.d-z2\.d}'
+[^ :]+:[0-9]+: Error: operand mismatch -- `mova za\.q\[w8,0\],{z0\.q-z3\.q}'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: mova za\.b\[w8, 0\], {z0\.b-z3\.b}
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: mova za\.h\[w8, 0\], {z0\.h-z3\.h}
+[^ :]+:[0-9]+: Info: mova za\.s\[w8, 0\], {z0\.s-z3\.s}
+[^ :]+:[0-9]+: Info: mova za\.d\[w8, 0\], {z0\.d-z3\.d}
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `mova za\.d\[w7,0\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `mova za\.d\[w12,0\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `mova za\.d\[w8,-1\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `mova za\.d\[w8,8\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za\.d\[w8,0\],{z1\.d-z4\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za\.d\[w8,0\],{z2\.d-z5\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za\.d\[w8,0\],{z3\.d-z6\.d}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.b\[w8,0:1\],{z1\.b-z2\.b}'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za1h\.b\[w12,0:1\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za1v\.b\[w12,0:1\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.b\[w11,0:1\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.b\[w16,0:1\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 1 -- `mova za0h\.b\[w12,-2:-1\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.b\[w12,1:2\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 1 -- `mova za0h\.b\[w12,15:16\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 1 -- `mova za0h\.b\[w12,16:17\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,0\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,0:2\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,0:3\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.b\[w12,0:1,vgx2\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.b\[w12,0:1,vgx4\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.b\[w12,0:1\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.h\[w12,0:1\],{z1\.h-z2\.h}'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za2h\.h\[w12,0:1\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za2v\.h\[w12,0:1\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.h\[w11,0:1\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.h\[w16,0:1\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `mova za0h\.h\[w12,-2:-1\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.h\[w12,1:2\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `mova za0h\.h\[w12,7:8\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `mova za0h\.h\[w12,8:9\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0:2\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0:3\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.h\[w12,0:1,vgx2\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.h\[w12,0:1,vgx4\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.h\[w12,0:1\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.s\[w12,0:1\],{z1\.s-z2\.s}'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za4h\.s\[w12,0:1\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za4v\.s\[w12,0:1\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.s\[w11,0:1\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.s\[w16,0:1\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 1 -- `mova za0h\.s\[w12,-2:-1\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.s\[w12,1:2\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 1 -- `mova za0h\.s\[w12,3:4\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 1 -- `mova za0h\.s\[w12,4:5\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0:2\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0:3\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.s\[w12,0:1,vgx2\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.s\[w12,0:1,vgx4\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.s\[w12,0:1\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.d\[w12,0:1\],{z1\.d-z2\.d}'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za8h\.d\[w12,0:1\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za8v\.d\[w12,0:1\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.d\[w11,0:1\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.d\[w16,0:1\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,-2:-1\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,1:2\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,2:3\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0:2\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0:3\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.d\[w12,0:1,vgx2\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.d\[w12,0:1,vgx4\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.d\[w12,0:1\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.b\[w12,0:3\],{z1\.b-z4\.b}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.b\[w12,0:3\],{z2\.b-z5\.b}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.b\[w12,0:3\],{z3\.b-z6\.b}'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za1h\.b\[w12,0:3\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za1v\.b\[w12,0:3\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.b\[w11,0:3\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.b\[w16,0:3\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 1 -- `mova za0h\.b\[w12,-4:-1\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.b\[w12,1:4\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,2:5\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.b\[w12,3:6\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.b\[w12,13:16\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,14:17\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 1 -- `mova za0h\.b\[w12,15:18\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 1 -- `mova za0h\.b\[w12,16:19\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,0\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.b\[w12,0:1\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,0:2\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,0:3,vgx2\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,0:3,vgx4\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.b\[w12,0:3\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0:3\],{z1\.h-z2\.h}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.h\[w12,0:3\],{z2\.h-z5\.h}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.h\[w12,0:3\],{z3\.h-z6\.h}'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za2h\.h\[w12,0:3\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za2v\.h\[w12,0:3\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.h\[w11,0:3\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.h\[w16,0:3\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `mova za0h\.h\[w12,-4:-1\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.h\[w12,1:2\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.h\[w12,5:8\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,6:9\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `mova za0h\.h\[w12,7:10\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `mova za0h\.h\[w12,8:11\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.h\[w12,0:1\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0:2\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0:3,vgx2\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0:3,vgx4\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.h\[w12,0:3\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0:3\],{z1\.s-z2\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.s\[w12,0:3\],{z2\.s-z5\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.s\[w12,0:3\],{z3\.s-z6\.s}'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za4h\.s\[w12,0:3\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za4v\.s\[w12,0:3\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.s\[w11,0:3\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.s\[w16,0:3\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 1 -- `mova za0h\.s\[w12,-4:-1\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.s\[w12,1:4\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,2:5\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 1 -- `mova za0h\.s\[w12,3:6\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 1 -- `mova za0h\.s\[w12,4:7\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.s\[w12,0:1\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0:2\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0:3,vgx2\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0:3,vgx4\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.s\[w12,0:3\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0:3\],{z1\.d-z2\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.d\[w12,0:3\],{z2\.d-z5\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.d\[w12,0:3\],{z3\.d-z6\.d}'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za8h\.d\[w12,0:3\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za8v\.d\[w12,0:3\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.d\[w11,0:3\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.d\[w16,0:3\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,-4:-1\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,1:4\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,2:5\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,3:6\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,4:7\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.d\[w12,0:1\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0:2\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0:3,vgx2\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0:3,vgx4\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.d\[w12,0:3\],{z0\.d-z3\.d}'
--- /dev/null
+ mov 0, za.b[w8, 0]
+ mov { z0.b - z1.b }, 0
+
+ mov { z0.d - z1.d }, za.q[w8, 0]
+ mov { z1.d - z2.d }, za.d[w8, 0]
+ mov { z0.d - z1.d }, za.d[w7, 0]
+ mov { z0.d - z1.d }, za.d[w12, 0]
+ mov { z0.d - z1.d }, za.d[w8, -1]
+ mov { z0.d - z1.d }, za.d[w8, 8]
+
+ mov { z0.d - z3.d }, za.q[w8, 0]
+ mov { z1.d - z4.d }, za.d[w8, 0]
+ mov { z2.d - z5.d }, za.d[w8, 0]
+ mov { z3.d - z6.d }, za.d[w8, 0]
+ mov { z0.d - z3.d }, za.d[w7, 0]
+ mov { z0.d - z3.d }, za.d[w12, 0]
+ mov { z0.d - z3.d }, za.d[w8, -1]
+ mov { z0.d - z3.d }, za.d[w8, 8]
+
+ mov { z1.b - z2.b }, za0h.b[w8, 0:1]
+ mov { z0.b - z1.b }, za1h.b[w12, 0:1]
+ mov { z0.b - z1.b }, za1v.b[w12, 0:1]
+ mov { z0.b - z1.b }, za0h.b[w11, 0:1]
+ mov { z0.b - z1.b }, za0h.b[w16, 0:1]
+ mov { z0.b - z1.b }, za0h.b[w12, -2:-1]
+ mov { z0.b - z1.b }, za0h.b[w12, 1:2]
+ mov { z0.b - z1.b }, za0h.b[w12, 15:16]
+ mov { z0.b - z1.b }, za0h.b[w12, 16:17]
+ mov { z0.b - z1.b }, za0h.b[w12, 0]
+ mov { z0.b - z1.b }, za0h.b[w12, 0:2]
+ mov { z0.b - z1.b }, za0h.b[w12, 0:3]
+ mov { z0.b - z1.b }, za0h.b[w12, 0:1, vgx2]
+ mov { z0.b - z1.b }, za0h.b[w12, 0:1, vgx4]
+ mov { z0.b - z1.b }, za0.b[w12, 0:1]
+
+ mov { z1.h - z2.h }, za0h.h[w12, 0:1]
+ mov { z0.h - z1.h }, za2h.h[w12, 0:1]
+ mov { z0.h - z1.h }, za2v.h[w12, 0:1]
+ mov { z0.h - z1.h }, za0h.h[w11, 0:1]
+ mov { z0.h - z1.h }, za0h.h[w16, 0:1]
+ mov { z0.h - z1.h }, za0h.h[w12, -2:-1]
+ mov { z0.h - z1.h }, za0h.h[w12, 1:2]
+ mov { z0.h - z1.h }, za0h.h[w12, 7:8]
+ mov { z0.h - z1.h }, za0h.h[w12, 8:9]
+ mov { z0.h - z1.h }, za0h.h[w12, 0]
+ mov { z0.h - z1.h }, za0h.h[w12, 0:2]
+ mov { z0.h - z1.h }, za0h.h[w12, 0:3]
+ mov { z0.h - z1.h }, za0h.h[w12, 0:1, vgx2]
+ mov { z0.h - z1.h }, za0h.h[w12, 0:1, vgx4]
+ mov { z0.h - z1.h }, za0.h[w12, 0:1]
+
+ mov { z1.s - z2.s }, za0h.s[w12, 0:1]
+ mov { z0.s - z1.s }, za4h.s[w12, 0:1]
+ mov { z0.s - z1.s }, za4v.s[w12, 0:1]
+ mov { z0.s - z1.s }, za0h.s[w11, 0:1]
+ mov { z0.s - z1.s }, za0h.s[w16, 0:1]
+ mov { z0.s - z1.s }, za0h.s[w12, -2:-1]
+ mov { z0.s - z1.s }, za0h.s[w12, 1:2]
+ mov { z0.s - z1.s }, za0h.s[w12, 3:4]
+ mov { z0.s - z1.s }, za0h.s[w12, 4:5]
+ mov { z0.s - z1.s }, za0h.s[w12, 0]
+ mov { z0.s - z1.s }, za0h.s[w12, 0:2]
+ mov { z0.s - z1.s }, za0h.s[w12, 0:3]
+ mov { z0.s - z1.s }, za0h.s[w12, 0:1, vgx2]
+ mov { z0.s - z1.s }, za0h.s[w12, 0:1, vgx4]
+ mov { z0.s - z1.s }, za0.s[w12, 0:1]
+
+ mov { z1.d - z2.d }, za0h.d[w12, 0:1]
+ mov { z0.d - z1.d }, za8h.d[w12, 0:1]
+ mov { z0.d - z1.d }, za8v.d[w12, 0:1]
+ mov { z0.d - z1.d }, za0h.d[w11, 0:1]
+ mov { z0.d - z1.d }, za0h.d[w16, 0:1]
+ mov { z0.d - z1.d }, za0h.d[w12, -2:-1]
+ mov { z0.d - z1.d }, za0h.d[w12, 1:2]
+ mov { z0.d - z1.d }, za0h.d[w12, 2:3]
+ mov { z0.d - z1.d }, za0h.d[w12, 0]
+ mov { z0.d - z1.d }, za0h.d[w12, 0:2]
+ mov { z0.d - z1.d }, za0h.d[w12, 0:3]
+ mov { z0.d - z1.d }, za0h.d[w12, 0:1, vgx2]
+ mov { z0.d - z1.d }, za0h.d[w12, 0:1, vgx4]
+ mov { z0.d - z1.d }, za0.d[w12, 0:1]
+
+ mov { z1.b - z4.b }, za0h.b[w12, 0:3]
+ mov { z2.b - z5.b }, za0h.b[w12, 0:3]
+ mov { z3.b - z6.b }, za0h.b[w12, 0:3]
+ mov { z0.b - z3.b }, za1h.b[w12, 0:3]
+ mov { z0.b - z3.b }, za1v.b[w12, 0:3]
+ mov { z0.b - z3.b }, za0h.b[w11, 0:3]
+ mov { z0.b - z3.b }, za0h.b[w16, 0:3]
+ mov { z0.b - z3.b }, za0h.b[w12, -4:-1]
+ mov { z0.b - z3.b }, za0h.b[w12, 1:4]
+ mov { z0.b - z3.b }, za0h.b[w12, 2:5]
+ mov { z0.b - z3.b }, za0h.b[w12, 3:6]
+ mov { z0.b - z3.b }, za0h.b[w12, 13:16]
+ mov { z0.b - z3.b }, za0h.b[w12, 14:17]
+ mov { z0.b - z3.b }, za0h.b[w12, 15:18]
+ mov { z0.b - z3.b }, za0h.b[w12, 16:19]
+ mov { z0.b - z3.b }, za0h.b[w12, 0]
+ mov { z0.b - z3.b }, za0h.b[w12, 0:1]
+ mov { z0.b - z3.b }, za0h.b[w12, 0:2]
+ mov { z0.b - z3.b }, za0h.b[w12, 0:3, vgx2]
+ mov { z0.b - z3.b }, za0h.b[w12, 0:3, vgx4]
+ mov { z0.b - z3.b }, za0.b[w12, 0:3]
+
+ mov { z1.h - z2.h }, za0h.h[w12, 0:3]
+ mov { z2.h - z5.h }, za0h.h[w12, 0:3]
+ mov { z3.h - z6.h }, za0h.h[w12, 0:3]
+ mov { z0.h - z3.h }, za2h.h[w12, 0:3]
+ mov { z0.h - z3.h }, za2v.h[w12, 0:3]
+ mov { z0.h - z3.h }, za0h.h[w11, 0:3]
+ mov { z0.h - z3.h }, za0h.h[w16, 0:3]
+ mov { z0.h - z3.h }, za0h.h[w12, -4:-1]
+ mov { z0.h - z3.h }, za0h.h[w12, 1:2]
+ mov { z0.h - z3.h }, za0h.h[w12, 5:8]
+ mov { z0.h - z3.h }, za0h.h[w12, 6:9]
+ mov { z0.h - z3.h }, za0h.h[w12, 7:10]
+ mov { z0.h - z3.h }, za0h.h[w12, 8:11]
+ mov { z0.h - z3.h }, za0h.h[w12, 0]
+ mov { z0.h - z3.h }, za0h.h[w12, 0:1]
+ mov { z0.h - z3.h }, za0h.h[w12, 0:2]
+ mov { z0.h - z3.h }, za0h.h[w12, 0:3, vgx2]
+ mov { z0.h - z3.h }, za0h.h[w12, 0:3, vgx4]
+ mov { z0.h - z3.h }, za0.h[w12, 0:3]
+
+ mov { z1.s - z2.s }, za0h.s[w12, 0:3]
+ mov { z2.s - z5.s }, za0h.s[w12, 0:3]
+ mov { z3.s - z6.s }, za0h.s[w12, 0:3]
+ mov { z0.s - z3.s }, za4h.s[w12, 0:3]
+ mov { z0.s - z3.s }, za4v.s[w12, 0:3]
+ mov { z0.s - z3.s }, za0h.s[w11, 0:3]
+ mov { z0.s - z3.s }, za0h.s[w16, 0:3]
+ mov { z0.s - z3.s }, za0h.s[w12, -4:-1]
+ mov { z0.s - z3.s }, za0h.s[w12, 1:4]
+ mov { z0.s - z3.s }, za0h.s[w12, 2:5]
+ mov { z0.s - z3.s }, za0h.s[w12, 3:6]
+ mov { z0.s - z3.s }, za0h.s[w12, 4:7]
+ mov { z0.s - z3.s }, za0h.s[w12, 0]
+ mov { z0.s - z3.s }, za0h.s[w12, 0:1]
+ mov { z0.s - z3.s }, za0h.s[w12, 0:2]
+ mov { z0.s - z3.s }, za0h.s[w12, 0:3, vgx2]
+ mov { z0.s - z3.s }, za0h.s[w12, 0:3, vgx4]
+ mov { z0.s - z3.s }, za0.s[w12, 0:3]
+
+ mov { z1.d - z2.d }, za0h.d[w12, 0:3]
+ mov { z2.d - z5.d }, za0h.d[w12, 0:3]
+ mov { z3.d - z6.d }, za0h.d[w12, 0:3]
+ mov { z0.d - z3.d }, za8h.d[w12, 0:3]
+ mov { z0.d - z3.d }, za8v.d[w12, 0:3]
+ mov { z0.d - z3.d }, za0h.d[w11, 0:3]
+ mov { z0.d - z3.d }, za0h.d[w16, 0:3]
+ mov { z0.d - z3.d }, za0h.d[w12, -4:-1]
+ mov { z0.d - z3.d }, za0h.d[w12, 1:4]
+ mov { z0.d - z3.d }, za0h.d[w12, 2:5]
+ mov { z0.d - z3.d }, za0h.d[w12, 3:6]
+ mov { z0.d - z3.d }, za0h.d[w12, 4:7]
+ mov { z0.d - z3.d }, za0h.d[w12, 0]
+ mov { z0.d - z3.d }, za0h.d[w12, 0:1]
+ mov { z0.d - z3.d }, za0h.d[w12, 0:2]
+ mov { z0.d - z3.d }, za0h.d[w12, 0:3, vgx2]
+ mov { z0.d - z3.d }, za0h.d[w12, 0:3, vgx4]
+ mov { z0.d - z3.d }, za0.d[w12, 0:3]
+
+ mova 0, za.b[w8, 0]
+ mova { z0.b - z1.b }, 0
+
+ mova za.q[w8, 0], { z0.q - z1.q }
+ mova za.d[w7, 0], { z0.d - z1.d }
+ mova za.d[w12, 0], { z0.d - z1.d }
+ mova za.d[w8, -1], { z0.d - z1.d }
+ mova za.d[w8, 8], { z0.d - z1.d }
+ mova za.d[w8, 0], { z1.d - z2.d }
+
+ mova za.q[w8, 0], { z0.q - z3.q }
+ mova za.d[w7, 0], { z0.d - z3.d }
+ mova za.d[w12, 0], { z0.d - z3.d }
+ mova za.d[w8, -1], { z0.d - z3.d }
+ mova za.d[w8, 8], { z0.d - z3.d }
+ mova za.d[w8, 0], { z1.d - z4.d }
+ mova za.d[w8, 0], { z2.d - z5.d }
+ mova za.d[w8, 0], { z3.d - z6.d }
+
+ mova za0h.b[w8, 0:1], { z1.b - z2.b }
+ mova za1h.b[w12, 0:1], { z0.b - z1.b }
+ mova za1v.b[w12, 0:1], { z0.b - z1.b }
+ mova za0h.b[w11, 0:1], { z0.b - z1.b }
+ mova za0h.b[w16, 0:1], { z0.b - z1.b }
+ mova za0h.b[w12, -2:-1], { z0.b - z1.b }
+ mova za0h.b[w12, 1:2], { z0.b - z1.b }
+ mova za0h.b[w12, 15:16], { z0.b - z1.b }
+ mova za0h.b[w12, 16:17], { z0.b - z1.b }
+ mova za0h.b[w12, 0], { z0.b - z1.b }
+ mova za0h.b[w12, 0:2], { z0.b - z1.b }
+ mova za0h.b[w12, 0:3], { z0.b - z1.b }
+ mova za0h.b[w12, 0:1, vgx2], { z0.b - z1.b }
+ mova za0h.b[w12, 0:1, vgx4], { z0.b - z1.b }
+ mova za0.b[w12, 0:1], { z0.b - z1.b }
+
+ mova za0h.h[w12, 0:1], { z1.h - z2.h }
+ mova za2h.h[w12, 0:1], { z0.h - z1.h }
+ mova za2v.h[w12, 0:1], { z0.h - z1.h }
+ mova za0h.h[w11, 0:1], { z0.h - z1.h }
+ mova za0h.h[w16, 0:1], { z0.h - z1.h }
+ mova za0h.h[w12, -2:-1], { z0.h - z1.h }
+ mova za0h.h[w12, 1:2], { z0.h - z1.h }
+ mova za0h.h[w12, 7:8], { z0.h - z1.h }
+ mova za0h.h[w12, 8:9], { z0.h - z1.h }
+ mova za0h.h[w12, 0], { z0.h - z1.h }
+ mova za0h.h[w12, 0:2], { z0.h - z1.h }
+ mova za0h.h[w12, 0:3], { z0.h - z1.h }
+ mova za0h.h[w12, 0:1, vgx2], { z0.h - z1.h }
+ mova za0h.h[w12, 0:1, vgx4], { z0.h - z1.h }
+ mova za0.h[w12, 0:1], { z0.h - z1.h }
+
+ mova za0h.s[w12, 0:1], { z1.s - z2.s }
+ mova za4h.s[w12, 0:1], { z0.s - z1.s }
+ mova za4v.s[w12, 0:1], { z0.s - z1.s }
+ mova za0h.s[w11, 0:1], { z0.s - z1.s }
+ mova za0h.s[w16, 0:1], { z0.s - z1.s }
+ mova za0h.s[w12, -2:-1], { z0.s - z1.s }
+ mova za0h.s[w12, 1:2], { z0.s - z1.s }
+ mova za0h.s[w12, 3:4], { z0.s - z1.s }
+ mova za0h.s[w12, 4:5], { z0.s - z1.s }
+ mova za0h.s[w12, 0], { z0.s - z1.s }
+ mova za0h.s[w12, 0:2], { z0.s - z1.s }
+ mova za0h.s[w12, 0:3], { z0.s - z1.s }
+ mova za0h.s[w12, 0:1, vgx2], { z0.s - z1.s }
+ mova za0h.s[w12, 0:1, vgx4], { z0.s - z1.s }
+ mova za0.s[w12, 0:1], { z0.s - z1.s }
+
+ mova za0h.d[w12, 0:1], { z1.d - z2.d }
+ mova za8h.d[w12, 0:1], { z0.d - z1.d }
+ mova za8v.d[w12, 0:1], { z0.d - z1.d }
+ mova za0h.d[w11, 0:1], { z0.d - z1.d }
+ mova za0h.d[w16, 0:1], { z0.d - z1.d }
+ mova za0h.d[w12, -2:-1], { z0.d - z1.d }
+ mova za0h.d[w12, 1:2], { z0.d - z1.d }
+ mova za0h.d[w12, 2:3], { z0.d - z1.d }
+ mova za0h.d[w12, 0], { z0.d - z1.d }
+ mova za0h.d[w12, 0:2], { z0.d - z1.d }
+ mova za0h.d[w12, 0:3], { z0.d - z1.d }
+ mova za0h.d[w12, 0:1, vgx2], { z0.d - z1.d }
+ mova za0h.d[w12, 0:1, vgx4], { z0.d - z1.d }
+ mova za0.d[w12, 0:1], { z0.d - z1.d }
+
+ mova za0h.b[w12, 0:3], { z1.b - z4.b }
+ mova za0h.b[w12, 0:3], { z2.b - z5.b }
+ mova za0h.b[w12, 0:3], { z3.b - z6.b }
+ mova za1h.b[w12, 0:3], { z0.b - z3.b }
+ mova za1v.b[w12, 0:3], { z0.b - z3.b }
+ mova za0h.b[w11, 0:3], { z0.b - z3.b }
+ mova za0h.b[w16, 0:3], { z0.b - z3.b }
+ mova za0h.b[w12, -4:-1], { z0.b - z3.b }
+ mova za0h.b[w12, 1:4], { z0.b - z3.b }
+ mova za0h.b[w12, 2:5], { z0.b - z3.b }
+ mova za0h.b[w12, 3:6], { z0.b - z3.b }
+ mova za0h.b[w12, 13:16], { z0.b - z3.b }
+ mova za0h.b[w12, 14:17], { z0.b - z3.b }
+ mova za0h.b[w12, 15:18], { z0.b - z3.b }
+ mova za0h.b[w12, 16:19], { z0.b - z3.b }
+ mova za0h.b[w12, 0], { z0.b - z3.b }
+ mova za0h.b[w12, 0:1], { z0.b - z3.b }
+ mova za0h.b[w12, 0:2], { z0.b - z3.b }
+ mova za0h.b[w12, 0:3, vgx2], { z0.b - z3.b }
+ mova za0h.b[w12, 0:3, vgx4], { z0.b - z3.b }
+ mova za0.b[w12, 0:3], { z0.b - z3.b }
+
+ mova za0h.h[w12, 0:3], { z1.h - z2.h }
+ mova za0h.h[w12, 0:3], { z2.h - z5.h }
+ mova za0h.h[w12, 0:3], { z3.h - z6.h }
+ mova za2h.h[w12, 0:3], { z0.h - z3.h }
+ mova za2v.h[w12, 0:3], { z0.h - z3.h }
+ mova za0h.h[w11, 0:3], { z0.h - z3.h }
+ mova za0h.h[w16, 0:3], { z0.h - z3.h }
+ mova za0h.h[w12, -4:-1], { z0.h - z3.h }
+ mova za0h.h[w12, 1:2], { z0.h - z3.h }
+ mova za0h.h[w12, 5:8], { z0.h - z3.h }
+ mova za0h.h[w12, 6:9], { z0.h - z3.h }
+ mova za0h.h[w12, 7:10], { z0.h - z3.h }
+ mova za0h.h[w12, 8:11], { z0.h - z3.h }
+ mova za0h.h[w12, 0], { z0.h - z3.h }
+ mova za0h.h[w12, 0:1], { z0.h - z3.h }
+ mova za0h.h[w12, 0:2], { z0.h - z3.h }
+ mova za0h.h[w12, 0:3, vgx2], { z0.h - z3.h }
+ mova za0h.h[w12, 0:3, vgx4], { z0.h - z3.h }
+ mova za0.h[w12, 0:3], { z0.h - z3.h }
+
+ mova za0h.s[w12, 0:3], { z1.s - z2.s }
+ mova za0h.s[w12, 0:3], { z2.s - z5.s }
+ mova za0h.s[w12, 0:3], { z3.s - z6.s }
+ mova za4h.s[w12, 0:3], { z0.s - z3.s }
+ mova za4v.s[w12, 0:3], { z0.s - z3.s }
+ mova za0h.s[w11, 0:3], { z0.s - z3.s }
+ mova za0h.s[w16, 0:3], { z0.s - z3.s }
+ mova za0h.s[w12, -4:-1], { z0.s - z3.s }
+ mova za0h.s[w12, 1:4], { z0.s - z3.s }
+ mova za0h.s[w12, 2:5], { z0.s - z3.s }
+ mova za0h.s[w12, 3:6], { z0.s - z3.s }
+ mova za0h.s[w12, 4:7], { z0.s - z3.s }
+ mova za0h.s[w12, 0], { z0.s - z3.s }
+ mova za0h.s[w12, 0:1], { z0.s - z3.s }
+ mova za0h.s[w12, 0:2], { z0.s - z3.s }
+ mova za0h.s[w12, 0:3, vgx2], { z0.s - z3.s }
+ mova za0h.s[w12, 0:3, vgx4], { z0.s - z3.s }
+ mova za0.s[w12, 0:3], { z0.s - z3.s }
+
+ mova za0h.d[w12, 0:3], { z1.d - z2.d }
+ mova za0h.d[w12, 0:3], { z2.d - z5.d }
+ mova za0h.d[w12, 0:3], { z3.d - z6.d }
+ mova za8h.d[w12, 0:3], { z0.d - z3.d }
+ mova za8v.d[w12, 0:3], { z0.d - z3.d }
+ mova za0h.d[w11, 0:3], { z0.d - z3.d }
+ mova za0h.d[w16, 0:3], { z0.d - z3.d }
+ mova za0h.d[w12, -4:-1], { z0.d - z3.d }
+ mova za0h.d[w12, 1:4], { z0.d - z3.d }
+ mova za0h.d[w12, 2:5], { z0.d - z3.d }
+ mova za0h.d[w12, 3:6], { z0.d - z3.d }
+ mova za0h.d[w12, 4:7], { z0.d - z3.d }
+ mova za0h.d[w12, 0], { z0.d - z3.d }
+ mova za0h.d[w12, 0:1], { z0.d - z3.d }
+ mova za0h.d[w12, 0:2], { z0.d - z3.d }
+ mova za0h.d[w12, 0:3, vgx2], { z0.d - z3.d }
+ mova za0h.d[w12, 0:3, vgx4], { z0.d - z3.d }
+ mova za0.d[w12, 0:3], { z0.d - z3.d }
--- /dev/null
+#as: -march=armv8-a+sme
+#source: sme2-1.s
+#error_output: sme2-1-noarch.l
--- /dev/null
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z1\.b},za\.b\[w8,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z1\.h},za\.h\[w8,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z1\.s},za\.s\[w8,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za\.d\[w8,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z30\.d-z31\.d},za\.d\[w8,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za\.d\[w11,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za\.d\[w8,7\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z3\.b},za\.b\[w8,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z3\.h},za\.h\[w8,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z3\.s},za\.s\[w8,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za\.d\[w8,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z28\.d-z31\.d},za\.d\[w8,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za\.d\[w11,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za\.d\[w8,7\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z1\.b},za0h\.b\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z30\.b-z31\.b},za0h\.b\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z1\.b},za0v\.b\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z1\.b},za0h\.b\[w15,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z1\.b},za0h\.b\[w12,14:15\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z8\.b-z9\.b},za0h\.b\[w14,6:7\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z1\.h},za0h\.h\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z30\.h-z31\.h},za0h\.h\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z1\.h},za0v\.h\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z1\.h},za1h\.h\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z1\.h},za1v\.h\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z1\.h},za0h\.h\[w15,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z1\.h},za0h\.h\[w12,6:7\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z10\.h-z11\.h},za0h\.h\[w13,2:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z1\.s},za0h\.s\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z30\.s-z31\.s},za0h\.s\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z1\.s},za0v\.s\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z1\.s},za3h\.s\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z1\.s},za3v\.s\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z1\.s},za0h\.s\[w15,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z1\.s},za0h\.s\[w12,2:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z18\.s-z19\.s},za2h\.s\[w14,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za0h\.d\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z30\.d-z31\.d},za0h\.d\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za0v\.d\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za7h\.d\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za7v\.d\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za0h\.d\[w15,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z22\.d-z23\.d},za6h\.d\[w13,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z3\.b},za0h\.b\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z28\.b-z31\.b},za0h\.b\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z3\.b},za0v\.b\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z3\.b},za0h\.b\[w15,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z3\.b},za0h\.b\[w12,12:15\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z12\.b-z15\.b},za0h\.b\[w14,8:11\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z3\.h},za0h\.h\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z28\.h-z31\.h},za0h\.h\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z3\.h},za0v\.h\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z3\.h},za1h\.h\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z3\.h},za1v\.h\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z3\.h},za0h\.h\[w15,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z3\.h},za0h\.h\[w12,4:7\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z16\.h-z19\.h},za0h\.h\[w13,4:7\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z3\.s},za0h\.s\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z28\.s-z31\.s},za0h\.s\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z3\.s},za0v\.s\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z3\.s},za3h\.s\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z3\.s},za3v\.s\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z3\.s},za0h\.s\[w15,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z20\.s-z23\.s},za2h\.s\[w13,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za0h\.d\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z28\.d-z31\.d},za0h\.d\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za0v\.d\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za7h\.d\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za7v\.d\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za0h\.d\[w15,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov {z24\.d-z27\.d},za5h\.d\[w13,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.b\[w8,0\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.h\[w8,0\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.s\[w8,0\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w8,0\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w11,0\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w8,7\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w8,0\],{z30\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w9,5\],{z2\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.b\[w8,0\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.h\[w8,0\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.s\[w8,0\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w8,0\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w11,0\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w8,7\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w8,0\],{z28\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w10,1\],{z20\.d-z23\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w12,0:1\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.b\[w12,0:1\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w15,0:1\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w12,14:15\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w12,0:1\],{z30\.b-z31\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w14,6:7\],{z8\.b-z9\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w12,0:1\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.h\[w12,0:1\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za1h\.h\[w12,0:1\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za1v\.h\[w12,0:1\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w15,0:1\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w12,6:7\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w12,0:1\],{z30\.h-z31\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w13,2:3\],{z10\.h-z11\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.s\[w12,0:1\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.s\[w12,0:1\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za3h\.s\[w12,0:1\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za3v\.s\[w12,0:1\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.s\[w15,0:1\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.s\[w12,2:3\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.s\[w12,0:1\],{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za2h\.s\[w14,0:1\],{z18\.s-z19\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.d\[w12,0:1\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.d\[w12,0:1\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za7h\.d\[w12,0:1\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za7v\.d\[w12,0:1\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.d\[w15,0:1\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.d\[w12,0:1\],{z30\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za6h\.d\[w13,0:1\],{z22\.d-z23\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w12,0:3\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.b\[w12,0:3\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w15,0:3\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w12,12:15\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w12,0:3\],{z28\.b-z31\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w14,8:11\],{z12\.b-z15\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w12,0:3\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.h\[w12,0:3\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za1h\.h\[w12,0:3\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za1v\.h\[w12,0:3\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w15,0:3\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w12,4:7\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w12,0:3\],{z28\.h-z31\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w13,4:7\],{z16\.h-z19\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.s\[w12,0:3\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.s\[w12,0:3\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za3h\.s\[w12,0:3\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za3v\.s\[w12,0:3\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.s\[w15,0:3\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.s\[w12,0:3\],{z28\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za2h\.s\[w13,0:3\],{z20\.s-z23\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.d\[w12,0:3\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.d\[w12,0:3\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za7h\.d\[w12,0:3\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za7v\.d\[w12,0:3\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.d\[w15,0:3\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.d\[w12,0:3\],{z28\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov za5h\.d\[w13,0:3\],{z24\.d-z27\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z1\.b},za\.b\[w8,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z1\.h},za\.h\[w8,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z1\.s},za\.s\[w8,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za\.d\[w8,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z30\.d-z31\.d},za\.d\[w8,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za\.d\[w11,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za\.d\[w8,7\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z3\.b},za\.b\[w8,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z3\.h},za\.h\[w8,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z3\.s},za\.s\[w8,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za\.d\[w8,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z28\.d-z31\.d},za\.d\[w8,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za\.d\[w11,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za\.d\[w8,7\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z1\.b},za0h\.b\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z30\.b-z31\.b},za0h\.b\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z1\.b},za0v\.b\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z1\.b},za0h\.b\[w15,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z1\.b},za0h\.b\[w12,14:15\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z8\.b-z9\.b},za0h\.b\[w14,6:7\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z1\.h},za0h\.h\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z30\.h-z31\.h},za0h\.h\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z1\.h},za0v\.h\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z1\.h},za1h\.h\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z1\.h},za1v\.h\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z1\.h},za0h\.h\[w15,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z1\.h},za0h\.h\[w12,6:7\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z10\.h-z11\.h},za0h\.h\[w13,2:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z1\.s},za0h\.s\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z30\.s-z31\.s},za0h\.s\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z1\.s},za0v\.s\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z1\.s},za3h\.s\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z1\.s},za3v\.s\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z1\.s},za0h\.s\[w15,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z1\.s},za0h\.s\[w12,2:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z18\.s-z19\.s},za2h\.s\[w14,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za0h\.d\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z30\.d-z31\.d},za0h\.d\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za0v\.d\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za7h\.d\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za7v\.d\[w12,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za0h\.d\[w15,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z22\.d-z23\.d},za6h\.d\[w13,0:1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z3\.b},za0h\.b\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z28\.b-z31\.b},za0h\.b\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z3\.b},za0v\.b\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z3\.b},za0h\.b\[w15,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z3\.b},za0h\.b\[w12,12:15\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z12\.b-z15\.b},za0h\.b\[w14,8:11\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z3\.h},za0h\.h\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z28\.h-z31\.h},za0h\.h\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z3\.h},za0v\.h\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z3\.h},za1h\.h\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z3\.h},za1v\.h\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z3\.h},za0h\.h\[w15,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z3\.h},za0h\.h\[w12,4:7\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z16\.h-z19\.h},za0h\.h\[w13,4:7\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z3\.s},za0h\.s\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z28\.s-z31\.s},za0h\.s\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z3\.s},za0v\.s\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z3\.s},za3h\.s\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z3\.s},za3v\.s\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z3\.s},za0h\.s\[w15,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z20\.s-z23\.s},za2h\.s\[w13,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za0h\.d\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z28\.d-z31\.d},za0h\.d\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za0v\.d\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za7h\.d\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za7v\.d\[w12,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za0h\.d\[w15,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova {z24\.d-z27\.d},za5h\.d\[w13,0:3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.b\[w8,0\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.h\[w8,0\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.s\[w8,0\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w8,0\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w11,0\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w8,7\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w8,0\],{z30\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w9,5\],{z2\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.b\[w8,0\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.h\[w8,0\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.s\[w8,0\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w8,0\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w11,0\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w8,7\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w8,0\],{z28\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w10,1\],{z20\.d-z23\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w12,0:1\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.b\[w12,0:1\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w15,0:1\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w12,14:15\],{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w12,0:1\],{z30\.b-z31\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w14,6:7\],{z8\.b-z9\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w12,0:1\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.h\[w12,0:1\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za1h\.h\[w12,0:1\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za1v\.h\[w12,0:1\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w15,0:1\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w12,6:7\],{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w12,0:1\],{z30\.h-z31\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w13,2:3\],{z10\.h-z11\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.s\[w12,0:1\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.s\[w12,0:1\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za3h\.s\[w12,0:1\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za3v\.s\[w12,0:1\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.s\[w15,0:1\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.s\[w12,2:3\],{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.s\[w12,0:1\],{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za2h\.s\[w14,0:1\],{z18\.s-z19\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.d\[w12,0:1\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.d\[w12,0:1\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za7h\.d\[w12,0:1\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za7v\.d\[w12,0:1\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.d\[w15,0:1\],{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.d\[w12,0:1\],{z30\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za6h\.d\[w13,0:1\],{z22\.d-z23\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w12,0:3\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.b\[w12,0:3\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w15,0:3\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w12,12:15\],{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w12,0:3\],{z28\.b-z31\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w14,8:11\],{z12\.b-z15\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w12,0:3\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.h\[w12,0:3\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za1h\.h\[w12,0:3\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za1v\.h\[w12,0:3\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w15,0:3\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w12,4:7\],{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w12,0:3\],{z28\.h-z31\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w13,4:7\],{z16\.h-z19\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.s\[w12,0:3\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.s\[w12,0:3\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za3h\.s\[w12,0:3\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za3v\.s\[w12,0:3\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.s\[w15,0:3\],{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.s\[w12,0:3\],{z28\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za2h\.s\[w13,0:3\],{z20\.s-z23\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.d\[w12,0:3\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.d\[w12,0:3\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za7h\.d\[w12,0:3\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za7v\.d\[w12,0:3\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.d\[w15,0:3\],{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.d\[w12,0:3\],{z28\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `mova za5h\.d\[w13,0:3\],{z24\.d-z27\.d}'
--- /dev/null
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\]
+[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\]
+[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\]
+[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\]
+[^:]+: c006081e mov {z30\.d-z31\.d}, za\.d\[w8, 0, vgx2\]
+[^:]+: c0066800 mov {z0\.d-z1\.d}, za\.d\[w11, 0, vgx2\]
+[^:]+: c00608e0 mov {z0\.d-z1\.d}, za\.d\[w8, 7, vgx2\]
+[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\]
+[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\]
+[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\]
+[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\]
+[^:]+: c0060c1c mov {z28\.d-z31\.d}, za\.d\[w8, 0, vgx4\]
+[^:]+: c0066c00 mov {z0\.d-z3\.d}, za\.d\[w11, 0, vgx4\]
+[^:]+: c0060ce0 mov {z0\.d-z3\.d}, za\.d\[w8, 7, vgx4\]
+[^:]+: c0060000 mov {z0\.b-z1\.b}, za0h\.b\[w12, 0:1\]
+[^:]+: c006001e mov {z30\.b-z31\.b}, za0h\.b\[w12, 0:1\]
+[^:]+: c0068000 mov {z0\.b-z1\.b}, za0v\.b\[w12, 0:1\]
+[^:]+: c0066000 mov {z0\.b-z1\.b}, za0h\.b\[w15, 0:1\]
+[^:]+: c00600e0 mov {z0\.b-z1\.b}, za0h\.b\[w12, 14:15\]
+[^:]+: c0064068 mov {z8\.b-z9\.b}, za0h\.b\[w14, 6:7\]
+[^:]+: c0460000 mov {z0\.h-z1\.h}, za0h\.h\[w12, 0:1\]
+[^:]+: c046001e mov {z30\.h-z31\.h}, za0h\.h\[w12, 0:1\]
+[^:]+: c0468000 mov {z0\.h-z1\.h}, za0v\.h\[w12, 0:1\]
+[^:]+: c0460080 mov {z0\.h-z1\.h}, za1h\.h\[w12, 0:1\]
+[^:]+: c0468080 mov {z0\.h-z1\.h}, za1v\.h\[w12, 0:1\]
+[^:]+: c0466000 mov {z0\.h-z1\.h}, za0h\.h\[w15, 0:1\]
+[^:]+: c0460060 mov {z0\.h-z1\.h}, za0h\.h\[w12, 6:7\]
+[^:]+: c046202a mov {z10\.h-z11\.h}, za0h\.h\[w13, 2:3\]
+[^:]+: c0860000 mov {z0\.s-z1\.s}, za0h\.s\[w12, 0:1\]
+[^:]+: c086001e mov {z30\.s-z31\.s}, za0h\.s\[w12, 0:1\]
+[^:]+: c0868000 mov {z0\.s-z1\.s}, za0v\.s\[w12, 0:1\]
+[^:]+: c08600c0 mov {z0\.s-z1\.s}, za3h\.s\[w12, 0:1\]
+[^:]+: c08680c0 mov {z0\.s-z1\.s}, za3v\.s\[w12, 0:1\]
+[^:]+: c0866000 mov {z0\.s-z1\.s}, za0h\.s\[w15, 0:1\]
+[^:]+: c0860020 mov {z0\.s-z1\.s}, za0h\.s\[w12, 2:3\]
+[^:]+: c0864092 mov {z18\.s-z19\.s}, za2h\.s\[w14, 0:1\]
+[^:]+: c0c60000 mov {z0\.d-z1\.d}, za0h\.d\[w12, 0:1\]
+[^:]+: c0c6001e mov {z30\.d-z31\.d}, za0h\.d\[w12, 0:1\]
+[^:]+: c0c68000 mov {z0\.d-z1\.d}, za0v\.d\[w12, 0:1\]
+[^:]+: c0c600e0 mov {z0\.d-z1\.d}, za7h\.d\[w12, 0:1\]
+[^:]+: c0c680e0 mov {z0\.d-z1\.d}, za7v\.d\[w12, 0:1\]
+[^:]+: c0c66000 mov {z0\.d-z1\.d}, za0h\.d\[w15, 0:1\]
+[^:]+: c0c620d6 mov {z22\.d-z23\.d}, za6h\.d\[w13, 0:1\]
+[^:]+: c0060400 mov {z0\.b-z3\.b}, za0h\.b\[w12, 0:3\]
+[^:]+: c006041c mov {z28\.b-z31\.b}, za0h\.b\[w12, 0:3\]
+[^:]+: c0068400 mov {z0\.b-z3\.b}, za0v\.b\[w12, 0:3\]
+[^:]+: c0066400 mov {z0\.b-z3\.b}, za0h\.b\[w15, 0:3\]
+[^:]+: c0060460 mov {z0\.b-z3\.b}, za0h\.b\[w12, 12:15\]
+[^:]+: c006444c mov {z12\.b-z15\.b}, za0h\.b\[w14, 8:11\]
+[^:]+: c0460400 mov {z0\.h-z3\.h}, za0h\.h\[w12, 0:3\]
+[^:]+: c046041c mov {z28\.h-z31\.h}, za0h\.h\[w12, 0:3\]
+[^:]+: c0468400 mov {z0\.h-z3\.h}, za0v\.h\[w12, 0:3\]
+[^:]+: c0460440 mov {z0\.h-z3\.h}, za1h\.h\[w12, 0:3\]
+[^:]+: c0468440 mov {z0\.h-z3\.h}, za1v\.h\[w12, 0:3\]
+[^:]+: c0466400 mov {z0\.h-z3\.h}, za0h\.h\[w15, 0:3\]
+[^:]+: c0460420 mov {z0\.h-z3\.h}, za0h\.h\[w12, 4:7\]
+[^:]+: c0462430 mov {z16\.h-z19\.h}, za0h\.h\[w13, 4:7\]
+[^:]+: c0860400 mov {z0\.s-z3\.s}, za0h\.s\[w12, 0:3\]
+[^:]+: c086041c mov {z28\.s-z31\.s}, za0h\.s\[w12, 0:3\]
+[^:]+: c0868400 mov {z0\.s-z3\.s}, za0v\.s\[w12, 0:3\]
+[^:]+: c0860460 mov {z0\.s-z3\.s}, za3h\.s\[w12, 0:3\]
+[^:]+: c0868460 mov {z0\.s-z3\.s}, za3v\.s\[w12, 0:3\]
+[^:]+: c0866400 mov {z0\.s-z3\.s}, za0h\.s\[w15, 0:3\]
+[^:]+: c0862454 mov {z20\.s-z23\.s}, za2h\.s\[w13, 0:3\]
+[^:]+: c0c60400 mov {z0\.d-z3\.d}, za0h\.d\[w12, 0:3\]
+[^:]+: c0c6041c mov {z28\.d-z31\.d}, za0h\.d\[w12, 0:3\]
+[^:]+: c0c68400 mov {z0\.d-z3\.d}, za0v\.d\[w12, 0:3\]
+[^:]+: c0c604e0 mov {z0\.d-z3\.d}, za7h\.d\[w12, 0:3\]
+[^:]+: c0c684e0 mov {z0\.d-z3\.d}, za7v\.d\[w12, 0:3\]
+[^:]+: c0c66400 mov {z0\.d-z3\.d}, za0h\.d\[w15, 0:3\]
+[^:]+: c0c624b8 mov {z24\.d-z27\.d}, za5h\.d\[w13, 0:3\]
+[^:]+: c0060480 \.inst 0xc0060480 ; undefined
+[^:]+: c00604e0 \.inst 0xc00604e0 ; undefined
+[^:]+: c0460480 \.inst 0xc0460480 ; undefined
+[^:]+: c04604e0 \.inst 0xc04604e0 ; undefined
+[^:]+: c0860480 \.inst 0xc0860480 ; undefined
+[^:]+: c08604e0 \.inst 0xc08604e0 ; undefined
+[^:]+: c0c60480 mov {z0\.d-z3\.d}, za4h\.d\[w12, 0:3\]
+[^:]+: c0c604e0 mov {z0\.d-z3\.d}, za7h\.d\[w12, 0:3\]
+[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
+[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
+[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
+[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
+[^:]+: c0046800 mov za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}
+[^:]+: c0040807 mov za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}
+[^:]+: c0040bc0 mov za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}
+[^:]+: c0042845 mov za\.d\[w9, 5, vgx2\], {z2\.d-z3\.d}
+[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
+[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
+[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
+[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
+[^:]+: c0046c00 mov za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}
+[^:]+: c0040c07 mov za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}
+[^:]+: c0040f80 mov za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}
+[^:]+: c0044e81 mov za\.d\[w10, 1, vgx4\], {z20\.d-z23\.d}
+[^:]+: c0040000 mov za0h\.b\[w12, 0:1\], {z0\.b-z1\.b}
+[^:]+: c0048000 mov za0v\.b\[w12, 0:1\], {z0\.b-z1\.b}
+[^:]+: c0046000 mov za0h\.b\[w15, 0:1\], {z0\.b-z1\.b}
+[^:]+: c0040007 mov za0h\.b\[w12, 14:15\], {z0\.b-z1\.b}
+[^:]+: c00403c0 mov za0h\.b\[w12, 0:1\], {z30\.b-z31\.b}
+[^:]+: c0044103 mov za0h\.b\[w14, 6:7\], {z8\.b-z9\.b}
+[^:]+: c0440000 mov za0h\.h\[w12, 0:1\], {z0\.h-z1\.h}
+[^:]+: c0448000 mov za0v\.h\[w12, 0:1\], {z0\.h-z1\.h}
+[^:]+: c0440004 mov za1h\.h\[w12, 0:1\], {z0\.h-z1\.h}
+[^:]+: c0448004 mov za1v\.h\[w12, 0:1\], {z0\.h-z1\.h}
+[^:]+: c0446000 mov za0h\.h\[w15, 0:1\], {z0\.h-z1\.h}
+[^:]+: c0440003 mov za0h\.h\[w12, 6:7\], {z0\.h-z1\.h}
+[^:]+: c04403c0 mov za0h\.h\[w12, 0:1\], {z30\.h-z31\.h}
+[^:]+: c0442141 mov za0h\.h\[w13, 2:3\], {z10\.h-z11\.h}
+[^:]+: c0840000 mov za0h\.s\[w12, 0:1\], {z0\.s-z1\.s}
+[^:]+: c0848000 mov za0v\.s\[w12, 0:1\], {z0\.s-z1\.s}
+[^:]+: c0840006 mov za3h\.s\[w12, 0:1\], {z0\.s-z1\.s}
+[^:]+: c0848006 mov za3v\.s\[w12, 0:1\], {z0\.s-z1\.s}
+[^:]+: c0846000 mov za0h\.s\[w15, 0:1\], {z0\.s-z1\.s}
+[^:]+: c0840001 mov za0h\.s\[w12, 2:3\], {z0\.s-z1\.s}
+[^:]+: c08403c0 mov za0h\.s\[w12, 0:1\], {z30\.s-z31\.s}
+[^:]+: c0844244 mov za2h\.s\[w14, 0:1\], {z18\.s-z19\.s}
+[^:]+: c0c40000 mov za0h\.d\[w12, 0:1\], {z0\.d-z1\.d}
+[^:]+: c0c48000 mov za0v\.d\[w12, 0:1\], {z0\.d-z1\.d}
+[^:]+: c0c40007 mov za7h\.d\[w12, 0:1\], {z0\.d-z1\.d}
+[^:]+: c0c48007 mov za7v\.d\[w12, 0:1\], {z0\.d-z1\.d}
+[^:]+: c0c46000 mov za0h\.d\[w15, 0:1\], {z0\.d-z1\.d}
+[^:]+: c0c403c0 mov za0h\.d\[w12, 0:1\], {z30\.d-z31\.d}
+[^:]+: c0c422c6 mov za6h\.d\[w13, 0:1\], {z22\.d-z23\.d}
+[^:]+: c0040400 mov za0h\.b\[w12, 0:3\], {z0\.b-z3\.b}
+[^:]+: c0048400 mov za0v\.b\[w12, 0:3\], {z0\.b-z3\.b}
+[^:]+: c0046400 mov za0h\.b\[w15, 0:3\], {z0\.b-z3\.b}
+[^:]+: c0040403 mov za0h\.b\[w12, 12:15\], {z0\.b-z3\.b}
+[^:]+: c0040780 mov za0h\.b\[w12, 0:3\], {z28\.b-z31\.b}
+[^:]+: c0044582 mov za0h\.b\[w14, 8:11\], {z12\.b-z15\.b}
+[^:]+: c0440400 mov za0h\.h\[w12, 0:3\], {z0\.h-z3\.h}
+[^:]+: c0448400 mov za0v\.h\[w12, 0:3\], {z0\.h-z3\.h}
+[^:]+: c0440402 mov za1h\.h\[w12, 0:3\], {z0\.h-z3\.h}
+[^:]+: c0448402 mov za1v\.h\[w12, 0:3\], {z0\.h-z3\.h}
+[^:]+: c0446400 mov za0h\.h\[w15, 0:3\], {z0\.h-z3\.h}
+[^:]+: c0440401 mov za0h\.h\[w12, 4:7\], {z0\.h-z3\.h}
+[^:]+: c0440780 mov za0h\.h\[w12, 0:3\], {z28\.h-z31\.h}
+[^:]+: c0442601 mov za0h\.h\[w13, 4:7\], {z16\.h-z19\.h}
+[^:]+: c0840400 mov za0h\.s\[w12, 0:3\], {z0\.s-z3\.s}
+[^:]+: c0848400 mov za0v\.s\[w12, 0:3\], {z0\.s-z3\.s}
+[^:]+: c0840403 mov za3h\.s\[w12, 0:3\], {z0\.s-z3\.s}
+[^:]+: c0848403 mov za3v\.s\[w12, 0:3\], {z0\.s-z3\.s}
+[^:]+: c0846400 mov za0h\.s\[w15, 0:3\], {z0\.s-z3\.s}
+[^:]+: c0840780 mov za0h\.s\[w12, 0:3\], {z28\.s-z31\.s}
+[^:]+: c0842682 mov za2h\.s\[w13, 0:3\], {z20\.s-z23\.s}
+[^:]+: c0c40400 mov za0h\.d\[w12, 0:3\], {z0\.d-z3\.d}
+[^:]+: c0c48400 mov za0v\.d\[w12, 0:3\], {z0\.d-z3\.d}
+[^:]+: c0c40407 mov za7h\.d\[w12, 0:3\], {z0\.d-z3\.d}
+[^:]+: c0c48407 mov za7v\.d\[w12, 0:3\], {z0\.d-z3\.d}
+[^:]+: c0c46400 mov za0h\.d\[w15, 0:3\], {z0\.d-z3\.d}
+[^:]+: c0c40780 mov za0h\.d\[w12, 0:3\], {z28\.d-z31\.d}
+[^:]+: c0c42705 mov za5h\.d\[w13, 0:3\], {z24\.d-z27\.d}
+[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\]
+[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\]
+[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\]
+[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\]
+[^:]+: c006081e mov {z30\.d-z31\.d}, za\.d\[w8, 0, vgx2\]
+[^:]+: c0066800 mov {z0\.d-z1\.d}, za\.d\[w11, 0, vgx2\]
+[^:]+: c00608e0 mov {z0\.d-z1\.d}, za\.d\[w8, 7, vgx2\]
+[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\]
+[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\]
+[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\]
+[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\]
+[^:]+: c0060c1c mov {z28\.d-z31\.d}, za\.d\[w8, 0, vgx4\]
+[^:]+: c0066c00 mov {z0\.d-z3\.d}, za\.d\[w11, 0, vgx4\]
+[^:]+: c0060ce0 mov {z0\.d-z3\.d}, za\.d\[w8, 7, vgx4\]
+[^:]+: c0060000 mov {z0\.b-z1\.b}, za0h\.b\[w12, 0:1\]
+[^:]+: c006001e mov {z30\.b-z31\.b}, za0h\.b\[w12, 0:1\]
+[^:]+: c0068000 mov {z0\.b-z1\.b}, za0v\.b\[w12, 0:1\]
+[^:]+: c0066000 mov {z0\.b-z1\.b}, za0h\.b\[w15, 0:1\]
+[^:]+: c00600e0 mov {z0\.b-z1\.b}, za0h\.b\[w12, 14:15\]
+[^:]+: c0064068 mov {z8\.b-z9\.b}, za0h\.b\[w14, 6:7\]
+[^:]+: c0460000 mov {z0\.h-z1\.h}, za0h\.h\[w12, 0:1\]
+[^:]+: c046001e mov {z30\.h-z31\.h}, za0h\.h\[w12, 0:1\]
+[^:]+: c0468000 mov {z0\.h-z1\.h}, za0v\.h\[w12, 0:1\]
+[^:]+: c0460080 mov {z0\.h-z1\.h}, za1h\.h\[w12, 0:1\]
+[^:]+: c0468080 mov {z0\.h-z1\.h}, za1v\.h\[w12, 0:1\]
+[^:]+: c0466000 mov {z0\.h-z1\.h}, za0h\.h\[w15, 0:1\]
+[^:]+: c0460060 mov {z0\.h-z1\.h}, za0h\.h\[w12, 6:7\]
+[^:]+: c046202a mov {z10\.h-z11\.h}, za0h\.h\[w13, 2:3\]
+[^:]+: c0860000 mov {z0\.s-z1\.s}, za0h\.s\[w12, 0:1\]
+[^:]+: c086001e mov {z30\.s-z31\.s}, za0h\.s\[w12, 0:1\]
+[^:]+: c0868000 mov {z0\.s-z1\.s}, za0v\.s\[w12, 0:1\]
+[^:]+: c08600c0 mov {z0\.s-z1\.s}, za3h\.s\[w12, 0:1\]
+[^:]+: c08680c0 mov {z0\.s-z1\.s}, za3v\.s\[w12, 0:1\]
+[^:]+: c0866000 mov {z0\.s-z1\.s}, za0h\.s\[w15, 0:1\]
+[^:]+: c0860020 mov {z0\.s-z1\.s}, za0h\.s\[w12, 2:3\]
+[^:]+: c0864092 mov {z18\.s-z19\.s}, za2h\.s\[w14, 0:1\]
+[^:]+: c0c60000 mov {z0\.d-z1\.d}, za0h\.d\[w12, 0:1\]
+[^:]+: c0c6001e mov {z30\.d-z31\.d}, za0h\.d\[w12, 0:1\]
+[^:]+: c0c68000 mov {z0\.d-z1\.d}, za0v\.d\[w12, 0:1\]
+[^:]+: c0c600e0 mov {z0\.d-z1\.d}, za7h\.d\[w12, 0:1\]
+[^:]+: c0c680e0 mov {z0\.d-z1\.d}, za7v\.d\[w12, 0:1\]
+[^:]+: c0c66000 mov {z0\.d-z1\.d}, za0h\.d\[w15, 0:1\]
+[^:]+: c0c620d6 mov {z22\.d-z23\.d}, za6h\.d\[w13, 0:1\]
+[^:]+: c0060400 mov {z0\.b-z3\.b}, za0h\.b\[w12, 0:3\]
+[^:]+: c006041c mov {z28\.b-z31\.b}, za0h\.b\[w12, 0:3\]
+[^:]+: c0068400 mov {z0\.b-z3\.b}, za0v\.b\[w12, 0:3\]
+[^:]+: c0066400 mov {z0\.b-z3\.b}, za0h\.b\[w15, 0:3\]
+[^:]+: c0060460 mov {z0\.b-z3\.b}, za0h\.b\[w12, 12:15\]
+[^:]+: c006444c mov {z12\.b-z15\.b}, za0h\.b\[w14, 8:11\]
+[^:]+: c0460400 mov {z0\.h-z3\.h}, za0h\.h\[w12, 0:3\]
+[^:]+: c046041c mov {z28\.h-z31\.h}, za0h\.h\[w12, 0:3\]
+[^:]+: c0468400 mov {z0\.h-z3\.h}, za0v\.h\[w12, 0:3\]
+[^:]+: c0460440 mov {z0\.h-z3\.h}, za1h\.h\[w12, 0:3\]
+[^:]+: c0468440 mov {z0\.h-z3\.h}, za1v\.h\[w12, 0:3\]
+[^:]+: c0466400 mov {z0\.h-z3\.h}, za0h\.h\[w15, 0:3\]
+[^:]+: c0460420 mov {z0\.h-z3\.h}, za0h\.h\[w12, 4:7\]
+[^:]+: c0462430 mov {z16\.h-z19\.h}, za0h\.h\[w13, 4:7\]
+[^:]+: c0860400 mov {z0\.s-z3\.s}, za0h\.s\[w12, 0:3\]
+[^:]+: c086041c mov {z28\.s-z31\.s}, za0h\.s\[w12, 0:3\]
+[^:]+: c0868400 mov {z0\.s-z3\.s}, za0v\.s\[w12, 0:3\]
+[^:]+: c0860460 mov {z0\.s-z3\.s}, za3h\.s\[w12, 0:3\]
+[^:]+: c0868460 mov {z0\.s-z3\.s}, za3v\.s\[w12, 0:3\]
+[^:]+: c0866400 mov {z0\.s-z3\.s}, za0h\.s\[w15, 0:3\]
+[^:]+: c0862454 mov {z20\.s-z23\.s}, za2h\.s\[w13, 0:3\]
+[^:]+: c0c60400 mov {z0\.d-z3\.d}, za0h\.d\[w12, 0:3\]
+[^:]+: c0c6041c mov {z28\.d-z31\.d}, za0h\.d\[w12, 0:3\]
+[^:]+: c0c68400 mov {z0\.d-z3\.d}, za0v\.d\[w12, 0:3\]
+[^:]+: c0c604e0 mov {z0\.d-z3\.d}, za7h\.d\[w12, 0:3\]
+[^:]+: c0c684e0 mov {z0\.d-z3\.d}, za7v\.d\[w12, 0:3\]
+[^:]+: c0c66400 mov {z0\.d-z3\.d}, za0h\.d\[w15, 0:3\]
+[^:]+: c0c624b8 mov {z24\.d-z27\.d}, za5h\.d\[w13, 0:3\]
+[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
+[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
+[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
+[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
+[^:]+: c0046800 mov za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}
+[^:]+: c0040807 mov za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}
+[^:]+: c0040bc0 mov za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}
+[^:]+: c0042845 mov za\.d\[w9, 5, vgx2\], {z2\.d-z3\.d}
+[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
+[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
+[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
+[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
+[^:]+: c0046c00 mov za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}
+[^:]+: c0040c07 mov za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}
+[^:]+: c0040f80 mov za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}
+[^:]+: c0044e81 mov za\.d\[w10, 1, vgx4\], {z20\.d-z23\.d}
+[^:]+: c0040000 mov za0h\.b\[w12, 0:1\], {z0\.b-z1\.b}
+[^:]+: c0048000 mov za0v\.b\[w12, 0:1\], {z0\.b-z1\.b}
+[^:]+: c0046000 mov za0h\.b\[w15, 0:1\], {z0\.b-z1\.b}
+[^:]+: c0040007 mov za0h\.b\[w12, 14:15\], {z0\.b-z1\.b}
+[^:]+: c00403c0 mov za0h\.b\[w12, 0:1\], {z30\.b-z31\.b}
+[^:]+: c0044103 mov za0h\.b\[w14, 6:7\], {z8\.b-z9\.b}
+[^:]+: c0440000 mov za0h\.h\[w12, 0:1\], {z0\.h-z1\.h}
+[^:]+: c0448000 mov za0v\.h\[w12, 0:1\], {z0\.h-z1\.h}
+[^:]+: c0440004 mov za1h\.h\[w12, 0:1\], {z0\.h-z1\.h}
+[^:]+: c0448004 mov za1v\.h\[w12, 0:1\], {z0\.h-z1\.h}
+[^:]+: c0446000 mov za0h\.h\[w15, 0:1\], {z0\.h-z1\.h}
+[^:]+: c0440003 mov za0h\.h\[w12, 6:7\], {z0\.h-z1\.h}
+[^:]+: c04403c0 mov za0h\.h\[w12, 0:1\], {z30\.h-z31\.h}
+[^:]+: c0442141 mov za0h\.h\[w13, 2:3\], {z10\.h-z11\.h}
+[^:]+: c0840000 mov za0h\.s\[w12, 0:1\], {z0\.s-z1\.s}
+[^:]+: c0848000 mov za0v\.s\[w12, 0:1\], {z0\.s-z1\.s}
+[^:]+: c0840006 mov za3h\.s\[w12, 0:1\], {z0\.s-z1\.s}
+[^:]+: c0848006 mov za3v\.s\[w12, 0:1\], {z0\.s-z1\.s}
+[^:]+: c0846000 mov za0h\.s\[w15, 0:1\], {z0\.s-z1\.s}
+[^:]+: c0840001 mov za0h\.s\[w12, 2:3\], {z0\.s-z1\.s}
+[^:]+: c08403c0 mov za0h\.s\[w12, 0:1\], {z30\.s-z31\.s}
+[^:]+: c0844244 mov za2h\.s\[w14, 0:1\], {z18\.s-z19\.s}
+[^:]+: c0c40000 mov za0h\.d\[w12, 0:1\], {z0\.d-z1\.d}
+[^:]+: c0c48000 mov za0v\.d\[w12, 0:1\], {z0\.d-z1\.d}
+[^:]+: c0c40007 mov za7h\.d\[w12, 0:1\], {z0\.d-z1\.d}
+[^:]+: c0c48007 mov za7v\.d\[w12, 0:1\], {z0\.d-z1\.d}
+[^:]+: c0c46000 mov za0h\.d\[w15, 0:1\], {z0\.d-z1\.d}
+[^:]+: c0c403c0 mov za0h\.d\[w12, 0:1\], {z30\.d-z31\.d}
+[^:]+: c0c422c6 mov za6h\.d\[w13, 0:1\], {z22\.d-z23\.d}
+[^:]+: c0040400 mov za0h\.b\[w12, 0:3\], {z0\.b-z3\.b}
+[^:]+: c0048400 mov za0v\.b\[w12, 0:3\], {z0\.b-z3\.b}
+[^:]+: c0046400 mov za0h\.b\[w15, 0:3\], {z0\.b-z3\.b}
+[^:]+: c0040403 mov za0h\.b\[w12, 12:15\], {z0\.b-z3\.b}
+[^:]+: c0040780 mov za0h\.b\[w12, 0:3\], {z28\.b-z31\.b}
+[^:]+: c0044582 mov za0h\.b\[w14, 8:11\], {z12\.b-z15\.b}
+[^:]+: c0440400 mov za0h\.h\[w12, 0:3\], {z0\.h-z3\.h}
+[^:]+: c0448400 mov za0v\.h\[w12, 0:3\], {z0\.h-z3\.h}
+[^:]+: c0440402 mov za1h\.h\[w12, 0:3\], {z0\.h-z3\.h}
+[^:]+: c0448402 mov za1v\.h\[w12, 0:3\], {z0\.h-z3\.h}
+[^:]+: c0446400 mov za0h\.h\[w15, 0:3\], {z0\.h-z3\.h}
+[^:]+: c0440401 mov za0h\.h\[w12, 4:7\], {z0\.h-z3\.h}
+[^:]+: c0440780 mov za0h\.h\[w12, 0:3\], {z28\.h-z31\.h}
+[^:]+: c0442601 mov za0h\.h\[w13, 4:7\], {z16\.h-z19\.h}
+[^:]+: c0840400 mov za0h\.s\[w12, 0:3\], {z0\.s-z3\.s}
+[^:]+: c0848400 mov za0v\.s\[w12, 0:3\], {z0\.s-z3\.s}
+[^:]+: c0840403 mov za3h\.s\[w12, 0:3\], {z0\.s-z3\.s}
+[^:]+: c0848403 mov za3v\.s\[w12, 0:3\], {z0\.s-z3\.s}
+[^:]+: c0846400 mov za0h\.s\[w15, 0:3\], {z0\.s-z3\.s}
+[^:]+: c0840780 mov za0h\.s\[w12, 0:3\], {z28\.s-z31\.s}
+[^:]+: c0842682 mov za2h\.s\[w13, 0:3\], {z20\.s-z23\.s}
+[^:]+: c0c40400 mov za0h\.d\[w12, 0:3\], {z0\.d-z3\.d}
+[^:]+: c0c48400 mov za0v\.d\[w12, 0:3\], {z0\.d-z3\.d}
+[^:]+: c0c40407 mov za7h\.d\[w12, 0:3\], {z0\.d-z3\.d}
+[^:]+: c0c48407 mov za7v\.d\[w12, 0:3\], {z0\.d-z3\.d}
+[^:]+: c0c46400 mov za0h\.d\[w15, 0:3\], {z0\.d-z3\.d}
+[^:]+: c0c40780 mov za0h\.d\[w12, 0:3\], {z28\.d-z31\.d}
+[^:]+: c0c42705 mov za5h\.d\[w13, 0:3\], {z24\.d-z27\.d}
--- /dev/null
+ mov { z0.b - z1.b }, za.b[w8, 0]
+ mov { z0.h - z1.h }, za.h[w8, 0]
+ mov { z0.s - z1.s }, za.s[w8, 0]
+ mov { z0.d - z1.d }, za.d[w8, 0]
+ mov { z30.d - z31.d }, za.d[w8, 0]
+ mov { z0.d - z1.d }, za.d[w11, 0]
+ mov { z0.d - z1.d }, za.d[w8, 7]
+
+ mov { z0.b - z3.b }, za.b[w8, 0]
+ mov { z0.h - z3.h }, za.h[w8, 0]
+ mov { z0.s - z3.s }, za.s[w8, 0]
+ mov { z0.d - z3.d }, za.d[w8, 0]
+ mov { z28.d - z31.d }, za.d[w8, 0]
+ mov { z0.d - z3.d }, za.d[w11, 0]
+ mov { z0.d - z3.d }, za.d[w8, 7]
+
+ mov { z0.b - z1.b }, za0h.b[w12, 0:1]
+ mov { z30.b - z31.b }, za0h.b[w12, 0:1]
+ mov { z0.b - z1.b }, za0v.b[w12, 0:1]
+ mov { z0.b - z1.b }, za0h.b[w15, 0:1]
+ mov { z0.b - z1.b }, za0h.b[w12, 14:15]
+ mov { z8.b - z9.b }, za0h.b[w14, 6:7]
+
+ mov { z0.h - z1.h }, za0h.h[w12, 0:1]
+ mov { z30.h - z31.h }, za0h.h[w12, 0:1]
+ mov { z0.h - z1.h }, za0v.h[w12, 0:1]
+ mov { z0.h - z1.h }, za1h.h[w12, 0:1]
+ mov { z0.h - z1.h }, za1v.h[w12, 0:1]
+ mov { z0.h - z1.h }, za0h.h[w15, 0:1]
+ mov { z0.h - z1.h }, za0h.h[w12, 6:7]
+ mov { z10.h - z11.h }, za0h.h[w13, 2:3]
+
+ mov { z0.s - z1.s }, za0h.s[w12, 0:1]
+ mov { z30.s - z31.s }, za0h.s[w12, 0:1]
+ mov { z0.s - z1.s }, za0v.s[w12, 0:1]
+ mov { z0.s - z1.s }, za3h.s[w12, 0:1]
+ mov { z0.s - z1.s }, za3v.s[w12, 0:1]
+ mov { z0.s - z1.s }, za0h.s[w15, 0:1]
+ mov { z0.s - z1.s }, za0h.s[w12, 2:3]
+ mov { z18.s - z19.s }, za2h.s[w14, 0:1]
+
+ mov { z0.d - z1.d }, za0h.d[w12, 0:1]
+ mov { z30.d - z31.d }, za0h.d[w12, 0:1]
+ mov { z0.d - z1.d }, za0v.d[w12, 0:1]
+ mov { z0.d - z1.d }, za7h.d[w12, 0:1]
+ mov { z0.d - z1.d }, za7v.d[w12, 0:1]
+ mov { z0.d - z1.d }, za0h.d[w15, 0:1]
+ mov { z22.d - z23.d }, za6h.d[w13, 0:1]
+
+ mov { z0.b - z3.b }, za0h.b[w12, 0:3]
+ mov { z28.b - z31.b }, za0h.b[w12, 0:3]
+ mov { z0.b - z3.b }, za0v.b[w12, 0:3]
+ mov { z0.b - z3.b }, za0h.b[w15, 0:3]
+ mov { z0.b - z3.b }, za0h.b[w12, 12:15]
+ mov { z12.b - z15.b }, za0h.b[w14, 8:11]
+
+ mov { z0.h - z3.h }, za0h.h[w12, 0:3]
+ mov { z28.h - z31.h }, za0h.h[w12, 0:3]
+ mov { z0.h - z3.h }, za0v.h[w12, 0:3]
+ mov { z0.h - z3.h }, za1h.h[w12, 0:3]
+ mov { z0.h - z3.h }, za1v.h[w12, 0:3]
+ mov { z0.h - z3.h }, za0h.h[w15, 0:3]
+ mov { z0.h - z3.h }, za0h.h[w12, 4:7]
+ mov { z16.h - z19.h }, za0h.h[w13, 4:7]
+
+ mov { z0.s - z3.s }, za0h.s[w12, 0:3]
+ mov { z28.s - z31.s }, za0h.s[w12, 0:3]
+ mov { z0.s - z3.s }, za0v.s[w12, 0:3]
+ mov { z0.s - z3.s }, za3h.s[w12, 0:3]
+ mov { z0.s - z3.s }, za3v.s[w12, 0:3]
+ mov { z0.s - z3.s }, za0h.s[w15, 0:3]
+ mov { z20.s - z23.s }, za2h.s[w13, 0:3]
+
+ mov { z0.d - z3.d }, za0h.d[w12, 0:3]
+ mov { z28.d - z31.d }, za0h.d[w12, 0:3]
+ mov { z0.d - z3.d }, za0v.d[w12, 0:3]
+ mov { z0.d - z3.d }, za7h.d[w12, 0:3]
+ mov { z0.d - z3.d }, za7v.d[w12, 0:3]
+ mov { z0.d - z3.d }, za0h.d[w15, 0:3]
+ mov { z24.d - z27.d }, za5h.d[w13, 0:3]
+
+ // Invalid MOVAs
+ .inst 0xc0060480
+ .inst 0xc00604e0
+ .inst 0xc0460480
+ .inst 0xc04604e0
+ .inst 0xc0860480
+ .inst 0xc08604e0
+ // Valid MOVAs
+ .inst 0xc0c60480
+ .inst 0xc0c604e0
+
+ mov za.b[w8, 0], { z0.b - z1.b }
+ mov za.h[w8, 0], { z0.h - z1.h }
+ mov za.s[w8, 0], { z0.s - z1.s }
+ mov za.d[w8, 0], { z0.d - z1.d }
+ mov za.d[w11, 0], { z0.d - z1.d }
+ mov za.d[w8, 7], { z0.d - z1.d }
+ mov za.d[w8, 0], { z30.d - z31.d }
+ mov za.d[w9, 5], { z2.d - z3.d }
+
+ mov za.b[w8, 0], { z0.b - z3.b }
+ mov za.h[w8, 0], { z0.h - z3.h }
+ mov za.s[w8, 0], { z0.s - z3.s }
+ mov za.d[w8, 0], { z0.d - z3.d }
+ mov za.d[w11, 0], { z0.d - z3.d }
+ mov za.d[w8, 7], { z0.d - z3.d }
+ mov za.d[w8, 0], { z28.d - z31.d }
+ mov za.d[w10, 1], { z20.d - z23.d }
+
+ mov za0h.b[w12, 0:1], { z0.b - z1.b }
+ mov za0v.b[w12, 0:1], { z0.b - z1.b }
+ mov za0h.b[w15, 0:1], { z0.b - z1.b }
+ mov za0h.b[w12, 14:15], { z0.b - z1.b }
+ mov za0h.b[w12, 0:1], { z30.b - z31.b }
+ mov za0h.b[w14, 6:7], { z8.b - z9.b }
+
+ mov za0h.h[w12, 0:1], { z0.h - z1.h }
+ mov za0v.h[w12, 0:1], { z0.h - z1.h }
+ mov za1h.h[w12, 0:1], { z0.h - z1.h }
+ mov za1v.h[w12, 0:1], { z0.h - z1.h }
+ mov za0h.h[w15, 0:1], { z0.h - z1.h }
+ mov za0h.h[w12, 6:7], { z0.h - z1.h }
+ mov za0h.h[w12, 0:1], { z30.h - z31.h }
+ mov za0h.h[w13, 2:3], { z10.h - z11.h }
+
+ mov za0h.s[w12, 0:1], { z0.s - z1.s }
+ mov za0v.s[w12, 0:1], { z0.s - z1.s }
+ mov za3h.s[w12, 0:1], { z0.s - z1.s }
+ mov za3v.s[w12, 0:1], { z0.s - z1.s }
+ mov za0h.s[w15, 0:1], { z0.s - z1.s }
+ mov za0h.s[w12, 2:3], { z0.s - z1.s }
+ mov za0h.s[w12, 0:1], { z30.s - z31.s }
+ mov za2h.s[w14, 0:1], { z18.s - z19.s }
+
+ mov za0h.d[w12, 0:1], { z0.d - z1.d }
+ mov za0v.d[w12, 0:1], { z0.d - z1.d }
+ mov za7h.d[w12, 0:1], { z0.d - z1.d }
+ mov za7v.d[w12, 0:1], { z0.d - z1.d }
+ mov za0h.d[w15, 0:1], { z0.d - z1.d }
+ mov za0h.d[w12, 0:1], { z30.d - z31.d }
+ mov za6h.d[w13, 0:1], { z22.d - z23.d }
+
+ mov za0h.b[w12, 0:3], { z0.b - z3.b }
+ mov za0v.b[w12, 0:3], { z0.b - z3.b }
+ mov za0h.b[w15, 0:3], { z0.b - z3.b }
+ mov za0h.b[w12, 12:15], { z0.b - z3.b }
+ mov za0h.b[w12, 0:3], { z28.b - z31.b }
+ mov za0h.b[w14, 8:11], { z12.b - z15.b }
+
+ mov za0h.h[w12, 0:3], { z0.h - z3.h }
+ mov za0v.h[w12, 0:3], { z0.h - z3.h }
+ mov za1h.h[w12, 0:3], { z0.h - z3.h }
+ mov za1v.h[w12, 0:3], { z0.h - z3.h }
+ mov za0h.h[w15, 0:3], { z0.h - z3.h }
+ mov za0h.h[w12, 4:7], { z0.h - z3.h }
+ mov za0h.h[w12, 0:3], { z28.h - z31.h }
+ mov za0h.h[w13, 4:7], { z16.h - z19.h }
+
+ mov za0h.s[w12, 0:3], { z0.s - z3.s }
+ mov za0v.s[w12, 0:3], { z0.s - z3.s }
+ mov za3h.s[w12, 0:3], { z0.s - z3.s }
+ mov za3v.s[w12, 0:3], { z0.s - z3.s }
+ mov za0h.s[w15, 0:3], { z0.s - z3.s }
+ mov za0h.s[w12, 0:3], { z28.s - z31.s }
+ mov za2h.s[w13, 0:3], { z20.s - z23.s }
+
+ mov za0h.d[w12, 0:3], { z0.d - z3.d }
+ mov za0v.d[w12, 0:3], { z0.d - z3.d }
+ mov za7h.d[w12, 0:3], { z0.d - z3.d }
+ mov za7v.d[w12, 0:3], { z0.d - z3.d }
+ mov za0h.d[w15, 0:3], { z0.d - z3.d }
+ mov za0h.d[w12, 0:3], { z28.d - z31.d }
+ mov za5h.d[w13, 0:3], { z24.d - z27.d }
+
+ mova { z0.b - z1.b }, za.b[w8, 0]
+ mova { z0.h - z1.h }, za.h[w8, 0]
+ mova { z0.s - z1.s }, za.s[w8, 0]
+ mova { z0.d - z1.d }, za.d[w8, 0]
+ mova { z30.d - z31.d }, za.d[w8, 0]
+ mova { z0.d - z1.d }, za.d[w11, 0]
+ mova { z0.d - z1.d }, za.d[w8, 7]
+
+ mova { z0.b - z3.b }, za.b[w8, 0]
+ mova { z0.h - z3.h }, za.h[w8, 0]
+ mova { z0.s - z3.s }, za.s[w8, 0]
+ mova { z0.d - z3.d }, za.d[w8, 0]
+ mova { z28.d - z31.d }, za.d[w8, 0]
+ mova { z0.d - z3.d }, za.d[w11, 0]
+ mova { z0.d - z3.d }, za.d[w8, 7]
+
+ mova { z0.b - z1.b }, za0h.b[w12, 0:1]
+ mova { z30.b - z31.b }, za0h.b[w12, 0:1]
+ mova { z0.b - z1.b }, za0v.b[w12, 0:1]
+ mova { z0.b - z1.b }, za0h.b[w15, 0:1]
+ mova { z0.b - z1.b }, za0h.b[w12, 14:15]
+ mova { z8.b - z9.b }, za0h.b[w14, 6:7]
+
+ mova { z0.h - z1.h }, za0h.h[w12, 0:1]
+ mova { z30.h - z31.h }, za0h.h[w12, 0:1]
+ mova { z0.h - z1.h }, za0v.h[w12, 0:1]
+ mova { z0.h - z1.h }, za1h.h[w12, 0:1]
+ mova { z0.h - z1.h }, za1v.h[w12, 0:1]
+ mova { z0.h - z1.h }, za0h.h[w15, 0:1]
+ mova { z0.h - z1.h }, za0h.h[w12, 6:7]
+ mova { z10.h - z11.h }, za0h.h[w13, 2:3]
+
+ mova { z0.s - z1.s }, za0h.s[w12, 0:1]
+ mova { z30.s - z31.s }, za0h.s[w12, 0:1]
+ mova { z0.s - z1.s }, za0v.s[w12, 0:1]
+ mova { z0.s - z1.s }, za3h.s[w12, 0:1]
+ mova { z0.s - z1.s }, za3v.s[w12, 0:1]
+ mova { z0.s - z1.s }, za0h.s[w15, 0:1]
+ mova { z0.s - z1.s }, za0h.s[w12, 2:3]
+ mova { z18.s - z19.s }, za2h.s[w14, 0:1]
+
+ mova { z0.d - z1.d }, za0h.d[w12, 0:1]
+ mova { z30.d - z31.d }, za0h.d[w12, 0:1]
+ mova { z0.d - z1.d }, za0v.d[w12, 0:1]
+ mova { z0.d - z1.d }, za7h.d[w12, 0:1]
+ mova { z0.d - z1.d }, za7v.d[w12, 0:1]
+ mova { z0.d - z1.d }, za0h.d[w15, 0:1]
+ mova { z22.d - z23.d }, za6h.d[w13, 0:1]
+
+ mova { z0.b - z3.b }, za0h.b[w12, 0:3]
+ mova { z28.b - z31.b }, za0h.b[w12, 0:3]
+ mova { z0.b - z3.b }, za0v.b[w12, 0:3]
+ mova { z0.b - z3.b }, za0h.b[w15, 0:3]
+ mova { z0.b - z3.b }, za0h.b[w12, 12:15]
+ mova { z12.b - z15.b }, za0h.b[w14, 8:11]
+
+ mova { z0.h - z3.h }, za0h.h[w12, 0:3]
+ mova { z28.h - z31.h }, za0h.h[w12, 0:3]
+ mova { z0.h - z3.h }, za0v.h[w12, 0:3]
+ mova { z0.h - z3.h }, za1h.h[w12, 0:3]
+ mova { z0.h - z3.h }, za1v.h[w12, 0:3]
+ mova { z0.h - z3.h }, za0h.h[w15, 0:3]
+ mova { z0.h - z3.h }, za0h.h[w12, 4:7]
+ mova { z16.h - z19.h }, za0h.h[w13, 4:7]
+
+ mova { z0.s - z3.s }, za0h.s[w12, 0:3]
+ mova { z28.s - z31.s }, za0h.s[w12, 0:3]
+ mova { z0.s - z3.s }, za0v.s[w12, 0:3]
+ mova { z0.s - z3.s }, za3h.s[w12, 0:3]
+ mova { z0.s - z3.s }, za3v.s[w12, 0:3]
+ mova { z0.s - z3.s }, za0h.s[w15, 0:3]
+ mova { z20.s - z23.s }, za2h.s[w13, 0:3]
+
+ mova { z0.d - z3.d }, za0h.d[w12, 0:3]
+ mova { z28.d - z31.d }, za0h.d[w12, 0:3]
+ mova { z0.d - z3.d }, za0v.d[w12, 0:3]
+ mova { z0.d - z3.d }, za7h.d[w12, 0:3]
+ mova { z0.d - z3.d }, za7v.d[w12, 0:3]
+ mova { z0.d - z3.d }, za0h.d[w15, 0:3]
+ mova { z24.d - z27.d }, za5h.d[w13, 0:3]
+
+ mova za.b[w8, 0], { z0.b - z1.b }
+ mova za.h[w8, 0], { z0.h - z1.h }
+ mova za.s[w8, 0], { z0.s - z1.s }
+ mova za.d[w8, 0], { z0.d - z1.d }
+ mova za.d[w11, 0], { z0.d - z1.d }
+ mova za.d[w8, 7], { z0.d - z1.d }
+ mova za.d[w8, 0], { z30.d - z31.d }
+ mova za.d[w9, 5], { z2.d - z3.d }
+
+ mova za.b[w8, 0], { z0.b - z3.b }
+ mova za.h[w8, 0], { z0.h - z3.h }
+ mova za.s[w8, 0], { z0.s - z3.s }
+ mova za.d[w8, 0], { z0.d - z3.d }
+ mova za.d[w11, 0], { z0.d - z3.d }
+ mova za.d[w8, 7], { z0.d - z3.d }
+ mova za.d[w8, 0], { z28.d - z31.d }
+ mova za.d[w10, 1], { z20.d - z23.d }
+
+ mova za0h.b[w12, 0:1], { z0.b - z1.b }
+ mova za0v.b[w12, 0:1], { z0.b - z1.b }
+ mova za0h.b[w15, 0:1], { z0.b - z1.b }
+ mova za0h.b[w12, 14:15], { z0.b - z1.b }
+ mova za0h.b[w12, 0:1], { z30.b - z31.b }
+ mova za0h.b[w14, 6:7], { z8.b - z9.b }
+
+ mova za0h.h[w12, 0:1], { z0.h - z1.h }
+ mova za0v.h[w12, 0:1], { z0.h - z1.h }
+ mova za1h.h[w12, 0:1], { z0.h - z1.h }
+ mova za1v.h[w12, 0:1], { z0.h - z1.h }
+ mova za0h.h[w15, 0:1], { z0.h - z1.h }
+ mova za0h.h[w12, 6:7], { z0.h - z1.h }
+ mova za0h.h[w12, 0:1], { z30.h - z31.h }
+ mova za0h.h[w13, 2:3], { z10.h - z11.h }
+
+ mova za0h.s[w12, 0:1], { z0.s - z1.s }
+ mova za0v.s[w12, 0:1], { z0.s - z1.s }
+ mova za3h.s[w12, 0:1], { z0.s - z1.s }
+ mova za3v.s[w12, 0:1], { z0.s - z1.s }
+ mova za0h.s[w15, 0:1], { z0.s - z1.s }
+ mova za0h.s[w12, 2:3], { z0.s - z1.s }
+ mova za0h.s[w12, 0:1], { z30.s - z31.s }
+ mova za2h.s[w14, 0:1], { z18.s - z19.s }
+
+ mova za0h.d[w12, 0:1], { z0.d - z1.d }
+ mova za0v.d[w12, 0:1], { z0.d - z1.d }
+ mova za7h.d[w12, 0:1], { z0.d - z1.d }
+ mova za7v.d[w12, 0:1], { z0.d - z1.d }
+ mova za0h.d[w15, 0:1], { z0.d - z1.d }
+ mova za0h.d[w12, 0:1], { z30.d - z31.d }
+ mova za6h.d[w13, 0:1], { z22.d - z23.d }
+
+ mova za0h.b[w12, 0:3], { z0.b - z3.b }
+ mova za0v.b[w12, 0:3], { z0.b - z3.b }
+ mova za0h.b[w15, 0:3], { z0.b - z3.b }
+ mova za0h.b[w12, 12:15], { z0.b - z3.b }
+ mova za0h.b[w12, 0:3], { z28.b - z31.b }
+ mova za0h.b[w14, 8:11], { z12.b - z15.b }
+
+ mova za0h.h[w12, 0:3], { z0.h - z3.h }
+ mova za0v.h[w12, 0:3], { z0.h - z3.h }
+ mova za1h.h[w12, 0:3], { z0.h - z3.h }
+ mova za1v.h[w12, 0:3], { z0.h - z3.h }
+ mova za0h.h[w15, 0:3], { z0.h - z3.h }
+ mova za0h.h[w12, 4:7], { z0.h - z3.h }
+ mova za0h.h[w12, 0:3], { z28.h - z31.h }
+ mova za0h.h[w13, 4:7], { z16.h - z19.h }
+
+ mova za0h.s[w12, 0:3], { z0.s - z3.s }
+ mova za0v.s[w12, 0:3], { z0.s - z3.s }
+ mova za3h.s[w12, 0:3], { z0.s - z3.s }
+ mova za3v.s[w12, 0:3], { z0.s - z3.s }
+ mova za0h.s[w15, 0:3], { z0.s - z3.s }
+ mova za0h.s[w12, 0:3], { z28.s - z31.s }
+ mova za2h.s[w13, 0:3], { z20.s - z23.s }
+
+ mova za0h.d[w12, 0:3], { z0.d - z3.d }
+ mova za0v.d[w12, 0:3], { z0.d - z3.d }
+ mova za7h.d[w12, 0:3], { z0.d - z3.d }
+ mova za7v.d[w12, 0:3], { z0.d - z3.d }
+ mova za0h.d[w15, 0:3], { z0.d - z3.d }
+ mova za0h.d[w12, 0:3], { z28.d - z31.d }
+ mova za5h.d[w13, 0:3], { z24.d - z27.d }
AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
+ AARCH64_OPND_SME_Zdnx2, /* SVE vector register list from [4:1]*2. */
+ AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */
+ AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */
+ AARCH64_OPND_SME_Znx4, /* SVE vector register list from [9:7]*4. */
AARCH64_OPND_SME_ZAda_2b, /* SME <ZAda>.S, 2-bits. */
AARCH64_OPND_SME_ZAda_3b, /* SME <ZAda>.D, 3-bits. */
AARCH64_OPND_SME_ZA_HV_idx_src, /* SME source ZA tile vector. */
+ AARCH64_OPND_SME_ZA_HV_idx_srcxN, /* SME N source ZA tile vectors. */
AARCH64_OPND_SME_ZA_HV_idx_dest, /* SME destination ZA tile vector. */
+ AARCH64_OPND_SME_ZA_HV_idx_destxN, /* SME N dest ZA tile vectors. */
AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */
AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */
AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */
+ AARCH64_OPND_SME_ZA_array_off3_0, /* SME ZA[<Wv>{, #<imm3>}]. */
+ AARCH64_OPND_SME_ZA_array_off3_5, /* SME ZA[<Wv>{, #<imm3>}]. */
AARCH64_OPND_SME_ZA_array_off4, /* SME ZA[<Wv>{, #<imm>}]. */
AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */
AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */
sme_mov,
sme_ldr,
sme_psel,
+ sme_size_22,
sme_str,
sme_start,
sme_stop,
+ sme2_mov,
sve_cpy,
sve_index,
sve_limm,
case 203:
case 209:
case 212:
- case 214:
- case 215:
case 218:
+ case 219:
+ case 224:
return aarch64_ins_regno (self, info, code, inst, errors);
case 15:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
case 33:
case 34:
case 35:
- case 226:
+ case 234:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 36:
return aarch64_ins_reglist (self, info, code, inst, errors);
case 192:
case 193:
case 194:
- case 219:
case 225:
- case 230:
- case 231:
+ case 233:
+ case 238:
+ case 239:
return aarch64_ins_imm (self, info, code, inst, errors);
case 44:
case 45:
case 211:
case 213:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
+ case 214:
+ case 215:
case 216:
case 217:
+ return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
case 220:
+ case 222:
+ case 226:
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
case 221:
- return aarch64_ins_sme_za_array (self, info, code, inst, errors);
- case 222:
- return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 223:
- return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
- case 224:
- return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 227:
case 228:
case 229:
+ return aarch64_ins_sme_za_array (self, info, code, inst, errors);
+ case 230:
+ return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
+ case 231:
+ return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
+ case 232:
+ return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 235:
+ case 236:
+ case 237:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
default: assert (0); abort ();
}
return true;
}
+bool
+aarch64_ins_sve_aligned_reglist (const aarch64_operand *self,
+ const aarch64_opnd_info *info,
+ aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ unsigned int num_regs = get_operand_specific_data (self);
+ unsigned int val = info->reglist.first_regno;
+ insert_field (self->fields[0], code, val / num_regs, 0);
+ return true;
+}
+
/* Encode an SVE CPY/DUP immediate. */
bool
aarch64_ins_sve_asimm (const aarch64_operand *self,
return true;
}
+bool
+aarch64_ins_sme_za_hv_tiles_range (const aarch64_operand *self,
+ const aarch64_opnd_info *info,
+ aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors
+ ATTRIBUTE_UNUSED)
+{
+ int ebytes = aarch64_get_qualifier_esize (info->qualifier);
+ int range_size = get_opcode_dependent_value (inst->opcode);
+ int fld_v = info->indexed_za.v;
+ int fld_rv = info->indexed_za.index.regno - 12;
+ int imm = info->indexed_za.index.imm;
+ int max_value = 16 / range_size / ebytes;
+
+ if (max_value == 0)
+ max_value = 1;
+
+ assert (imm % range_size == 0 && (imm / range_size) < max_value);
+ int fld_zan_imm = (info->indexed_za.regno * max_value) | (imm / range_size);
+ assert (fld_zan_imm < (range_size == 4 && ebytes < 8 ? 4 : 8));
+
+ insert_field (self->fields[0], code, fld_v, 0);
+ insert_field (self->fields[1], code, fld_rv, 0);
+ insert_field (self->fields[2], code, fld_zan_imm, 0);
+
+ return true;
+}
+
/* Encode in SME instruction ZERO list of up to eight 64-bit element tile names
separated by commas, encoded in the "imm8" field.
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
- int regno = info->indexed_za.index.regno - 12;
+ int regno = info->indexed_za.index.regno & 3;
int imm = info->indexed_za.index.imm;
insert_field (self->fields[0], code, regno, 0);
insert_field (self->fields[1], code, imm, 0);
/* The variant is encoded as part of the immediate. */
break;
+ case sme_size_22:
+ insert_field (FLD_SME_size_22, &inst->value,
+ aarch64_get_variant (inst), 0);
+ break;
+
case sve_cpy:
insert_fields (&inst->value, aarch64_get_variant (inst),
0, 2, FLD_SVE_M_14, FLD_size);
break;
case sve_limm:
+ case sme2_mov:
/* For sve_limm, the .B, .H, and .S forms are just a convenience
and depend on the immediate. They don't have a separate
encoding. */
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_sxtw);
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_uxtw);
AARCH64_DECL_OPD_INSERTER (ins_sve_aimm);
+AARCH64_DECL_OPD_INSERTER (ins_sve_aligned_reglist);
AARCH64_DECL_OPD_INSERTER (ins_sve_asimm);
AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_one);
AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_two);
AARCH64_DECL_OPD_INSERTER (ins_sve_shlimm);
AARCH64_DECL_OPD_INSERTER (ins_sve_shrimm);
AARCH64_DECL_OPD_INSERTER (ins_sme_za_hv_tiles);
+AARCH64_DECL_OPD_INSERTER (ins_sme_za_hv_tiles_range);
AARCH64_DECL_OPD_INSERTER (ins_sme_za_list);
AARCH64_DECL_OPD_INSERTER (ins_sme_za_array);
AARCH64_DECL_OPD_INSERTER (ins_sme_addr_ri_u4xvl);
{
if (((word >> 17) & 0x1) == 0)
{
- if (((word >> 19) & 0x1) == 0)
+ if (((word >> 18) & 0x1) == 0)
{
- if (((word >> 20) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000xx000x0xxxxxxxxxxxxxxxxx
- mov. */
- return 2389;
- }
- else
+ if (((word >> 19) & 0x1) == 0)
{
- if (((word >> 16) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
- if (((word >> 22) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000x0010x00xxxxxxxxxxxxxxxx
- addha. */
- return 2357;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000x1010x00xxxxxxxxxxxxxxxx
- addha. */
- return 2358;
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx00000xxxxxxxxxxxxxxxxx
+ mov. */
+ return 2389;
}
else
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 16) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000x0010x01xxxxxxxxxxxxxxxx
- addva. */
- return 2361;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x0010000xxxxxxxxxxxxxxxx
+ addha. */
+ return 2357;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x1010000xxxxxxxxxxxxxxxx
+ addha. */
+ return 2358;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000x1010x01xxxxxxxxxxxxxxxx
- addva. */
- return 2362;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x0010001xxxxxxxxxxxxxxxx
+ addva. */
+ return 2361;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x1010001xxxxxxxxxxxxxxxx
+ addva. */
+ return 2362;
+ }
}
}
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx0x100xxxxxxxxxxxxxxxxx
+ zero. */
+ return 2392;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000xx0x1x0xxxxxxxxxxxxxxxxx
- zero. */
- return 2392;
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx0xx10xxxxx00xxxxxxxxxx
+ mov. */
+ return 2426;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx0xx10xxxxx10xxxxxxxxxx
+ mov. */
+ return 2424;
+ }
+ }
+ else
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx0xx10xxxxx01xxxxxxxxxx
+ mov. */
+ return 2427;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx0xx10xxxxx11xxxxxxxxxx
+ mov. */
+ return 2425;
+ }
+ }
}
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000xx0xxx1xxxxxxxxxxxxxxxxx
- mov. */
- return 2388;
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx0xx01xxxxxxxxxxxxxxxxx
+ mov. */
+ return 2388;
+ }
+ else
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx0xx11xxxxx00xxxxxxxxxx
+ mov. */
+ return 2422;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx0xx11xxxxx10xxxxxxxxxx
+ mov. */
+ return 2420;
+ }
+ }
+ else
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx0xx11xxxxx01xxxxxxxxxx
+ mov. */
+ return 2423;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx0xx11xxxxx11xxxxxxxxxx
+ mov. */
+ return 2421;
+ }
+ }
+ }
}
}
}
10987654321098765432109876543210
00011001000xxxxxxxxx00xxxxxxxxxx
stlurb. */
- return 2460;
+ return 2476;
}
else
{
10987654321098765432109876543210
10011001000xxxxxxxxx00xxxxxxxxxx
stlur. */
- return 2468;
+ return 2484;
}
}
else
10987654321098765432109876543210
01011001000xxxxxxxxx00xxxxxxxxxx
stlurh. */
- return 2464;
+ return 2480;
}
else
{
10987654321098765432109876543210
11011001000xxxxxxxxx00xxxxxxxxxx
stlur. */
- return 2471;
+ return 2487;
}
}
}
10987654321098765432109876543210
xx011001000xxxxx0000x1xxxxxxxxxx
cpyfp. */
- return 2520;
+ return 2536;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1000x1xxxxxxxxxx
cpyfprn. */
- return 2526;
+ return 2542;
}
}
else
10987654321098765432109876543210
xx011001000xxxxx0100x1xxxxxxxxxx
cpyfpwn. */
- return 2523;
+ return 2539;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1100x1xxxxxxxxxx
cpyfpn. */
- return 2529;
+ return 2545;
}
}
}
10987654321098765432109876543210
xx011001000xxxxx0010x1xxxxxxxxxx
cpyfprt. */
- return 2544;
+ return 2560;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1010x1xxxxxxxxxx
cpyfprtrn. */
- return 2550;
+ return 2566;
}
}
else
10987654321098765432109876543210
xx011001000xxxxx0110x1xxxxxxxxxx
cpyfprtwn. */
- return 2547;
+ return 2563;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1110x1xxxxxxxxxx
cpyfprtn. */
- return 2553;
+ return 2569;
}
}
}
10987654321098765432109876543210
xx011001000xxxxx0001x1xxxxxxxxxx
cpyfpwt. */
- return 2532;
+ return 2548;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1001x1xxxxxxxxxx
cpyfpwtrn. */
- return 2538;
+ return 2554;
}
}
else
10987654321098765432109876543210
xx011001000xxxxx0101x1xxxxxxxxxx
cpyfpwtwn. */
- return 2535;
+ return 2551;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1101x1xxxxxxxxxx
cpyfpwtn. */
- return 2541;
+ return 2557;
}
}
}
10987654321098765432109876543210
xx011001000xxxxx0011x1xxxxxxxxxx
cpyfpt. */
- return 2556;
+ return 2572;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1011x1xxxxxxxxxx
cpyfptrn. */
- return 2562;
+ return 2578;
}
}
else
10987654321098765432109876543210
xx011001000xxxxx0111x1xxxxxxxxxx
cpyfptwn. */
- return 2559;
+ return 2575;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1111x1xxxxxxxxxx
cpyfptn. */
- return 2565;
+ return 2581;
}
}
}
10987654321098765432109876543210
00011001010xxxxxxxxx00xxxxxxxxxx
ldapurb. */
- return 2461;
+ return 2477;
}
else
{
10987654321098765432109876543210
10011001010xxxxxxxxx00xxxxxxxxxx
ldapur. */
- return 2469;
+ return 2485;
}
}
else
10987654321098765432109876543210
01011001010xxxxxxxxx00xxxxxxxxxx
ldapurh. */
- return 2465;
+ return 2481;
}
else
{
10987654321098765432109876543210
11011001010xxxxxxxxx00xxxxxxxxxx
ldapur. */
- return 2472;
+ return 2488;
}
}
}
10987654321098765432109876543210
xx011001010xxxxx0000x1xxxxxxxxxx
cpyfm. */
- return 2521;
+ return 2537;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1000x1xxxxxxxxxx
cpyfmrn. */
- return 2527;
+ return 2543;
}
}
else
10987654321098765432109876543210
xx011001010xxxxx0100x1xxxxxxxxxx
cpyfmwn. */
- return 2524;
+ return 2540;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1100x1xxxxxxxxxx
cpyfmn. */
- return 2530;
+ return 2546;
}
}
}
10987654321098765432109876543210
xx011001010xxxxx0010x1xxxxxxxxxx
cpyfmrt. */
- return 2545;
+ return 2561;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1010x1xxxxxxxxxx
cpyfmrtrn. */
- return 2551;
+ return 2567;
}
}
else
10987654321098765432109876543210
xx011001010xxxxx0110x1xxxxxxxxxx
cpyfmrtwn. */
- return 2548;
+ return 2564;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1110x1xxxxxxxxxx
cpyfmrtn. */
- return 2554;
+ return 2570;
}
}
}
10987654321098765432109876543210
xx011001010xxxxx0001x1xxxxxxxxxx
cpyfmwt. */
- return 2533;
+ return 2549;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1001x1xxxxxxxxxx
cpyfmwtrn. */
- return 2539;
+ return 2555;
}
}
else
10987654321098765432109876543210
xx011001010xxxxx0101x1xxxxxxxxxx
cpyfmwtwn. */
- return 2536;
+ return 2552;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1101x1xxxxxxxxxx
cpyfmwtn. */
- return 2542;
+ return 2558;
}
}
}
10987654321098765432109876543210
xx011001010xxxxx0011x1xxxxxxxxxx
cpyfmt. */
- return 2557;
+ return 2573;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1011x1xxxxxxxxxx
cpyfmtrn. */
- return 2563;
+ return 2579;
}
}
else
10987654321098765432109876543210
xx011001010xxxxx0111x1xxxxxxxxxx
cpyfmtwn. */
- return 2560;
+ return 2576;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1111x1xxxxxxxxxx
cpyfmtn. */
- return 2566;
+ return 2582;
}
}
}
10987654321098765432109876543210
00011001100xxxxxxxxx00xxxxxxxxxx
ldapursb. */
- return 2463;
+ return 2479;
}
else
{
10987654321098765432109876543210
10011001100xxxxxxxxx00xxxxxxxxxx
ldapursw. */
- return 2470;
+ return 2486;
}
}
else
10987654321098765432109876543210
x1011001100xxxxxxxxx00xxxxxxxxxx
ldapursh. */
- return 2467;
+ return 2483;
}
}
else
10987654321098765432109876543210
x0011001110xxxxxxxxx00xxxxxxxxxx
ldapursb. */
- return 2462;
+ return 2478;
}
else
{
10987654321098765432109876543210
x1011001110xxxxxxxxx00xxxxxxxxxx
ldapursh. */
- return 2466;
+ return 2482;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0000x1xxxxxxxxxx
cpyfe. */
- return 2522;
+ return 2538;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0000x1xxxxxxxxxx
setp. */
- return 2616;
+ return 2632;
}
}
else
10987654321098765432109876543210
xx011001100xxxxx1000x1xxxxxxxxxx
cpyfern. */
- return 2528;
+ return 2544;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx1000x1xxxxxxxxxx
sete. */
- return 2618;
+ return 2634;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0100x1xxxxxxxxxx
cpyfewn. */
- return 2525;
+ return 2541;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0100x1xxxxxxxxxx
setm. */
- return 2617;
+ return 2633;
}
}
else
10987654321098765432109876543210
xx0110011x0xxxxx1100x1xxxxxxxxxx
cpyfen. */
- return 2531;
+ return 2547;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0010x1xxxxxxxxxx
cpyfert. */
- return 2546;
+ return 2562;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0010x1xxxxxxxxxx
setpn. */
- return 2622;
+ return 2638;
}
}
else
10987654321098765432109876543210
xx011001100xxxxx1010x1xxxxxxxxxx
cpyfertrn. */
- return 2552;
+ return 2568;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx1010x1xxxxxxxxxx
seten. */
- return 2624;
+ return 2640;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0110x1xxxxxxxxxx
cpyfertwn. */
- return 2549;
+ return 2565;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0110x1xxxxxxxxxx
setmn. */
- return 2623;
+ return 2639;
}
}
else
10987654321098765432109876543210
xx0110011x0xxxxx1110x1xxxxxxxxxx
cpyfertn. */
- return 2555;
+ return 2571;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0001x1xxxxxxxxxx
cpyfewt. */
- return 2534;
+ return 2550;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0001x1xxxxxxxxxx
setpt. */
- return 2619;
+ return 2635;
}
}
else
10987654321098765432109876543210
xx011001100xxxxx1001x1xxxxxxxxxx
cpyfewtrn. */
- return 2540;
+ return 2556;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx1001x1xxxxxxxxxx
setet. */
- return 2621;
+ return 2637;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0101x1xxxxxxxxxx
cpyfewtwn. */
- return 2537;
+ return 2553;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0101x1xxxxxxxxxx
setmt. */
- return 2620;
+ return 2636;
}
}
else
10987654321098765432109876543210
xx0110011x0xxxxx1101x1xxxxxxxxxx
cpyfewtn. */
- return 2543;
+ return 2559;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0011x1xxxxxxxxxx
cpyfet. */
- return 2558;
+ return 2574;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0011x1xxxxxxxxxx
setptn. */
- return 2625;
+ return 2641;
}
}
else
10987654321098765432109876543210
xx011001100xxxxx1011x1xxxxxxxxxx
cpyfetrn. */
- return 2564;
+ return 2580;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx1011x1xxxxxxxxxx
setetn. */
- return 2627;
+ return 2643;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0111x1xxxxxxxxxx
cpyfetwn. */
- return 2561;
+ return 2577;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0111x1xxxxxxxxxx
setmtn. */
- return 2626;
+ return 2642;
}
}
else
10987654321098765432109876543210
xx0110011x0xxxxx1111x1xxxxxxxxxx
cpyfetn. */
- return 2567;
+ return 2583;
}
}
}
10987654321098765432109876543210
x1x11010110xxxx0x01000xxxxxxxxxx
abs. */
- return 2645;
+ return 2661;
}
else
{
10987654321098765432109876543210
xxx11010110xxxxxx11000xxxxxxxxxx
smax. */
- return 2648;
+ return 2664;
}
}
}
10987654321098765432109876543210
xxx11010x00xxxxxx0xx10xxxxxxxxxx
setf8. */
- return 2458;
+ return 2474;
}
else
{
10987654321098765432109876543210
xxx11010x00xxxxxx1xx10xxxxxxxxxx
setf16. */
- return 2459;
+ return 2475;
}
}
else
10987654321098765432109876543210
xxx11010110xxxxxx11010xxxxxxxxxx
smin. */
- return 2650;
+ return 2666;
}
}
}
10987654321098765432109876543210
xxx11010110xxxx0x00110xxxxxxxxxx
ctz. */
- return 2647;
+ return 2663;
}
else
{
10987654321098765432109876543210
xxx11010000xxxxxxxxx01xxxxxxxxxx
rmif. */
- return 2457;
+ return 2473;
}
else
{
10987654321098765432109876543210
xxx11010x10xxxxxx11001xxxxxxxxxx
umax. */
- return 2649;
+ return 2665;
}
}
}
10987654321098765432109876543210
xxx11010xx0xxxxxx11011xxxxxxxxxx
umin. */
- return 2651;
+ return 2667;
}
}
}
10987654321098765432109876543210
xxx11010xx0xxxx0x00111xxxxxxxxxx
cnt. */
- return 2646;
+ return 2662;
}
else
{
10987654321098765432109876543210
010001x01x1xxxxx000110xxxxxxxxxx
usdot. */
- return 2477;
+ return 2493;
}
}
}
10987654321098765432109876543210
010001x01x1xxxxx000111xxxxxxxxxx
sudot. */
- return 2478;
+ return 2494;
}
}
}
10987654321098765432109876543210
010001x0xx0xxxxx011110xxxxxxxxxx
usdot. */
- return 2476;
+ return 2492;
}
}
}
10987654321098765432109876543210
011001x0100xxx10101xxxxxxxxxxxxx
bfcvtnt. */
- return 2505;
+ return 2521;
}
}
else
10987654321098765432109876543210
101001x00x1xxxxxx00xxxxxxxxxxxxx
ld1rob. */
- return 2481;
+ return 2497;
}
else
{
10987654321098765432109876543210
101001x01x1xxxxxx00xxxxxxxxxxxxx
ld1roh. */
- return 2482;
+ return 2498;
}
}
else
10987654321098765432109876543210
011001x0011xxxxx010xxxxxxxxxxxxx
bfdot. */
- return 2502;
+ return 2518;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx010xx0xxxxxxxxxx
bfmlalb. */
- return 2509;
+ return 2525;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx010xx1xxxxxxxxxx
bfmlalt. */
- return 2508;
+ return 2524;
}
}
else
10987654321098765432109876543210
x11001x0011xxxxx1x0xxxxxxxxxxxxx
bfdot. */
- return 2501;
+ return 2517;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx1x0xx0xxxxxxxxxx
bfmlalb. */
- return 2507;
+ return 2523;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx1x0xx1xxxxxxxxxx
bfmlalt. */
- return 2506;
+ return 2522;
}
}
else
10987654321098765432109876543210
101001x00x1xxxxx001xxxxxxxxxxxxx
ld1rob. */
- return 2485;
+ return 2501;
}
else
{
10987654321098765432109876543210
101001x01x1xxxxx001xxxxxxxxxxxxx
ld1roh. */
- return 2486;
+ return 2502;
}
}
else
10987654321098765432109876543210
011001x0101xxxxx111xxxxxxxxxxxxx
fmmla. */
- return 2479;
+ return 2495;
}
else
{
10987654321098765432109876543210
011001x0011xxxxx111xxxxxxxxxxxxx
bfmmla. */
- return 2503;
+ return 2519;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx111xxxxxxxxxxxxx
fmmla. */
- return 2480;
+ return 2496;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000x00xxxxxxxxxx
zip1. */
- return 2489;
+ return 2505;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000010xxxxxxxxxx
uzp1. */
- return 2491;
+ return 2507;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000110xxxxxxxxxx
trn1. */
- return 2493;
+ return 2509;
}
}
}
10987654321098765432109876543210
000001x1101xxxxx000x01xxxxxxxxxx
zip2. */
- return 2490;
+ return 2506;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000011xxxxxxxxxx
uzp2. */
- return 2492;
+ return 2508;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000111xxxxxxxxxx
trn2. */
- return 2494;
+ return 2510;
}
}
}
10987654321098765432109876543210
010001x1000xxxxx100110xxxxxxxxxx
smmla. */
- return 2473;
+ return 2489;
}
else
{
10987654321098765432109876543210
010001x1100xxxxx100110xxxxxxxxxx
usmmla. */
- return 2475;
+ return 2491;
}
}
else
10987654321098765432109876543210
010001x1x10xxxxx100110xxxxxxxxxx
ummla. */
- return 2474;
+ return 2490;
}
}
}
10987654321098765432109876543210
101001x10x1xxxxx000xxxxxxxxxxxxx
ld1row. */
- return 2483;
+ return 2499;
}
else
{
10987654321098765432109876543210
101001x11x1xxxxx000xxxxxxxxxxxxx
ld1rod. */
- return 2484;
+ return 2500;
}
}
}
10987654321098765432109876543210
101001x10x1xxxxx001xxxxxxxxxxxxx
ld1row. */
- return 2487;
+ return 2503;
}
else
{
10987654321098765432109876543210
101001x11x1xxxxx001xxxxxxxxxxxxx
ld1rod. */
- return 2488;
+ return 2504;
}
}
}
10987654321098765432109876543210
011001x110001x10101xxxxxxxxxxxxx
bfcvt. */
- return 2504;
+ return 2520;
}
}
else
10987654321098765432109876543210
x1010100xxxxxxxxxxxxxxxxxxx1xxxx
bc.c. */
- return 2640;
+ return 2656;
}
else
{
10987654321098765432109876543210
xx01110100xxxxxx0000xxxxxxxxxxxx
cpyp. */
- return 2568;
+ return 2584;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0000xxxxxxxxxxxx
cpye. */
- return 2570;
+ return 2586;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1000xxxxxxxxxxxx
cpyprn. */
- return 2574;
+ return 2590;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1000xxxxxxxxxxxx
cpyern. */
- return 2576;
+ return 2592;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0100xxxxxxxxxxxx
cpypwn. */
- return 2571;
+ return 2587;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0100xxxxxxxxxxxx
cpyewn. */
- return 2573;
+ return 2589;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1100xxxxxxxxxxxx
cpypn. */
- return 2577;
+ return 2593;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1100xxxxxxxxxxxx
cpyen. */
- return 2579;
+ return 2595;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0010xxxxxxxxxxxx
cpyprt. */
- return 2592;
+ return 2608;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0010xxxxxxxxxxxx
cpyert. */
- return 2594;
+ return 2610;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1010xxxxxxxxxxxx
cpyprtrn. */
- return 2598;
+ return 2614;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1010xxxxxxxxxxxx
cpyertrn. */
- return 2600;
+ return 2616;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0110xxxxxxxxxxxx
cpyprtwn. */
- return 2595;
+ return 2611;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0110xxxxxxxxxxxx
cpyertwn. */
- return 2597;
+ return 2613;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1110xxxxxxxxxxxx
cpyprtn. */
- return 2601;
+ return 2617;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1110xxxxxxxxxxxx
cpyertn. */
- return 2603;
+ return 2619;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0001xxxxxxxxxxxx
cpypwt. */
- return 2580;
+ return 2596;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0001xxxxxxxxxxxx
cpyewt. */
- return 2582;
+ return 2598;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1001xxxxxxxxxxxx
cpypwtrn. */
- return 2586;
+ return 2602;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1001xxxxxxxxxxxx
cpyewtrn. */
- return 2588;
+ return 2604;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0101xxxxxxxxxxxx
cpypwtwn. */
- return 2583;
+ return 2599;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0101xxxxxxxxxxxx
cpyewtwn. */
- return 2585;
+ return 2601;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1101xxxxxxxxxxxx
cpypwtn. */
- return 2589;
+ return 2605;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1101xxxxxxxxxxxx
cpyewtn. */
- return 2591;
+ return 2607;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0011xxxxxxxxxxxx
cpypt. */
- return 2604;
+ return 2620;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0011xxxxxxxxxxxx
cpyet. */
- return 2606;
+ return 2622;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1011xxxxxxxxxxxx
cpyptrn. */
- return 2610;
+ return 2626;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1011xxxxxxxxxxxx
cpyetrn. */
- return 2612;
+ return 2628;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0111xxxxxxxxxxxx
cpyptwn. */
- return 2607;
+ return 2623;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0111xxxxxxxxxxxx
cpyetwn. */
- return 2609;
+ return 2625;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1111xxxxxxxxxxxx
cpyptn. */
- return 2613;
+ return 2629;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1111xxxxxxxxxxxx
cpyetn. */
- return 2615;
+ return 2631;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0000xxxxxxxxxxxx
cpym. */
- return 2569;
+ return 2585;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0000xxxxxxxxxxxx
setgp. */
- return 2628;
+ return 2644;
}
}
else
10987654321098765432109876543210
xx01110101xxxxxx1000xxxxxxxxxxxx
cpymrn. */
- return 2575;
+ return 2591;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx1000xxxxxxxxxxxx
setge. */
- return 2630;
+ return 2646;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0100xxxxxxxxxxxx
cpymwn. */
- return 2572;
+ return 2588;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0100xxxxxxxxxxxx
setgm. */
- return 2629;
+ return 2645;
}
}
else
10987654321098765432109876543210
xx011101x1xxxxxx1100xxxxxxxxxxxx
cpymn. */
- return 2578;
+ return 2594;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0010xxxxxxxxxxxx
cpymrt. */
- return 2593;
+ return 2609;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0010xxxxxxxxxxxx
setgpn. */
- return 2634;
+ return 2650;
}
}
else
10987654321098765432109876543210
xx01110101xxxxxx1010xxxxxxxxxxxx
cpymrtrn. */
- return 2599;
+ return 2615;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx1010xxxxxxxxxxxx
setgen. */
- return 2636;
+ return 2652;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0110xxxxxxxxxxxx
cpymrtwn. */
- return 2596;
+ return 2612;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0110xxxxxxxxxxxx
setgmn. */
- return 2635;
+ return 2651;
}
}
else
10987654321098765432109876543210
xx011101x1xxxxxx1110xxxxxxxxxxxx
cpymrtn. */
- return 2602;
+ return 2618;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0001xxxxxxxxxxxx
cpymwt. */
- return 2581;
+ return 2597;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0001xxxxxxxxxxxx
setgpt. */
- return 2631;
+ return 2647;
}
}
else
10987654321098765432109876543210
xx01110101xxxxxx1001xxxxxxxxxxxx
cpymwtrn. */
- return 2587;
+ return 2603;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx1001xxxxxxxxxxxx
setget. */
- return 2633;
+ return 2649;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0101xxxxxxxxxxxx
cpymwtwn. */
- return 2584;
+ return 2600;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0101xxxxxxxxxxxx
setgmt. */
- return 2632;
+ return 2648;
}
}
else
10987654321098765432109876543210
xx011101x1xxxxxx1101xxxxxxxxxxxx
cpymwtn. */
- return 2590;
+ return 2606;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0011xxxxxxxxxxxx
cpymt. */
- return 2605;
+ return 2621;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0011xxxxxxxxxxxx
setgptn. */
- return 2637;
+ return 2653;
}
}
else
10987654321098765432109876543210
xx01110101xxxxxx1011xxxxxxxxxxxx
cpymtrn. */
- return 2611;
+ return 2627;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx1011xxxxxxxxxxxx
setgetn. */
- return 2639;
+ return 2655;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0111xxxxxxxxxxxx
cpymtwn. */
- return 2608;
+ return 2624;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0111xxxxxxxxxxxx
setgmtn. */
- return 2638;
+ return 2654;
}
}
else
10987654321098765432109876543210
xx011101x1xxxxxx1111xxxxxxxxxxxx
cpymtn. */
- return 2614;
+ return 2630;
}
}
}
10987654321098765432109876543210
0x001110xx0xxxxx1x1001xxxxxxxxxx
smmla. */
- return 2495;
+ return 2511;
}
}
}
10987654321098765432109876543210
0x001110xx0xxxxx1x0101xxxxxxxxxx
sdot. */
- return 2421;
+ return 2437;
}
}
else
10987654321098765432109876543210
0x001110xx0xxxxx1x1011xxxxxxxxxx
usmmla. */
- return 2497;
+ return 2513;
}
}
}
10987654321098765432109876543210
0x001110xx0xxxxx1x0111xxxxxxxxxx
usdot. */
- return 2498;
+ return 2514;
}
}
else
10987654321098765432109876543210
1x001110000xxxxxxxxxxxxxxxxxxxxx
eor3. */
- return 2428;
+ return 2444;
}
else
{
10987654321098765432109876543210
1x001110100xxxxxxxxxxxxxxxxxxxxx
xar. */
- return 2430;
+ return 2446;
}
}
else
10987654321098765432109876543210
1x001110x10xxxxx0xxxxxxxxxxxxxxx
sm3ss1. */
- return 2432;
+ return 2448;
}
else
{
10987654321098765432109876543210
1x001110010xxxxx1xxx00xxxxxxxxxx
sm3tt1a. */
- return 2433;
+ return 2449;
}
else
{
10987654321098765432109876543210
1x001110110xxxxx1xxx00xxxxxxxxxx
sha512su0. */
- return 2426;
+ return 2442;
}
}
else
10987654321098765432109876543210
1x001110x10xxxxx1xxx10xxxxxxxxxx
sm3tt2a. */
- return 2435;
+ return 2451;
}
}
else
10987654321098765432109876543210
1x001110010xxxxx1xxx01xxxxxxxxxx
sm3tt1b. */
- return 2434;
+ return 2450;
}
else
{
10987654321098765432109876543210
1x001110110xxxxx1xxx01xxxxxxxxxx
sm4e. */
- return 2439;
+ return 2455;
}
}
else
10987654321098765432109876543210
1x001110x10xxxxx1xxx11xxxxxxxxxx
sm3tt2b. */
- return 2436;
+ return 2452;
}
}
}
10987654321098765432109876543210
xx101110xx0xxxxx100101xxxxxxxxxx
udot. */
- return 2420;
+ return 2436;
}
}
else
10987654321098765432109876543210
xx101110xx0xxxxx101x01xxxxxxxxxx
ummla. */
- return 2496;
+ return 2512;
}
else
{
10987654321098765432109876543210
xx101110xx0xxxxx1x1011xxxxxxxxxx
bfmmla. */
- return 2512;
+ return 2528;
}
else
{
10987654321098765432109876543210
xx1011100x0xxxxx1x1111xxxxxxxxxx
bfdot. */
- return 2510;
+ return 2526;
}
else
{
10987654321098765432109876543210
x01011101x0xxxxx1x1111xxxxxxxxxx
bfmlalb. */
- return 2517;
+ return 2533;
}
else
{
10987654321098765432109876543210
x11011101x0xxxxx1x1111xxxxxxxxxx
bfmlalt. */
- return 2516;
+ return 2532;
}
}
}
10987654321098765432109876543210
000011101x1xxxx1011010xxxxxxxxxx
bfcvtn. */
- return 2513;
+ return 2529;
}
else
{
10987654321098765432109876543210
010011101x1xxxx1011010xxxxxxxxxx
bfcvtn2. */
- return 2514;
+ return 2530;
}
}
}
10987654321098765432109876543210
1x001110xx1xxxxx0xxxxxxxxxxxxxxx
bcax. */
- return 2431;
+ return 2447;
}
}
else
10987654321098765432109876543210
11001110xx1xxxxx100000xxxxxxxxxx
sha512h. */
- return 2424;
+ return 2440;
}
}
}
10987654321098765432109876543210
11001110xx1xxxxx110000xxxxxxxxxx
sm3partw1. */
- return 2437;
+ return 2453;
}
}
}
10987654321098765432109876543210
1x001110xx1xxxxx100010xxxxxxxxxx
sha512su1. */
- return 2427;
+ return 2443;
}
}
else
10987654321098765432109876543210
1x0011100x1xxxxx110010xxxxxxxxxx
sm4ekey. */
- return 2440;
+ return 2456;
}
}
else
10987654321098765432109876543210
1x001110xx1xxxxx100001xxxxxxxxxx
sha512h2. */
- return 2425;
+ return 2441;
}
}
else
10987654321098765432109876543210
1x0011100x1xxxxx110001xxxxxxxxxx
sm3partw2. */
- return 2438;
+ return 2454;
}
}
else
10987654321098765432109876543210
1x001110xx1xxxxx100011xxxxxxxxxx
rax1. */
- return 2429;
+ return 2445;
}
}
else
10987654321098765432109876543210
x01011100x1xxxxx110011xxxxxxxxxx
fmlal2. */
- return 2443;
+ return 2459;
}
else
{
10987654321098765432109876543210
x11011100x1xxxxx110011xxxxxxxxxx
fmlal2. */
- return 2447;
+ return 2463;
}
}
}
10987654321098765432109876543210
x01011101x1xxxxx110011xxxxxxxxxx
fmlsl2. */
- return 2444;
+ return 2460;
}
else
{
10987654321098765432109876543210
x11011101x1xxxxx110011xxxxxxxxxx
fmlsl2. */
- return 2448;
+ return 2464;
}
}
}
10987654321098765432109876543210
x00011100x1xxxxx111011xxxxxxxxxx
fmlal. */
- return 2441;
+ return 2457;
}
else
{
10987654321098765432109876543210
x10011100x1xxxxx111011xxxxxxxxxx
fmlal. */
- return 2445;
+ return 2461;
}
}
else
10987654321098765432109876543210
x00011101x1xxxxx111011xxxxxxxxxx
fmlsl. */
- return 2442;
+ return 2458;
}
else
{
10987654321098765432109876543210
x10011101x1xxxxx111011xxxxxxxxxx
fmlsl. */
- return 2446;
+ return 2462;
}
}
else
10987654321098765432109876543210
x0001111xxxxxxxx0000x0xxxxxxxxxx
fmlal. */
- return 2449;
+ return 2465;
}
else
{
10987654321098765432109876543210
x1001111xxxxxxxx0000x0xxxxxxxxxx
fmlal. */
- return 2453;
+ return 2469;
}
}
else
10987654321098765432109876543210
x0001111xxxxxxxx0100x0xxxxxxxxxx
fmlsl. */
- return 2450;
+ return 2466;
}
else
{
10987654321098765432109876543210
x1001111xxxxxxxx0100x0xxxxxxxxxx
fmlsl. */
- return 2454;
+ return 2470;
}
}
else
10987654321098765432109876543210
x0101111xxxxxxxx1000x0xxxxxxxxxx
fmlal2. */
- return 2451;
+ return 2467;
}
else
{
10987654321098765432109876543210
x1101111xxxxxxxx1000x0xxxxxxxxxx
fmlal2. */
- return 2455;
+ return 2471;
}
}
}
10987654321098765432109876543210
x0101111xxxxxxxx1100x0xxxxxxxxxx
fmlsl2. */
- return 2452;
+ return 2468;
}
else
{
10987654321098765432109876543210
x1101111xxxxxxxx1100x0xxxxxxxxxx
fmlsl2. */
- return 2456;
+ return 2472;
}
}
}
10987654321098765432109876543210
xx001111xxxxxxxx1110x0xxxxxxxxxx
sdot. */
- return 2423;
+ return 2439;
}
else
{
10987654321098765432109876543210
xx101111xxxxxxxx1110x0xxxxxxxxxx
udot. */
- return 2422;
+ return 2438;
}
}
}
10987654321098765432109876543210
xx00111100xxxxxx1111x0xxxxxxxxxx
sudot. */
- return 2500;
+ return 2516;
}
else
{
10987654321098765432109876543210
xx00111110xxxxxx1111x0xxxxxxxxxx
usdot. */
- return 2499;
+ return 2515;
}
}
else
10987654321098765432109876543210
xx00111101xxxxxx1111x0xxxxxxxxxx
bfdot. */
- return 2511;
+ return 2527;
}
else
{
10987654321098765432109876543210
x000111111xxxxxx1111x0xxxxxxxxxx
bfmlalb. */
- return 2519;
+ return 2535;
}
else
{
10987654321098765432109876543210
x100111111xxxxxx1111x0xxxxxxxxxx
bfmlalt. */
- return 2518;
+ return 2534;
}
}
}
{
case 2389: value = 2391; break; /* mov --> mova. */
case 2391: return NULL; /* mova --> NULL. */
+ case 2426: value = 2434; break; /* mov --> mova. */
+ case 2434: return NULL; /* mova --> NULL. */
+ case 2424: value = 2432; break; /* mov --> mova. */
+ case 2432: return NULL; /* mova --> NULL. */
+ case 2427: value = 2435; break; /* mov --> mova. */
+ case 2435: return NULL; /* mova --> NULL. */
+ case 2425: value = 2433; break; /* mov --> mova. */
+ case 2433: return NULL; /* mova --> NULL. */
case 2388: value = 2390; break; /* mov --> mova. */
case 2390: return NULL; /* mova --> NULL. */
+ case 2422: value = 2430; break; /* mov --> mova. */
+ case 2430: return NULL; /* mova --> NULL. */
+ case 2420: value = 2428; break; /* mov --> mova. */
+ case 2428: return NULL; /* mova --> NULL. */
+ case 2423: value = 2431; break; /* mov --> mova. */
+ case 2431: return NULL; /* mova --> NULL. */
+ case 2421: value = 2429; break; /* mov --> mova. */
+ case 2429: return NULL; /* mova --> NULL. */
case 2393: value = 2398; break; /* ld1b --> ld1b. */
case 2398: return NULL; /* ld1b --> NULL. */
case 2395: value = 2400; break; /* ld1w --> ld1w. */
case 2407: value = 2412; break; /* st1q --> st1q. */
case 2412: return NULL; /* st1q --> NULL. */
case 12: value = 19; break; /* add --> addg. */
- case 19: value = 2641; break; /* addg --> smax. */
- case 2641: value = 2642; break; /* smax --> umax. */
- case 2642: value = 2643; break; /* umax --> smin. */
- case 2643: value = 2644; break; /* smin --> umin. */
- case 2644: return NULL; /* umin --> NULL. */
+ case 19: value = 2657; break; /* addg --> smax. */
+ case 2657: value = 2658; break; /* smax --> umax. */
+ case 2658: value = 2659; break; /* umax --> smin. */
+ case 2659: value = 2660; break; /* smin --> umin. */
+ case 2660: return NULL; /* umin --> NULL. */
case 16: value = 20; break; /* sub --> subg. */
case 20: return NULL; /* subg --> NULL. */
case 971: value = 975; break; /* stnp --> stp. */
case 824: return NULL; /* fsqrt --> NULL. */
case 832: value = 833; break; /* frintz --> frintz. */
case 833: return NULL; /* frintz --> NULL. */
- case 825: value = 2515; break; /* fcvt --> bfcvt. */
- case 2515: return NULL; /* bfcvt --> NULL. */
+ case 825: value = 2531; break; /* fcvt --> bfcvt. */
+ case 2531: return NULL; /* bfcvt --> NULL. */
case 834: value = 835; break; /* frinta --> frinta. */
case 835: return NULL; /* frinta --> NULL. */
case 836: value = 837; break; /* frintx --> frintx. */
case 203:
case 209:
case 212:
- case 214:
- case 215:
case 218:
+ case 219:
+ case 224:
return aarch64_ext_regno (self, info, code, inst, errors);
case 10:
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
case 33:
case 34:
case 35:
- case 226:
+ case 234:
return aarch64_ext_reglane (self, info, code, inst, errors);
case 36:
return aarch64_ext_reglist (self, info, code, inst, errors);
case 192:
case 193:
case 194:
- case 219:
case 225:
- case 230:
- case 231:
+ case 233:
+ case 238:
+ case 239:
return aarch64_ext_imm (self, info, code, inst, errors);
case 44:
case 45:
case 211:
case 213:
return aarch64_ext_sve_reglist (self, info, code, inst, errors);
+ case 214:
+ case 215:
case 216:
case 217:
+ return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors);
case 220:
+ case 222:
+ case 226:
return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors);
case 221:
- return aarch64_ext_sme_za_array (self, info, code, inst, errors);
- case 222:
- return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 223:
- return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
- case 224:
- return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+ return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 227:
case 228:
case 229:
+ return aarch64_ext_sme_za_array (self, info, code, inst, errors);
+ case 230:
+ return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
+ case 231:
+ return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
+ case 232:
+ return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 235:
+ case 236:
+ case 237:
return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);
default: assert (0); abort ();
}
&& decode_sve_aimm (info, (uint8_t) info->imm.value));
}
+bool
+aarch64_ext_sve_aligned_reglist (const aarch64_operand *self,
+ aarch64_opnd_info *info, aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ unsigned int num_regs = get_operand_specific_data (self);
+ unsigned int val = extract_field (self->fields[0], code, 0);
+ info->reglist.first_regno = val * num_regs;
+ info->reglist.num_regs = num_regs;
+ info->reglist.stride = 1;
+ return true;
+}
+
/* Decode an SVE CPY/DUP immediate. */
bool
aarch64_ext_sve_asimm (const aarch64_operand *self,
return true;
}
+bool
+aarch64_ext_sme_za_hv_tiles_range (const aarch64_operand *self,
+ aarch64_opnd_info *info, aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors
+ ATTRIBUTE_UNUSED)
+{
+ int ebytes = aarch64_get_qualifier_esize (info->qualifier);
+ int range_size = get_opcode_dependent_value (inst->opcode);
+ int fld_v = extract_field (self->fields[0], code, 0);
+ int fld_rv = extract_field (self->fields[1], code, 0);
+ int fld_zan_imm = extract_field (self->fields[2], code, 0);
+ int max_value = 16 / range_size / ebytes;
+
+ if (max_value == 0)
+ max_value = 1;
+
+ int regno = fld_zan_imm / max_value;
+ if (regno >= ebytes)
+ return false;
+
+ info->indexed_za.regno = regno;
+ info->indexed_za.index.imm = (fld_zan_imm % max_value) * range_size;
+ info->indexed_za.index.countm1 = range_size - 1;
+ info->indexed_za.index.regno = fld_rv + 12;
+ info->indexed_za.v = fld_v;
+
+ return true;
+}
+
/* Decode in SME instruction ZERO list of up to eight 64-bit element tile names
separated by commas, encoded in the "imm8" field.
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
- int regno = extract_field (self->fields[0], code, 0) + 12;
+ int regno = extract_field (self->fields[0], code, 0);
+ if (info->type == AARCH64_OPND_SME_ZA_array_off4)
+ regno += 12;
+ else
+ regno += 8;
int imm = extract_field (self->fields[1], code, 0);
info->indexed_za.index.regno = regno;
info->indexed_za.index.imm = imm;
+ info->indexed_za.group_size = get_opcode_dependent_value (inst->opcode);
return true;
}
}
break;
+ case sme_size_22:
+ variant = extract_field (FLD_SME_size_22, inst->value, 0);
+ break;
+
case sve_cpy:
variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_14);
break;
variant = 3;
break;
+ case sme2_mov:
+ /* .D is preferred over the other sizes in disassembly. */
+ variant = 3;
+ break;
+
case sme_misc:
case sve_misc:
/* These instructions have only a single variant. */
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zz_sxtw);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zz_uxtw);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_aimm);
+AARCH64_DECL_OPD_EXTRACTOR (ext_sve_aligned_reglist);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_asimm);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_one);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_two);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shlimm);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shrimm);
AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_hv_tiles);
+AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_hv_tiles_range);
AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_list);
AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_array);
AARCH64_DECL_OPD_EXTRACTOR (ext_sme_addr_ri_u4xvl);
{AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn2}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn4}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn4}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_2b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_2b}, "an SME ZA tile ZA0-ZA3"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_3b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_3b}, "an SME ZA tile ZA0-ZA7"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5}, "an SME horizontal or vertical vector access register"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_srcxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_imm3_5}, "an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_destxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_imm3_0}, "an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "a list of 64-bit ZA element tiles"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3_0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm3_0}, "ZA array"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm3_5}, "ZA array"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_0}, "ZA array"},
{AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, "memory offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"},
{ 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */
{ 0, 2 }, /* SME_ZAda_2b: tile ZA0-ZA3. */
{ 0, 3 }, /* SME_ZAda_3b: tile ZA0-ZA7. */
+ { 1, 4 }, /* SME_Zdn2: Z0-Z31, multiple of 2, bits [4:1]. */
+ { 2, 3 }, /* SME_Zdn4: Z0-Z31, multiple of 4, bits [4:2]. */
+ { 6, 4 }, /* SME_Zn2: Z0-Z31, multiple of 2, bits [9:6]. */
+ { 7, 3 }, /* SME_Zn4: Z0-Z31, multiple of 4, bits [9:7]. */
{ 23, 1 }, /* SME_i1: immediate field, bit 23. */
{ 22, 2 }, /* SME_size_22: size<1>, size<0> class field, [23:22]. */
{ 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */
{ 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
{ 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
{ 21, 2 }, /* hw: in move wide constant instructions. */
+ { 0, 3 }, /* imm3_0: general immediate in bits [2:0]. */
+ { 5, 3 }, /* imm3_5: general immediate in bits [7:5]. */
{ 10, 3 }, /* imm3_10: in add/sub extended reg instructions. */
{ 0, 4 }, /* imm4_0: in rmif instructions. */
{ 5, 4 }, /* imm4_5: in SME instructions. */
set_other_error (mismatch_detail, idx,
_("expected a selection register in the"
" range w12-w15"));
+ else if (min_wreg == 8)
+ set_other_error (mismatch_detail, idx,
+ _("expected a selection register in the"
+ " range w8-w11"));
else
abort ();
return false;
set_other_error (mismatch_detail, idx,
_("expected a single offset rather than"
" a range"));
+ else if (range_size == 2)
+ set_other_error (mismatch_detail, idx,
+ _("expected a range of two offsets"));
+ else if (range_size == 4)
+ set_other_error (mismatch_detail, idx,
+ _("expected a range of four offsets"));
else
abort ();
return false;
break;
case AARCH64_OPND_CLASS_SVE_REGLIST:
- num = get_opcode_dependent_value (opcode);
- if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
- return 0;
+ switch (type)
+ {
+ case AARCH64_OPND_SME_Zdnx2:
+ case AARCH64_OPND_SME_Zdnx4:
+ case AARCH64_OPND_SME_Znx2:
+ case AARCH64_OPND_SME_Znx4:
+ num = get_operand_specific_data (&aarch64_operands[type]);
+ if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
+ return 0;
+ if ((opnd->reglist.first_regno % num) != 0)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("start register out of range"));
+ return 0;
+ }
+ break;
+
+ case AARCH64_OPND_SVE_ZnxN:
+ case AARCH64_OPND_SVE_ZtxN:
+ num = get_opcode_dependent_value (opcode);
+ if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
+ return 0;
+ break;
+
+ default:
+ abort ();
+ }
break;
case AARCH64_OPND_CLASS_ZA_ACCESS:
return 0;
break;
+ case AARCH64_OPND_SME_ZA_array_off3_0:
+ case AARCH64_OPND_SME_ZA_array_off3_5:
+ if (!check_za_access (opnd, mismatch_detail, idx, 8, 7, 1,
+ get_opcode_dependent_value (opcode)))
+ return 0;
+ break;
+
+ case AARCH64_OPND_SME_ZA_HV_idx_srcxN:
+ case AARCH64_OPND_SME_ZA_HV_idx_destxN:
+ size = aarch64_get_qualifier_esize (opnd->qualifier);
+ num = get_opcode_dependent_value (opcode);
+ max_value = 16 / num / size;
+ if (max_value > 0)
+ max_value -= 1;
+ if (!check_za_access (opnd, mismatch_detail, idx,
+ 12, max_value, num, 0))
+ return 0;
+ break;
+
default:
abort ();
}
case AARCH64_OPND_SVE_ZnxN:
case AARCH64_OPND_SVE_ZtxN:
+ case AARCH64_OPND_SME_Zdnx2:
+ case AARCH64_OPND_SME_Zdnx4:
+ case AARCH64_OPND_SME_Znx2:
+ case AARCH64_OPND_SME_Znx4:
print_register_list (buf, size, opnd, "z", styler);
break;
break;
case AARCH64_OPND_SME_ZA_HV_idx_src:
+ case AARCH64_OPND_SME_ZA_HV_idx_srcxN:
case AARCH64_OPND_SME_ZA_HV_idx_dest:
+ case AARCH64_OPND_SME_ZA_HV_idx_destxN:
case AARCH64_OPND_SME_ZA_HV_idx_ldstr:
snprintf (buf, size, "%s%s[%s, %s%s%s%s%s]%s",
opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "{" : "",
print_sme_za_list (buf, size, opnd->reg.regno, styler);
break;
+ case AARCH64_OPND_SME_ZA_array_off3_0:
+ case AARCH64_OPND_SME_ZA_array_off3_5:
case AARCH64_OPND_SME_ZA_array_off4:
snprintf (buf, size, "%s[%s, %s%s%s%s%s]",
- style_reg (styler, "za"),
+ style_reg (styler, "za%s%s",
+ opnd->qualifier == AARCH64_OPND_QLF_NIL ? "" : ".",
+ (opnd->qualifier == AARCH64_OPND_QLF_NIL
+ ? ""
+ : aarch64_get_qualifier_name (opnd->qualifier))),
style_reg (styler, "w%d", opnd->indexed_za.index.regno),
style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm),
opnd->indexed_za.index.countm1 ? ":" : "",
FLD_SME_V,
FLD_SME_ZAda_2b,
FLD_SME_ZAda_3b,
+ FLD_SME_Zdn2,
+ FLD_SME_Zdn4,
+ FLD_SME_Zn2,
+ FLD_SME_Zn4,
FLD_SME_i1,
FLD_SME_size_22,
FLD_SME_tszh,
FLD_cond2,
FLD_defgh,
FLD_hw,
+ FLD_imm3_0,
+ FLD_imm3_5,
FLD_imm3_10,
FLD_imm4_0,
FLD_imm4_5,
static const aarch64_feature_set aarch64_feature_sme_i16i64 =
AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME
| AARCH64_FEATURE_SME_I16I64, 0);
+static const aarch64_feature_set aarch64_feature_sme2 =
+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME
+ | AARCH64_FEATURE_SME2, 0);
static const aarch64_feature_set aarch64_feature_v8_6 =
AARCH64_FEATURE (AARCH64_FEATURE_V8_6, 0);
static const aarch64_feature_set aarch64_feature_v8_7 =
#define SME &aarch64_feature_sme
#define SME_F64F64 &aarch64_feature_sme_f64f64
#define SME_I16I64 &aarch64_feature_sme_i16i64
+#define SME2 &aarch64_feature_sme2
#define ARMV8_6 &aarch64_feature_v8_6
#define ARMV8_6_SVE &aarch64_feature_v8_6
#define BFLOAT16_SVE &aarch64_feature_bfloat16_sve
#define SME_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \
F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL }
+#define SME2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, SME2, OPS, QUALS, \
+ F_STRICT | FLAGS, 0, TIED, NULL }
#define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_PNd, SVE_PNg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
+ /* SME2 extensions to SME. */
+ SME2_INSN ("mov", 0xc0060800, 0xffff9f01, sme2_mov, 0, OP2 (SME_Zdnx2, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (2), 0),
+ SME2_INSN ("mov", 0xc0060c00, 0xffff9f03, sme2_mov, 0, OP2 (SME_Zdnx4, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (4), 0),
+ SME2_INSN ("mov", 0xc0060000, 0xff3f1f01, sme_size_22, 0, OP2 (SME_Zdnx2, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (2), 0),
+ SME2_INSN ("mov", 0xc0060400, 0xff3f1f03, sme_size_22, 0, OP2 (SME_Zdnx4, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (4), 0),
+ SME2_INSN ("mov", 0xc0040800, 0xffff9c38, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VV_BHSD, F_OD (2), 0),
+ SME2_INSN ("mov", 0xc0040c00, 0xffff9c78, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VV_BHSD, F_OD (4), 0),
+ SME2_INSN ("mov", 0xc0040000, 0xff3f1c38, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx2), OP_SVE_VV_BHSDQ, F_OD (2), 0),
+ SME2_INSN ("mov", 0xc0040400, 0xff3f1c78, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx4), OP_SVE_VV_BHSDQ, F_OD (4), 0),
+ SME2_INSN ("mova", 0xc0060800, 0xffff9f01, sme2_mov, 0, OP2 (SME_Zdnx2, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (2), 0),
+ SME2_INSN ("mova", 0xc0060c00, 0xffff9f03, sme2_mov, 0, OP2 (SME_Zdnx4, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (4), 0),
+ SME2_INSN ("mova", 0xc0060000, 0xff3f1f01, sme_size_22, 0, OP2 (SME_Zdnx2, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (2), 0),
+ SME2_INSN ("mova", 0xc0060400, 0xff3f1f03, sme_size_22, 0, OP2 (SME_Zdnx4, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (4), 0),
+ SME2_INSN ("mova", 0xc0040800, 0xffff9c38, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VV_BHSD, F_OD (2), 0),
+ SME2_INSN ("mova", 0xc0040c00, 0xffff9c78, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VV_BHSD, F_OD (4), 0),
+ SME2_INSN ("mova", 0xc0040000, 0xff3f1c38, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx2), OP_SVE_VV_BHSDQ, F_OD (2), 0),
+ SME2_INSN ("mova", 0xc0040400, 0xff3f1c78, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx4), OP_SVE_VV_BHSDQ, F_OD (4), 0),
+
/* SIMD Dot Product (optional in v8.2-A). */
DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
DOT_INSN ("sdot", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
"an SVE vector register") \
Y(SVE_REGLIST, sve_reglist, "SVE_ZtxN", 0, F(FLD_SVE_Zt), \
"a list of SVE vector registers") \
+ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zdnx2", 2 << OPD_F_OD_LSB, \
+ F(FLD_SME_Zdn2), "a list of SVE vector registers") \
+ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zdnx4", 4 << OPD_F_OD_LSB, \
+ F(FLD_SME_Zdn4), "a list of SVE vector registers") \
+ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx2", 2 << OPD_F_OD_LSB, \
+ F(FLD_SME_Zn2), "a list of SVE vector registers") \
+ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx4", 4 << OPD_F_OD_LSB, \
+ F(FLD_SME_Zn4), "a list of SVE vector registers") \
Y(SVE_REG, regno, "SME_ZAda_2b", 0, F(FLD_SME_ZAda_2b), \
"an SME ZA tile ZA0-ZA3") \
Y(SVE_REG, regno, "SME_ZAda_3b", 0, F(FLD_SME_ZAda_3b), \
Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_src", 0, \
F(FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5), \
"an SME horizontal or vertical vector access register") \
+ Y(ZA_ACCESS, sme_za_hv_tiles_range, "SME_ZA_HV_idx_srcxN", 0, \
+ F(FLD_SME_V,FLD_SME_Rv,FLD_imm3_5), \
+ "an SME horizontal or vertical vector access register") \
Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_dest", 0, \
F(FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0), \
"an SME horizontal or vertical vector access register") \
+ Y(ZA_ACCESS, sme_za_hv_tiles_range, "SME_ZA_HV_idx_destxN", 0, \
+ F(FLD_SME_V,FLD_SME_Rv,FLD_imm3_0), \
+ "an SME horizontal or vertical vector access register") \
Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm), \
"an SVE predicate register") \
Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \
Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_ldstr", 0, \
F(FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0), \
"an SME horizontal or vertical vector access register") \
+ Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off3_0", 0, \
+ F(FLD_SME_Rv,FLD_imm3_0), "ZA array") \
+ Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off3_5", 0, \
+ F(FLD_SME_Rv,FLD_imm3_5), "ZA array") \
Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off4", 0, \
F(FLD_SME_Rv,FLD_imm4_0), "ZA array") \
Y(ADDRESS, sme_addr_ri_u4xvl, "SME_ADDR_RI_U4xVL", 0 << OPD_F_OD_LSB, \
projects / binutils-gdb.git / commitdiff