Enable bt and and movzx for Lakemont

	* config/i386/x86-tune.def (X86_TUNE_USE_BT): Enable for
	Lakemont.
	(X86_TUNE_ZERO_EXTEND_WITH_AND): Disable for Lakemont.

From-SVN: r228337

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2d86889bd5ae185b68657421edf685553e5db74a..70f964617b39700b1aa66a7e0246191caa083159 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2015-10-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * config/i386/x86-tune.def (X86_TUNE_USE_BT): Enable for
+       Lakemont.
+       (X86_TUNE_ZERO_EXTEND_WITH_AND): Disable for Lakemont.
+
 2015-10-01  James Greenhalgh  <james.greenhalgh@arm.com>
 
        * config/arm/aarch-common-protos.h

diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def
index 3b3f14911ccf07b321bd2897848d575e59e028be..213c604bc794b5cb9e69102014843d21b2058d63 100644 (file)
--- a/gcc/config/i386/x86-tune.def
+++ b/gcc/config/i386/x86-tune.def
@@ -292,7 +292,7 @@ DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd",
 /* X86_TUNE_USE_BT: Enable use of BT (bit test) instructions.  */
 DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
           m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_INTEL
-         | m_AMD_MULTIPLE | m_GENERIC)
+         | m_LAKEMONT | m_AMD_MULTIPLE | m_GENERIC)
 
 /*****************************************************************************/
 /* 387 instruction selection tuning                                          */
@@ -448,7 +448,7 @@ DEF_TUNE (X86_TUNE_SHIFT1, "shift1", ~m_486)
 /* X86_TUNE_ZERO_EXTEND_WITH_AND: Use AND instruction instead
    of mozbl/movwl.  */
 DEF_TUNE (X86_TUNE_ZERO_EXTEND_WITH_AND, "zero_extend_with_and",
-         m_486 | m_PENT | m_LAKEMONT)
+         m_486 | m_PENT)
 
 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
    and SImode multiply, but 386 and 486 do HImode multiply faster.  */