const struct r600_shader_src *shader_src,
unsigned chan);
+static int tgsi_last_instruction(unsigned writemask)
+{
+ int i, lasti = 0;
+
+ for (i = 0; i < 4; i++) {
+ if (writemask & (1 << i)) {
+ lasti = i;
+ }
+ }
+ return lasti;
+}
+
static int tgsi_is_supported(struct r600_shader_ctx *ctx)
{
struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
}
+static int r600_get_temp(struct r600_shader_ctx *ctx)
+{
+ return ctx->temp_reg + ctx->max_driver_temp_used++;
+}
+
static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
{
int i;
return 0;
}
-static int r600_get_temp(struct r600_shader_ctx *ctx)
-{
- return ctx->temp_reg + ctx->max_driver_temp_used++;
-}
-
static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
{
struct tgsi_parse_context parse;
}
}
-static int tgsi_last_instruction(unsigned writemask)
-{
- int i, lasti = 0;
-
- for (i = 0; i < 4; i++) {
- if (writemask & (1 << i)) {
- lasti = i;
- }
- }
- return lasti;
-}
-
-
-
static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap)
{
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;