projects / yosys.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 1809f46)
Cleanup xilinx_dsp
authorEddie Hung <eddie@fpgeh.com>
Fri, 20 Sep 2019 19:03:25 +0000 (12:03 -0700)
committerEddie Hung <eddie@fpgeh.com>
Fri, 20 Sep 2019 19:03:25 +0000 (12:03 -0700)
passes/pmgen/xilinx_dsp.pmg patch | blob | history

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 0ee230ccc72674ee7340fe1599e8a1476afd2767..7d34c6a78a18f02687375768dddea57f2d685277 100644 (file)
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -2,7 +2,7 @@ pattern xilinx_dsp_pack
 
 udata <std::function<SigSpec(const SigSpec&)>> unextend
 state <SigBit> clock
-state <SigSpec> sigA sigffAcemuxY sigB sigffBcemuxY sigC sigffCcemuxY sigD sigffDcemuxY sigM sigP
+state <SigSpec> sigA sigB sigC sigD sigM sigP
 state <IdString> postAddAB postAddMuxAB
 state <bool> ffA1cepol ffA2cepol ffADcepol ffB1cepol ffB2cepol ffCcepol ffDcepol ffMcepol ffPcepol
 state <bool> ffArstpol ffADrstpol ffBrstpol ffCrstpol ffDrstpol ffMrstpol ffPrstpol