create SATACON and use it in bist_tb

diff --git a/lib/sata/__init__.py b/lib/sata/__init__.py
new file mode 100644 (file)
index 0000000..7c76dcf
--- /dev/null
+++ b/lib/sata/__init__.py
@@ -0,0 +1,14 @@
+from migen.fhdl.std import *
+
+from lib.sata.common import *
+from lib.sata.link import SATALink
+from lib.sata.transport import SATATransport
+from lib.sata.command import SATACommand
+
+class SATACON(Module):
+       def __init__(self, phy, sector_size=512, max_count=16):
+               self.submodules.link = SATALink(phy)
+               self.submodules.transport = SATATransport(self.link)
+               self.submodules.command = SATACommand(self.transport)
+               self.sink, self.source = self.command.sink, self.command.source
+

diff --git a/lib/sata/test/bist_tb.py b/lib/sata/test/bist_tb.py
index b2e7ed6c04101f7477f44630e0e03c29e26f62b6..517441586d984437e88368a356eb27e4c4db7f0f 100644 (file)
--- a/lib/sata/test/bist_tb.py
+++ b/lib/sata/test/bist_tb.py
@@ -5,9 +5,7 @@ from migen.genlib.record import *
 from migen.sim.generic import run_simulation
 
 from lib.sata.common import *
-from lib.sata.link import SATALink
-from lib.sata.transport import SATATransport
-from lib.sata.command import SATACommand
+from lib.sata import SATACON
 from lib.sata.bist import SATABIST
 
 from lib.sata.test.hdd import *
@@ -19,14 +17,11 @@ class TB(Module):
                                link_debug=False, link_random_level=0,
                                transport_debug=False, transport_loopback=False,
                                hdd_debug=True)
-               self.submodules.link = SATALink(self.hdd.phy)
-               self.submodules.transport = SATATransport(self.link)
-               self.submodules.command = SATACommand(self.transport)
-               self.submodules.bist = SATABIST(sector_size=512, max_count=1)
-
+               self.submodules.controller = SATACON(self.hdd.phy)
+               self.submodules.bist = SATABIST(max_count=2)
                self.comb += [
-                       self.bist.source.connect(self.command.sink),
-                       self.command.source.connect(self.bist.sink)
+                       self.bist.source.connect(self.controller.sink),
+                       self.controller.source.connect(self.bist.sink)
                ]
 
        def gen_simulation(self, selfp):