Fix clk_gen_bypass

I broke clk_gen_bypass when updating the SOC reset code.

Fixes 03fd06deaf9f ("Rework SOC reset")
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

diff --git a/fpga/clk_gen_bypass.vhd b/fpga/clk_gen_bypass.vhd
index b204329e392125104e403bc54eea3c255f26d056..d5831599c274e60dd0d027a69e4313d20fca1fe9 100644 (file)
--- a/fpga/clk_gen_bypass.vhd
+++ b/fpga/clk_gen_bypass.vhd
@@ -14,7 +14,7 @@ architecture bypass of clock_generator is
 
 begin
 
-  pll_locked_out <= pll_rst_in;
+  pll_locked_out <= not pll_rst_in;
   pll_clk_out <= ext_clk;
 
 end architecture bypass;