Add SIMD to REG pattern for movhf without armv8.2-a support for AArch64

This fixes a regression where we don't have an instruction for pre Armv8.2-a
to do a move of an fp16 value from a GP reg to a SIMD reg.

This patch adds that pattern to movhf_aarch64 using a dup and only selectes it
using a very low priority.

This fixes an ICE at -O0.

gcc/
2018-06-20  Tamar Christina  <tamar.christina@arm.com>

	PR target/85769
	* config/aarch64/aarch64.md (*movhf_aarch64): Add dup v0.4h pattern.

gcc/testsuite/
2018-06-20  Tamar Christina  <tamar.christina@arm.com>

	PR target/85769
	* gcc.target/aarch64/f16_mov_immediate_3.c: New.

From-SVN: r262178

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 773eeaa4681d33db563b3288c574c6de2f94c55b..194d2eef3be27d91292f25218b041470a146c26f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2018-06-27 Tamar Christina  <tamar.christina@arm.com>
+
+       PR target/85769
+       * config/aarch64/aarch64.md (*movhf_aarch64): Add dup v0.4h pattern.
+
 2018-06-27  Siddhesh Poyarekar  <siddhesh@sourceware.org>
 
        * config/aarch64/aarch64.h (CALL_USE_REGISTERS): Fix obsolete

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 830f97603487d6ed07c4dc854a7898c4d17894d1..4ac6332a2001ac5869f9fe300a9c350a4621fdbf 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1161,13 +1161,14 @@
 )
 
 (define_insn "*movhf_aarch64"
-  [(set (match_operand:HF 0 "nonimmediate_operand" "=w,w  ,?r,w,w  ,w  ,w,m,r,m ,r")
-       (match_operand:HF 1 "general_operand"      "Y ,?rY, w,w,Ufc,Uvi,m,w,m,rY,r"))]
+  [(set (match_operand:HF 0 "nonimmediate_operand" "=w,w  , w,?r,w,w  ,w  ,w,m,r,m ,r")
+       (match_operand:HF 1 "general_operand"      "Y ,?rY,?r, w,w,Ufc,Uvi,m,w,m,rY,r"))]
   "TARGET_FLOAT && (register_operand (operands[0], HFmode)
     || aarch64_reg_or_fp_zero (operands[1], HFmode))"
   "@
    movi\\t%0.4h, #0
    fmov\\t%h0, %w1
+   dup\\t%w0.4h, %w1
    umov\\t%w0, %1.h[0]
    mov\\t%0.h[0], %1.h[0]
    fmov\\t%h0, %1
@@ -1177,10 +1178,10 @@
    ldrh\\t%w0, %1
    strh\\t%w1, %0
    mov\\t%w0, %w1"
-  [(set_attr "type" "neon_move,f_mcr,neon_to_gp,neon_move,fconsts, \
+  [(set_attr "type" "neon_move,f_mcr,neon_move,neon_to_gp, neon_move,fconsts, \
                     neon_move,f_loads,f_stores,load_4,store_4,mov_reg")
-   (set_attr "simd" "yes,*,yes,yes,*,yes,*,*,*,*,*")
-   (set_attr "fp16"   "*,yes,*,*,yes,*,*,*,*,*,*")]
+   (set_attr "simd" "yes,*,yes,yes,yes,*,yes,*,*,*,*,*")
+   (set_attr "fp16"   "*,yes,*,*,*,yes,*,*,*,*,*,*")]
 )
 
 (define_insn "*movsf_aarch64"

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 371c9f17a4713404e0642faed7facef7883dac44..f20147a7027204435bba5602c4c316e3f188104d 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2018-06-27 Tamar Christina  <tamar.christina@arm.com>
+
+       PR target/85769
+       * gcc.target/aarch64/f16_mov_immediate_3.c: New.
+
 2018-06-26  Kelvin Nilsen  <kelvin@gcc.gnu.org>
 
        * gcc.target/powerpc/builtins-1.c: Correct a comment.

diff --git a/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_3.c b/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_3.c
new file mode 100644 (file)
index 0000000..6dc325b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_3.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O0" } */
+
+extern __fp16 foo ();
+
+__fp16 f4 ()
+{
+  __fp16 a = 0;
+  __fp16 b = 1;
+  __fp16 c = 2;
+  __fp16 d = 4;
+
+  __fp16 z = a + b;
+  z = z + c;
+  z = z - d;
+  return z;
+}
+
+/* { dg-final { scan-assembler-times {dup\tv[0-9]+.4h, w[0-9]+} 1 } } */