radv: set amdgpu-32bit-address-high-bits LLVM attribute

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index 2d91ded7fe51f6d8ddd1afaa2aba30a1d4eba65d..3f32f62cdc4b067b55a6ac99fa160238b6e3df3f 100644 (file)
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -511,6 +511,12 @@ create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
                }
        }
 
+       if (options->address32_hi) {
+               ac_llvm_add_target_dep_function_attr(main_function,
+                                                    "amdgpu-32bit-address-high-bits",
+                                                    options->address32_hi);
+       }
+
        if (max_workgroup_size) {
                ac_llvm_add_target_dep_function_attr(main_function,
                                                     "amdgpu-max-work-group-size",

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 7589d9c88a56d000d783e1514838eaa8e6c3ec19..6ccbe81effaad7c1aed26c270eff4879a4d47d4e 100644 (file)
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -482,6 +482,7 @@ shader_variant_create(struct radv_device *device,
                                 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
        options->record_llvm_ir = device->keep_shader_info;
        options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
+       options->address32_hi = device->physical_device->rad_info.address32_hi;
 
        if (options->supports_spill)
                tm_options |= AC_TM_SUPPORTS_SPILL;

diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 679fa442798436bc3657a2472366b14c4bd5c078..05de188e3f3a3d41f4828c666499b3af27c81870 100644 (file)
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -123,6 +123,7 @@ struct radv_nir_compiler_options {
        enum radeon_family family;
        enum chip_class chip_class;
        uint32_t tess_offchip_block_dw_size;
+       uint32_t address32_hi;
 };
 
 enum radv_ud_index {