(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 0e4082c8d02d153875df80a7b0ff0a0b8e18a1fc..4d8f5a81702677be0c1e8a0c39eefb3240b89ed1 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -552,8 +552,9 @@ The similarity to ZOLC should not have gone unnoticed: where ZOLC
 has nested conditional for-loops Extra-V appears to have just the
 one conditional for-loop, but the key strategically-crucial
 part of this multi-faceted puzzle is that due to the deterministic and
-coherent nature of Extra-V, the processing of the loops is
-*embedded right next to the memory*
+coherent nature of Extra-V, the processing of the loops is not
+done close to the CPU it is
+*embedded right next to the memory*.
 
 **Snitch**