mention shape/remap

diff --git a/3d_gpu/microarchitecture.mdwn b/3d_gpu/microarchitecture.mdwn
index 92e614c227bdd7ac6d79db1bbc13c5ea4a4b704f..e6118d4cc123736111ef613d3afec4800cb97b58 100644 (file)
--- a/3d_gpu/microarchitecture.mdwn
+++ b/3d_gpu/microarchitecture.mdwn
@@ -14,7 +14,7 @@
   TODO: consider 2R for registers to be used as predication targets
   if >= 32.
 * Potentially: Lane-swapping / crossing / data-multiplexing
-  bus on register data
+  bus on register data (particularly because of SHAPE-REMAP (1D/2D/3D)
 * Potentially: Registers subdivided into 16-bit, to match
   elwidth down to 16-bit (for FP16).  8-bit elwidth only
   goes down as far as twin-SIMD (with predication).  This