module opt_share_test(
- input [15:0] a,
- input [15:0] b,
- input sel,
- output [15:0] res,
- );
+ input [15:0] a,
+ input [15:0] b,
+ input sel,
+ output [15:0] res,
+ );
- assign res = {sel ? a + b : a - b};
+ assign res = {sel ? a + b : a - b};
endmodule
module opt_share_test(
- input [15:0] a,
- input [15:0] b,
- input [15:0] c,
- input [15:0] d,
- input sel,
- output [63:0] res,
- );
+ input [15:0] a,
+ input [15:0] b,
+ input [15:0] c,
+ input [15:0] d,
+ input sel,
+ output [63:0] res,
+ );
- reg [31: 0] cat1 = {a+b, c+d};
- reg [31: 0] cat2 = {a-b, c-d};
+ reg [31: 0] cat1 = {a+b, c+d};
+ reg [31: 0] cat2 = {a-b, c-d};
- assign res = {b, sel ? cat1 : cat2, a};
+ assign res = {b, sel ? cat1 : cat2, a};
endmodule
module opt_share_test(
- input [15:0] a,
- input [15:0] b,
- input [15:0] c,
- input [15:0] d,
- input sel,
- output reg [47:0] res,
- );
+ input [15:0] a,
+ input [15:0] b,
+ input [15:0] c,
+ input [15:0] d,
+ input sel,
+ output reg [47:0] res,
+ );
- wire [15:0] add_res = a+b;
- wire [15:0] sub_res = a-b;
- wire [31: 0] cat1 = {add_res, c+d};
- wire [31: 0] cat2 = {sub_res, c-d};
+ wire [15:0] add_res = a+b;
+ wire [15:0] sub_res = a-b;
+ wire [31: 0] cat1 = {add_res, c+d};
+ wire [31: 0] cat2 = {sub_res, c-d};
- always @* begin
- case(sel)
- 0: res = {cat1, add_res};
- 1: res = {cat2, add_res};
- endcase
- end
+ always @* begin
+ case(sel)
+ 0: res = {cat1, add_res};
+ 1: res = {cat2, add_res};
+ endcase
+ end
endmodule
module opt_share_test(
- input [15:0] a,
- input [15:0] b,
- input [15:0] c,
- input [1:0] sel,
- output reg [15:0] res
- );
+ input [15:0] a,
+ input [15:0] b,
+ input [15:0] c,
+ input [1:0] sel,
+ output reg [15:0] res
+ );
- wire [15:0] add0_res = a+b;
- wire [15:0] add1_res = a+c;
+ wire [15:0] add0_res = a+b;
+ wire [15:0] add1_res = a+c;
- always @* begin
- case(sel)
- 0: res = add0_res[10:0];
- 1: res = add1_res[10:0];
- 2: res = a - b;
- default: res = 32'bx;
- endcase
- end
+ always @* begin
+ case(sel)
+ 0: res = add0_res[10:0];
+ 1: res = add1_res[10:0];
+ 2: res = a - b;
+ default: res = 32'bx;
+ endcase
+ end
endmodule
module opt_share_test(
- input signed [7:0] a,
- input signed [10:0] b,
- input signed [15:0] c,
- input [1:0] sel,
- output reg signed [15:0] res
- );
+ input signed [7:0] a,
+ input signed [10:0] b,
+ input signed [15:0] c,
+ input [1:0] sel,
+ output reg signed [15:0] res
+ );
- always @* begin
- case(sel)
- 0: res = a + b;
- 1: res = a - b;
- 2: res = a + c;
- default: res = 16'bx;
- endcase
- end
+ always @* begin
+ case(sel)
+ 0: res = a + b;
+ 1: res = a - b;
+ 2: res = a + c;
+ default: res = 16'bx;
+ endcase
+ end
endmodule
module opt_share_test(
- input [15:0] a,
- input [15:0] b,
- input [15:0] c,
- input [2:0] sel,
- output reg [31:0] res
- );
+ input [15:0] a,
+ input [15:0] b,
+ input [15:0] c,
+ input [2:0] sel,
+ output reg [31:0] res
+ );
- always @* begin
- case(sel)
- 0: res = {a + b, a};
- 1: res = {a - b, b};
- 2: res = {a + c, c};
- 3: res = {a - c, a};
- 4: res = {b, b};
- 5: res = {c, c};
- default: res = 32'bx;
- endcase
- end
+ always @* begin
+ case(sel)
+ 0: res = {a + b, a};
+ 1: res = {a - b, b};
+ 2: res = {a + c, c};
+ 3: res = {a - c, a};
+ 4: res = {b, b};
+ 5: res = {c, c};
+ default: res = 32'bx;
+ endcase
+ end
endmodule
module opt_share_test(
- input [15:0] a,
- input [15:0] b,
- input [15:0] c,
- input [15:0] d,
- input [2:0] sel,
- output reg [31:0] res
- );
+ input [15:0] a,
+ input [15:0] b,
+ input [15:0] c,
+ input [15:0] d,
+ input [2:0] sel,
+ output reg [31:0] res
+ );
- wire [15:0] add0_res = a+d;
+ wire [15:0] add0_res = a+d;
- always @* begin
- case(sel)
- 0: res = {add0_res, a};
- 1: res = {a - b, add0_res[7], 15'b0};
- 2: res = {b-a, b};
- 3: res = {d, b - c};
- 4: res = {d, b - a};
- 5: res = {c, d};
- 6: res = {a - c, b-d};
- default: res = 32'bx;
- endcase
- end
+ always @* begin
+ case(sel)
+ 0: res = {add0_res, a};
+ 1: res = {a - b, add0_res[7], 15'b0};
+ 2: res = {b-a, b};
+ 3: res = {d, b - c};
+ 4: res = {d, b - a};
+ 5: res = {c, d};
+ 6: res = {a - c, b-d};
+ default: res = 32'bx;
+ endcase
+ end
endmodule
module opt_share_test(
- input [15:0] a,
- input [15:0] b,
- input [15:0] c,
- input [15:0] d,
- input [2:0] sel,
- output reg [15:0] res
- );
+ input [15:0] a,
+ input [15:0] b,
+ input [15:0] c,
+ input [15:0] d,
+ input [2:0] sel,
+ output reg [15:0] res
+ );
- always @* begin
- case(sel)
- 0: res = a + d;
- 1: res = a - b;
- 2: res = b;
- 3: res = b - c;
- 4: res = b - a;
- 5: res = c;
- 6: res = a - c;
- default: res = 16'bx;
- endcase
- end
+ always @* begin
+ case(sel)
+ 0: res = a + d;
+ 1: res = a - b;
+ 2: res = b;
+ 3: res = b - c;
+ 4: res = b - a;
+ 5: res = c;
+ 6: res = a - c;
+ default: res = 16'bx;
+ endcase
+ end
endmodule
module opt_share_test(
- input [15:0] a,
- input [15:0] b,
- input [15:0] c,
- input [2:0] sel,
- output reg [15:0] res
- );
+ input [15:0] a,
+ input [15:0] b,
+ input [15:0] c,
+ input [2:0] sel,
+ output reg [15:0] res
+ );
- always @* begin
- case(sel)
- 0: res = a + b;
- 1: res = a - b;
- 2: res = a + c;
- 3: res = a - c;
- 4: res = b;
- 5: res = c;
- default: res = 16'bx;
- endcase
- end
+ always @* begin
+ case(sel)
+ 0: res = a + b;
+ 1: res = a - b;
+ 2: res = a + c;
+ 3: res = a - c;
+ 4: res = b;
+ 5: res = c;
+ default: res = 16'bx;
+ endcase
+ end
endmodule
module opt_share_test(
- input [15:0] a,
- input [15:0] b,
- input [15:0] c,
- input [1:0] sel,
- output reg [15:0] res
- );
+ input [15:0] a,
+ input [15:0] b,
+ input [15:0] c,
+ input [1:0] sel,
+ output reg [15:0] res
+ );
- always @* begin
- case(sel)
- 0: res = a + b;
- 1: res = a - b;
- 2: res = a + c;
- default: res = 16'bx;
- endcase
- end
+ always @* begin
+ case(sel)
+ 0: res = a + b;
+ 1: res = a - b;
+ 2: res = a + c;
+ default: res = 16'bx;
+ endcase
+ end
endmodule