Tabs to spaces in opt_share examples
authorBogdan Vukobratovic <bogdan.vukobratovic@gmail.com>
Sat, 3 Aug 2019 10:35:46 +0000 (12:35 +0200)
committerBogdan Vukobratovic <bogdan.vukobratovic@gmail.com>
Sat, 3 Aug 2019 10:35:46 +0000 (12:35 +0200)
tests/opt/opt_share_add_sub.v
tests/opt/opt_share_cat.v
tests/opt/opt_share_cat_multiuser.v
tests/opt/opt_share_diff_port_widths.v
tests/opt/opt_share_extend.v
tests/opt/opt_share_large_pmux_cat.v
tests/opt/opt_share_large_pmux_cat_multipart.v
tests/opt/opt_share_large_pmux_multipart.v
tests/opt/opt_share_large_pmux_part.v
tests/opt/opt_share_mux_tree.v

index 1c2665cf04804d29ef126902d32d216562eab569..d918f27ccc3dbb15336401be743ba1fe1fdc4936 100644 (file)
@@ -1,10 +1,10 @@
 module opt_share_test(
-       input [15:0]    a,
-       input [15:0]    b,
-       input                           sel,
-       output [15:0] res,
-       );
+  input [15:0]  a,
+  input [15:0]  b,
+  input         sel,
+  output [15:0] res,
+  );
 
-       assign res = {sel ? a + b : a - b};
+  assign res = {sel ? a + b : a - b};
 
 endmodule
index 7b6f626b97d0e09ff780032a37f903f3188192cb..7fb97fef5faa8a73e037957ce1c5b8b76808a0a8 100644 (file)
@@ -1,15 +1,15 @@
 module opt_share_test(
-       input [15:0]    a,
-       input [15:0]    b,
-       input [15:0]    c,
-       input [15:0]    d,
-       input                           sel,
-       output [63:0] res,
-       );
+  input [15:0]  a,
+  input [15:0]  b,
+  input [15:0]  c,
+  input [15:0]  d,
+  input         sel,
+  output [63:0] res,
+  );
 
-       reg [31: 0]     cat1 = {a+b, c+d};
-       reg [31: 0]     cat2 = {a-b, c-d};
+  reg [31: 0]   cat1 = {a+b, c+d};
+  reg [31: 0]   cat2 = {a-b, c-d};
 
-       assign res = {b, sel ? cat1 : cat2, a};
+  assign res = {b, sel ? cat1 : cat2, a};
 
 endmodule
index f77f912e9cdc35aa3a7b03b6e50ed6c5149bea23..b250689d90baeb9058e406f03a61991bb5fb44b8 100644 (file)
@@ -1,22 +1,22 @@
 module opt_share_test(
-       input [15:0]                    a,
-       input [15:0]                    b,
-       input [15:0]                    c,
-       input [15:0]                    d,
-       input                                           sel,
-       output reg [47:0] res,
-       );
+  input [15:0]      a,
+  input [15:0]      b,
+  input [15:0]      c,
+  input [15:0]      d,
+  input             sel,
+  output reg [47:0] res,
+  );
 
-       wire [15:0]                     add_res = a+b;
-       wire [15:0]                     sub_res = a-b;
-       wire [31: 0]                    cat1 = {add_res, c+d};
-       wire [31: 0]                    cat2 = {sub_res, c-d};
+  wire [15:0]       add_res = a+b;
+  wire [15:0]       sub_res = a-b;
+  wire [31: 0]      cat1 = {add_res, c+d};
+  wire [31: 0]      cat2 = {sub_res, c-d};
 
-       always @* begin
-               case(sel)
-                       0: res = {cat1, add_res};
-                       1: res = {cat2, add_res};
-               endcase
-       end
+  always @* begin
+    case(sel)
+      0: res = {cat1, add_res};
+      1: res = {cat2, add_res};
+    endcase
+  end
 
 endmodule
index e57ab7a8353f58d1859c8fd586d48e3811575d12..1a37c80a6c89418e8f43cda33ef09f9f6cb4a1e3 100644 (file)
@@ -1,21 +1,21 @@
 module opt_share_test(
-       input [15:0]                     a,
-       input [15:0]                     b,
-       input [15:0]                     c,
-       input [1:0]                      sel,
-       output reg [15:0] res
-       );
+  input [15:0]       a,
+  input [15:0]       b,
+  input [15:0]       c,
+  input [1:0]      sel,
+  output reg [15:0] res
+  );
 
-       wire [15:0]                     add0_res = a+b;
-       wire [15:0]                     add1_res = a+c;
+  wire [15:0]       add0_res = a+b;
+  wire [15:0]       add1_res = a+c;
 
-       always @* begin
-               case(sel)
-                       0: res = add0_res[10:0];
-                       1: res = add1_res[10:0];
-                       2: res = a - b;
-                       default: res = 32'bx;
-               endcase
-       end
+  always @* begin
+    case(sel)
+      0: res = add0_res[10:0];
+      1: res = add1_res[10:0];
+      2: res = a - b;
+      default: res = 32'bx;
+    endcase
+  end
 
 endmodule
index 60ce1a2f39a9bfa96bb945fbbea1e78108ea8768..d39f190696439300a08a10e29997b9520c7e9342 100644 (file)
@@ -1,18 +1,18 @@
 module opt_share_test(
-       input signed [7:0]                       a,
-       input signed [10:0]                      b,
-       input signed [15:0]                      c,
-       input [1:0]                                                      sel,
-       output reg signed [15:0] res
-       );
+  input signed [7:0]       a,
+  input signed [10:0]      b,
+  input signed [15:0]      c,
+  input [1:0]              sel,
+  output reg signed [15:0] res
+  );
 
-       always @* begin
-               case(sel)
-                       0: res = a + b;
-                       1: res = a - b;
-                       2: res = a + c;
-                       default: res = 16'bx;
-               endcase
-       end
+  always @* begin
+    case(sel)
+      0: res = a + b;
+      1: res = a - b;
+      2: res = a + c;
+      default: res = 16'bx;
+    endcase
+  end
 
 endmodule
index 0667e60802656ab8556d929b794057f40926692f..416ba3766742f11d7c382c3bf8409d15aacbe224 100644 (file)
@@ -1,21 +1,21 @@
 module opt_share_test(
-       input [15:0]                    a,
-       input [15:0]                    b,
-       input [15:0]                    c,
-       input [2:0]                             sel,
-       output reg [31:0] res
-       );
+  input [15:0]      a,
+  input [15:0]      b,
+  input [15:0]      c,
+  input [2:0]       sel,
+  output reg [31:0] res
+  );
 
-       always @* begin
-               case(sel)
-                       0: res = {a + b, a};
-                       1: res = {a - b, b};
-                       2: res = {a + c, c};
-                       3: res = {a - c, a};
-                       4: res = {b, b};
-                       5: res = {c, c};
-                       default: res = 32'bx;
-               endcase
-       end
+  always @* begin
+    case(sel)
+      0: res = {a + b, a};
+      1: res = {a - b, b};
+      2: res = {a + c, c};
+      3: res = {a - c, a};
+      4: res = {b, b};
+      5: res = {c, c};
+      default: res = 32'bx;
+    endcase
+  end
 
 endmodule
index f26505d3a0f94e5034c159212280647d22809034..34d2bd9a8d057212ce3ffe3566bbd0fbce504b60 100644 (file)
@@ -1,25 +1,25 @@
 module opt_share_test(
-       input [15:0]                    a,
-       input [15:0]                    b,
-       input [15:0]                    c,
-       input [15:0]                    d,
-       input [2:0]                             sel,
-       output reg [31:0] res
-       );
+  input [15:0]      a,
+  input [15:0]      b,
+  input [15:0]      c,
+  input [15:0]      d,
+  input [2:0]       sel,
+  output reg [31:0] res
+  );
 
-       wire [15:0]                     add0_res = a+d;
+  wire [15:0]       add0_res = a+d;
 
-       always @* begin
-               case(sel)
-                       0: res = {add0_res, a};
-                       1: res = {a - b, add0_res[7], 15'b0};
-                       2: res = {b-a, b};
-                       3: res = {d, b - c};
-                       4: res = {d, b - a};
-                       5: res = {c, d};
-                       6: res = {a - c, b-d};
-                       default: res = 32'bx;
-               endcase
-       end
+  always @* begin
+    case(sel)
+      0: res = {add0_res, a};
+      1: res = {a - b, add0_res[7], 15'b0};
+      2: res = {b-a, b};
+      3: res = {d, b - c};
+      4: res = {d, b - a};
+      5: res = {c, d};
+      6: res = {a - c, b-d};
+      default: res = 32'bx;
+    endcase
+  end
 
 endmodule
index 1c460292f043241a941c912dfe91de93f7d57357..535adf96f4637142b6a93d9be6401efa5a6db003 100644 (file)
@@ -1,23 +1,23 @@
 module opt_share_test(
-       input [15:0]                    a,
-       input [15:0]                    b,
-       input [15:0]                    c,
-       input [15:0]                    d,
-       input [2:0]                             sel,
-       output reg [15:0] res
-       );
+  input [15:0]      a,
+  input [15:0]      b,
+  input [15:0]      c,
+  input [15:0]      d,
+  input [2:0]       sel,
+  output reg [15:0] res
+  );
 
-       always @* begin
-               case(sel)
-                       0: res = a + d;
-                       1: res = a - b;
-                       2: res = b;
-                       3: res = b - c;
-                       4: res = b - a;
-                       5: res = c;
-                       6: res = a - c;
-                       default: res = 16'bx;
-               endcase
-       end
+  always @* begin
+    case(sel)
+      0: res = a + d;
+      1: res = a - b;
+      2: res = b;
+      3: res = b - c;
+      4: res = b - a;
+      5: res = c;
+      6: res = a - c;
+      default: res = 16'bx;
+    endcase
+  end
 
 endmodule
index f9dd174466c0daadd6911105cff9db2d4a4afe72..a9008fb5a24542ae4a34778a9a0aedd588c8e4d7 100644 (file)
@@ -1,21 +1,21 @@
 module opt_share_test(
-       input [15:0]                    a,
-       input [15:0]                    b,
-       input [15:0]                    c,
-       input [2:0]                             sel,
-       output reg [15:0] res
-       );
+  input [15:0]      a,
+  input [15:0]      b,
+  input [15:0]      c,
+  input [2:0]       sel,
+  output reg [15:0] res
+  );
 
-       always @* begin
-               case(sel)
-                       0: res = a + b;
-                       1: res = a - b;
-                       2: res = a + c;
-                       3: res = a - c;
-                       4: res = b;
-                       5: res = c;
-                       default: res = 16'bx;
-               endcase
-       end
+  always @* begin
+    case(sel)
+      0: res = a + b;
+      1: res = a - b;
+      2: res = a + c;
+      3: res = a - c;
+      4: res = b;
+      5: res = c;
+      default: res = 16'bx;
+    endcase
+  end
 
 endmodule
index 4a26afb463019e25f9d450f3d709aecf5ecc885a..cc5ae4eb96df1b107f7d20952554afc73a4b3f25 100644 (file)
@@ -1,18 +1,18 @@
 module opt_share_test(
-       input [15:0]                    a,
-       input [15:0]                    b,
-       input [15:0]                    c,
-       input [1:0]                     sel,
-       output reg [15:0] res
-       );
+  input [15:0]      a,
+  input [15:0]      b,
+  input [15:0]      c,
+  input [1:0]       sel,
+  output reg [15:0] res
+  );
 
-       always @* begin
-               case(sel)
-                       0: res = a + b;
-                       1: res = a - b;
-                       2: res = a + c;
-                       default: res = 16'bx;
-               endcase
-       end
+  always @* begin
+    case(sel)
+      0: res = a + b;
+      1: res = a - b;
+      2: res = a + c;
+      default: res = 16'bx;
+    endcase
+  end
 
 endmodule