bank/csrgen: fix RE generation

diff --git a/migen/bank/csrgen.py b/migen/bank/csrgen.py
index fed5058dc57a756f626054491e2726382da07281..5f5437f34b00384cfd74bf247b6cdabf607e0bb5 100644 (file)
--- a/migen/bank/csrgen.py
+++ b/migen/bank/csrgen.py
@@ -27,6 +27,7 @@ class Bank:
                                        self.interface.we & \
                                        (self.interface.adr[:nbits] == Constant(i, BV(nbits)))))
                        elif isinstance(reg, RegisterFields):
+                               sync.append(reg.re.eq(0))
                                bwra = [Constant(i, BV(nbits))]
                                offset = 0
                                for field in reg.fields: