O3: Skipping mem-order violation check for uncachable loads.

Uncachable load is not executed until it reaches the head of the ROB,
hence cannot cause one.

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 59149c8c37a4cabb2e2b83a3689c9f9ffe4d94dc..3f8f84cab126e10d82eacb2070fd30e6d0d18cbd 100644 (file)
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1150,9 +1150,9 @@ DefaultFetch<Impl>::fetch(bool &status_change)
 
                 instruction->setThreadState(cpu->thread[tid]);
 
-                DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
-                        "[sn:%lli]\n",
-                        tid, instruction->readPC(), inst_seq);
+                DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created "
+                        "[sn:%lli]\n", tid, instruction->readPC(),
+                        instruction->readMicroPC(), inst_seq);
 
                 //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst);
 

diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index abb941ef7901932d19876afd335d46fa79ada76c..2089913efd503f362acb49963a69067965b7582c 100644 (file)
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -1318,10 +1318,10 @@ DefaultIEW<Impl>::executeInsts()
                 DynInstPtr violator;
                 violator = ldstQueue.getMemDepViolator(tid);
 
-                DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
-                        "%#x, inst PC: %#x.  Addr is: %#x.\n",
-                        violator->readPC(), inst->readPC(), inst->physEffAddr);
-
+                DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %#x "
+                        "[sn:%lli], inst PC: %#x [sn:%lli]. Addr is: %#x.\n",
+                        violator->readPC(), violator->seqNum,
+                        inst->readPC(), inst->seqNum, inst->physEffAddr);
                 // Ensure the violating instruction is older than
                 // current squash
 /*                if (fetchRedirect[tid] &&

diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 7330ba2ef0c1b5069579ceffddf84312808cd8c3..8aa7fe3971a68ea1572ba78fab5070f3bd649d44 100644 (file)
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -479,9 +479,14 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
             // are quad word accesses.
 
             // @todo: Fix this, magic number being used here
+
+            // @todo: Uncachable load is not executed until it reaches
+            // the head of the ROB. Once this if checks only the executed
+            // loads(as noted above), this check can be removed
             if (loadQueue[load_idx]->effAddrValid &&
-                (loadQueue[load_idx]->effAddr >> 8) ==
-                (inst->effAddr >> 8)) {
+                ((loadQueue[load_idx]->effAddr >> 8)
+                 == (inst->effAddr >> 8)) &&
+                !loadQueue[load_idx]->uncacheable()) {
                 // A load incorrectly passed this load.  Squash and refetch.
                 // For now return a fault to show that it was unsuccessful.
                 DynInstPtr violator = loadQueue[load_idx];
@@ -553,9 +558,14 @@ LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
         // are quad word accesses.
 
         // @todo: Fix this, magic number being used here
+
+        // @todo: Uncachable load is not executed until it reaches
+        // the head of the ROB. Once this if checks only the executed
+        // loads(as noted above), this check can be removed
         if (loadQueue[load_idx]->effAddrValid &&
-            (loadQueue[load_idx]->effAddr >> 8) ==
-            (store_inst->effAddr >> 8)) {
+            ((loadQueue[load_idx]->effAddr >> 8)
+             == (store_inst->effAddr >> 8)) &&
+            !loadQueue[load_idx]->uncacheable()) {
             // A load incorrectly passed this store.  Squash and refetch.
             // For now return a fault to show that it was unsuccessful.
             DynInstPtr violator = loadQueue[load_idx];