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increase addr_wid to 64 in TestRunnerBase. hm this should not
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 10 Jan 2022 16:09:54 +0000 (16:09 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 10 Jan 2022 16:10:04 +0000 (16:10 +0000)
be importing from soc, openpower-isa should be entirely independent

src/openpower/test/runner.py patch | blob | history

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index 52091d925daca76ee1c92083955fd2cf86fa1197..fb0c8dbdb52b8b5a75ddb2b8705a7700ee30b2f8 100644 (file)
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -143,7 +143,7 @@ class TestRunnerBase(FHDLTestCase):
 
         pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
                              imem_ifacetype=imem_ifacetype,
-                             addr_wid=48,
+                             addr_wid=64,
                              mask_wid=8,
                              imem_reg_wid=64,
                              # wb_data_width=32,