Replace Signal(bits_for(... with Signal(max=...

diff --git a/examples/basic/arrays.py b/examples/basic/arrays.py
index d8152c7e53dd5781a8cc166258c3efde808e451e..10b5530e0a7d64e80daf8084e1089b6bcb662b60 100644 (file)
--- a/examples/basic/arrays.py
+++ b/examples/basic/arrays.py
@@ -4,8 +4,8 @@ from migen.fhdl import verilog
 dx = 5
 dy = 5
 
-x = Signal(bits_for(dx-1))
-y = Signal(bits_for(dy-1))
+x = Signal(max=dx)
+y = Signal(max=dy)
 out = Signal()
 
 my_2d_array = Array(Array(Signal() for a in range(dx)) for b in range(dy))

diff --git a/migen/actorlib/structuring.py b/migen/actorlib/structuring.py
index 27b08da572edf7fd398ee057a38b178667a2ee4c..2fc3985a8108d82fbb590d0604be3978ac8847e3 100644 (file)
--- a/migen/actorlib/structuring.py
+++ b/migen/actorlib/structuring.py
@@ -33,8 +33,7 @@ class Unpack(Actor):
                        ("source", Source, layout_to))
        
        def get_fragment(self):
-               muxbits = bits_for(self.n-1)
-               mux = Signal(muxbits)
+               mux = Signal(max=self.n)
                last = Signal()
                comb = [
                        last.eq(mux == (self.n-1)),
@@ -64,8 +63,7 @@ class Pack(Actor):
                        ("source", Source, pack_layout(layout_from, n)))
        
        def get_fragment(self):
-               demuxbits = bits_for(self.n-1)
-               demux = Signal(demuxbits)
+               demux = Signal(max=self.n)
                
                load_part = Signal()
                strobe_all = Signal()

diff --git a/migen/bus/asmibus.py b/migen/bus/asmibus.py
index cf7e7977547061a8cc41556ddae5c33653892af0..ff7b192726c39a8ae3e03a639a6f0dbe11239942 100644 (file)
--- a/migen/bus/asmibus.py
+++ b/migen/bus/asmibus.py
@@ -15,7 +15,7 @@ class Slot:
                self.adr = Signal(aw)
                self.time = time
                if self.time:
-                       self._counter = Signal(bits_for(time))
+                       self._counter = Signal(max=time+1)
                        self.mature = Signal()
                
                self.allocate = Signal()
@@ -76,7 +76,7 @@ class Port:
                self.base = base
                nslots = len(self.slots)
                if nslots > 1:
-                       self.tag_issue = Signal(bits_for(nslots-1))
+                       self.tag_issue = Signal(max=nslots)
                self.tag_call = Signal(tagbits)
        
        def get_call_expression(self, slotn=0):

diff --git a/migen/corelogic/divider.py b/migen/corelogic/divider.py
index 1c12b8f98c9503ee47a8bb06653969809431111c..62b87c21004374c2110d7614dd5514563e91156a 100644 (file)
--- a/migen/corelogic/divider.py
+++ b/migen/corelogic/divider.py
@@ -15,7 +15,7 @@ class Divider:
                w = self.w
                
                qr = Signal(2*w)
-               counter = Signal(bits_for(w))
+               counter = Signal(max=w+1)
                divisor_r = Signal(w)
                diff = Signal(w+1)
                

diff --git a/migen/corelogic/misc.py b/migen/corelogic/misc.py
index 357271f1f1bcfb6fd13a9ac23d2372e1874693a6..fc0469dbe94f7231c99aff9e8c12e5b10dd0f25b 100644 (file)
--- a/migen/corelogic/misc.py
+++ b/migen/corelogic/misc.py
@@ -54,7 +54,7 @@ def chooser(signal, shift, output, n=None, reverse=False):
 
 def timeline(trigger, events):
        lastevent = max([e[0] for e in events])
-       counter = Signal(bits_for(lastevent))
+       counter = Signal(max=lastevent+1)
        
        counterlogic = If(counter != 0,
                counter.eq(counter + 1)

diff --git a/migen/corelogic/roundrobin.py b/migen/corelogic/roundrobin.py
index 204afa7f3423ce97de277d25141ecca6511bc814..0b33344bbd56a5865042a220495f0ad15857cf4f 100644 (file)
--- a/migen/corelogic/roundrobin.py
+++ b/migen/corelogic/roundrobin.py
@@ -5,8 +5,7 @@ from migen.fhdl.structure import *
 class RoundRobin:
        def __init__(self, n, switch_policy=SP_WITHDRAW):
                self.n = n
-               self.bn = bits_for(self.n-1)
-               self.request = Signal(self.n)
+               self.request = Signal(max=self.n)
                self.grant = Signal(self.bn)
                self.switch_policy = switch_policy
                if self.switch_policy == SP_CE:

diff --git a/migen/flow/actor.py b/migen/flow/actor.py
index 4fa6acaa6904ed2e7ec6161fc29659ebd6f7d9eb..5552624cfa1becbf9ab93142f1557b847ee7cedb 100644 (file)
--- a/migen/flow/actor.py
+++ b/migen/flow/actor.py
@@ -112,7 +112,7 @@ class SequentialActor(BinaryActor):
 
        def get_binary_control_fragment(self, stb_i, ack_o, stb_o, ack_i):
                ready = Signal()
-               timer = Signal(bits_for(self.delay))
+               timer = Signal(max=self.delay+1)
                comb = [ready.eq(timer == 0)]
                sync = [
                        If(self.trigger,