## Submitted for NLNet RFP
+### NLnet.2019.02.012
+
+* [Bug #583](https://bugs.libre-soc.org/show_bug.cgi?id=583):
+ Implement simple VL for\-loop in nMigen for TestIssuer
+ * €2325 which is the total amount
+ * submitted on 2022-06-16
+
+### NLNet.2019.10.032.Formal
+
+* [Bug #565](https://bugs.libre-soc.org/show_bug.cgi?id=565):
+ Improve formal verification on PartitionedSignal
+ * €2200 out of total of €3000
+ * submitted on 2022-06-16
+
+### NLNet.2019.10.046.Standards
+
+* [Bug #588](https://bugs.libre-soc.org/show_bug.cgi?id=588):
+ add SVP64 to PowerDecoder2
+ * €300 out of total of €1000
+ * submitted on 2022-06-16
+
## Paid
### NLNet.2019.10.Wishbone