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diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index a7f3a0bc24635521b6d2ff1b89915f0072edd037..a08bce243bc4646401a1c0f59f706a26a9944135 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -36,11 +36,13 @@ them.
 
 Therefore because the goal of RED Semiconductor Ltd, an OpenPOWER Stakeholder,
 is to bring to market mass-volume general-purpose compute processors that
-are competitive in the 3D GPU Audio Visual DSP EDGE IoT markets, Simple-V
+are competitive in the 3D GPU Audio Visual DSP EDGE IoT desktop
+chromebook netbook smartphone laptop markets, Simple-V
 has to be accompanied by corresponding **Scalar** instructions that bring
 the **Scalar** Power ISA up-to-date.  These include IEEE754 Transcendentals
 AV cryptographic Biginteger and bitmanipulation operations that ARM Intel
-AMD and many other ISAs have been adding over the past 12 years.
+AMD and many other ISAs have been adding over the past 12 years and Power ISA
+has not.
 
 *Thus it becomes necesary to consider the Architectural Resource Allocation of not just
 Simple-V but the 80-100 Scalar instructions all at the same time*.