stats: Update stats for clean eviction addition
authorAndreas Hansson <andreas.hansson@arm.com>
Thu, 30 Jul 2015 07:42:27 +0000 (03:42 -0400)
committerAndreas Hansson <andreas.hansson@arm.com>
Thu, 30 Jul 2015 07:42:27 +0000 (03:42 -0400)
17 files changed:
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt

index b25b92aa695651596301713e1a187f561654b8b5..5b4459bdf94cf06c25339b48c772154d0142b10c 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.846047                       # Number of seconds simulated
-sim_ticks                                2846047385500                       # Number of ticks simulated
-final_tick                               2846047385500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.846057                       # Number of seconds simulated
+sim_ticks                                2846057099000                       # Number of ticks simulated
+final_tick                               2846057099000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 159625                       # Simulator instruction rate (inst/s)
-host_op_rate                                   193311                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3563510303                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 654020                       # Number of bytes of host memory used
-host_seconds                                   798.66                       # Real time elapsed on the host
-sim_insts                                   127487011                       # Number of instructions simulated
-sim_ops                                     154390534                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 155095                       # Simulator instruction rate (inst/s)
+host_op_rate                                   187821                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3461671389                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 654788                       # Number of bytes of host memory used
+host_seconds                                   822.16                       # Real time elapsed on the host
+sim_insts                                   127513349                       # Number of instructions simulated
+sim_ops                                     154419501                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker         7424                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         7744                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1468992                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1221616                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      8255360                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker         2560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           381888                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           706136                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher       588160                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1469184                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1233972                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8227712                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker         2752                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           383104                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           711064                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       574528                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12633224                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1468992                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       381888                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1850880                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8928128                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12611084                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1469184                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       383104                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1852288                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8917568                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8945692                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker          116                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8935132                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker          121                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             22953                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             19610                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       128990                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           40                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              5967                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             11055                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher         9190                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             22956                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             19804                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       128558                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           43                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              5986                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             11132                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher         8977                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                197938                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          139502                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                197593                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          139337                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               143893                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2609                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               143728                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2721                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              516152                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              429232                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      2900640                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           899                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              134182                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              248111                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       206659                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              516217                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              433572                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      2890916                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           967                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              134609                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              249842                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       201868                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4438866                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         516152                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         134182                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             650334                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3137027                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4431072                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         516217                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         134609                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             650826                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3133306                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6157                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3143199                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3137027                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2609                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3139477                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3133306                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2721                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             516152                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             435390                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      2900640                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          899                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             134182                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             248125                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       206659                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             516217                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             439730                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      2890916                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          967                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             134609                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             249856                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       201868                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7582065                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        197938                       # Number of read requests accepted
-system.physmem.writeReqs                       143893                       # Number of write requests accepted
-system.physmem.readBursts                      197938                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     143893                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12658432                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9600                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8958080                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12633224                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8945692                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      150                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3897                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          51249                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               12124                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               12298                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12956                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               12344                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               15465                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               12573                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12691                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               13082                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               12243                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               12357                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11723                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11147                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              12049                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11871                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              11344                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11521                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8574                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8801                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9504                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8801                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8786                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8838                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9085                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                9267                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8941                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8908                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8524                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8283                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8972                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8287                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8306                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8093                       # Per bank write bursts
+system.physmem.bw_total::total                7570549                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        197593                       # Number of read requests accepted
+system.physmem.writeReqs                       143728                       # Number of write requests accepted
+system.physmem.readBursts                      197593                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     143728                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12635520                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     10432                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8947648                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12611084                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8935132                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      163                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          51189                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               12157                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               12292                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               12950                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12405                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               15321                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12434                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12677                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               13084                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               12267                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               12426                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11655                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11073                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11997                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11769                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11320                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11603                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8631                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8804                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9518                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8865                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8658                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8780                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                9135                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                9275                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8996                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8951                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8409                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               8136                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8895                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8304                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8310                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               8140                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          26                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2846046899000                       # Total gap between requests
+system.physmem.numWrRetry                          40                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2846056522500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                     554                       # Read request sizes (log2)
+system.physmem.readPktSize::2                     555                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  197356                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  197010                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 139502                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     97008                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     48975                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     12438                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      9719                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      7811                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      6380                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      5314                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4715                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3822                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       751                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      280                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 139337                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     84527                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     62953                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     11439                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      9638                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      7653                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      6151                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      5113                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4583                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3751                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       746                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      272                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::11                      267                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      162                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      133                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      175                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      149                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -188,157 +184,159 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2733                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4836                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5514                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6014                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6576                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6962                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8463                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8832                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    10148                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9569                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9515                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8822                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9294                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10498                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8607                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8058                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7671                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      489                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      332                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      297                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      248                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      206                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      170                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      187                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       93                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        90544                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      238.739707                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     135.462322                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     300.134416                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          48559     53.63%     53.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17642     19.48%     73.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6276      6.93%     80.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3581      3.95%     84.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2857      3.16%     87.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1437      1.59%     88.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          927      1.02%     89.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1107      1.22%     90.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8158      9.01%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          90544                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6994                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        28.279525                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      555.958801                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6993     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6994                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6994                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.012868                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.560049                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.293161                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5872     83.96%     83.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             361      5.16%     89.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             205      2.93%     92.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              59      0.84%     92.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              60      0.86%     93.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             157      2.24%     96.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              22      0.31%     96.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               8      0.11%     96.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              14      0.20%     96.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               7      0.10%     96.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               6      0.09%     96.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               8      0.11%     96.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             162      2.32%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               3      0.04%     99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               7      0.10%     99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               9      0.13%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               3      0.04%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.01%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.01%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.01%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             1      0.01%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.01%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            12      0.17%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             2      0.03%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             3      0.04%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             6      0.09%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             2      0.03%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-203             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6994                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     5635724944                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9344249944                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    988940000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       28493.77                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                     2731                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4878                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5520                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6053                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6627                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7062                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     8465                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8859                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    10175                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9630                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9702                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8882                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     9201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    10384                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8548                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7940                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7665                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      412                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      342                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      221                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      188                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      157                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      115                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      131                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       88                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       29                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       33                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      106                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        90385                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      238.790065                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     135.540737                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     300.321787                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          48391     53.54%     53.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17645     19.52%     73.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6369      7.05%     80.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3664      4.05%     84.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2743      3.03%     87.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1397      1.55%     88.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          884      0.98%     89.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1036      1.15%     90.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8256      9.13%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          90385                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6985                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        28.264567                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      537.756673                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6984     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::43008-45055            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6985                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6985                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.015319                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.579154                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.029266                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5867     83.99%     83.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             359      5.14%     89.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             198      2.83%     91.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              50      0.72%     92.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              72      1.03%     93.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             159      2.28%     95.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              19      0.27%     96.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              12      0.17%     96.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              11      0.16%     96.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               8      0.11%     96.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               6      0.09%     96.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               5      0.07%     96.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             162      2.32%     99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               6      0.09%     99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               6      0.09%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              10      0.14%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.01%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               2      0.03%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               2      0.03%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.03%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.01%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.01%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.01%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.01%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            14      0.20%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.01%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             4      0.06%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             3      0.04%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6985                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     5478181174                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9179993674                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    987150000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       27747.46                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  47243.77                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.45                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.15                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.44                       # Average system read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  46497.46                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.44                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.14                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.43                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        3.14                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.06                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.58                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     164502                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     82711                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.17                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  59.08                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8325888.81                       # Average gap between requests
+system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.99                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     164056                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     82794                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.10                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  59.21                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8338357.51                       # Average gap between requests
 system.physmem.pageHitRate                      73.19                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  356257440                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  194386500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 807557400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                464330880                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           185889868320                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            83150566875                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1634688457500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1905551424915                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.543458                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2719326804644                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     95035720000                       # Time in different power states
+system.physmem_0.actEnergy                  356771520                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  194667000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 805888200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                464395680                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           185890376880                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            83219414895                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1634632736250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1905564250425                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.546132                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2719229075521                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     95035980000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     31683407856                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     31791929979                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  328255200                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  179107500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 735181200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                442674720                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           185889868320                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            82066427730                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1635639456750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1905280971420                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.448430                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2720915660225                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     95035720000                       # Time in different power states
+system.physmem_1.actEnergy                  326539080                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  178171125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 734050200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                441553680                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           185890376880                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            82136174355                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1635582947250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1905289812570                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.449705                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2720812978493                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     95035980000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30095909775                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     30205644507                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          512                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          832                       # Number of bytes read from this memory
@@ -364,15 +362,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               19568417                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         12741959                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           982246                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            12413476                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                8819135                       # Number of BTB hits
+system.cpu0.branchPred.lookups               19599196                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         12768904                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           991514                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            12558764                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                8839837                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            71.044847                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                3284365                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            198035                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            70.387795                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                3295346                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            199810                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -403,58 +401,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                    67683                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               67683                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        45041                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        22642                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples        67683                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0          67683    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        67683                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples         6748                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 10568.612922                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean  9555.209008                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  5781.304513                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383         6579     97.50%     97.50% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767          156      2.31%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151            6      0.09%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-98303            4      0.06%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-114687            2      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-212991            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total         6748                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks                    67395                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               67395                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        44710                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        22685                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples        67395                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0          67395    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        67395                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples         6692                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 10409.593545                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean  9352.624092                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  5969.180600                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383         6501     97.15%     97.15% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767          173      2.59%     99.73% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151           11      0.16%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::81920-98303            5      0.07%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-114687            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::212992-229375            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total         6692                       # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walksPending::samples    327753000                       # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::0      327753000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::total    327753000                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         5177     76.72%     76.72% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1571     23.28%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         6748                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        67683                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K         5137     76.76%     76.76% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1555     23.24%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         6692                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        67395                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        67683                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6748                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        67395                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6692                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6748                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        74431                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6692                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        74087                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    16473000                       # DTB read hits
-system.cpu0.dtb.read_misses                     62137                       # DTB read misses
-system.cpu0.dtb.write_hits                   13870452                       # DTB write hits
-system.cpu0.dtb.write_misses                     5546                       # DTB write misses
+system.cpu0.dtb.read_hits                    16492967                       # DTB read hits
+system.cpu0.dtb.read_misses                     61485                       # DTB read misses
+system.cpu0.dtb.write_hits                   13879033                       # DTB write hits
+system.cpu0.dtb.write_misses                     5910                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3508                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1130                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1591                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3512                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1104                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  1584                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      561                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                16535137                       # DTB read accesses
-system.cpu0.dtb.write_accesses               13875998                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      553                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                16554452                       # DTB read accesses
+system.cpu0.dtb.write_accesses               13884943                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         30343452                       # DTB hits
-system.cpu0.dtb.misses                          67683                       # DTB misses
-system.cpu0.dtb.accesses                     30411135                       # DTB accesses
+system.cpu0.dtb.hits                         30372000                       # DTB hits
+system.cpu0.dtb.misses                          67395                       # DTB misses
+system.cpu0.dtb.accesses                     30439395                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -484,36 +482,36 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                     3854                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                3854                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walks                     3867                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                3867                       # Table walker walks initiated with short descriptors
 system.cpu0.itb.walker.walksShortTerminationLevel::Level1          307                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3547                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples         3854                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0           3854    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         3854                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         2418                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 10984.077750                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean  9918.433232                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  7783.469031                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-32767         2416     99.92%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3560                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples         3867                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0           3867    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         3867                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         2421                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 10756.092524                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean  9615.276250                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  7885.681727                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767         2419     99.92%     99.92% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::32768-65535            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::294912-327679            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         2418                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total         2421                       # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walksPending::samples    327059500                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::0      327059500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::total    327059500                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         2118     87.59%     87.59% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          300     12.41%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2418                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K         2121     87.61%     87.61% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          300     12.39%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2421                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3854                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3854                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3867                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3867                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2418                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2418                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total         6272                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    36667532                       # ITB inst hits
-system.cpu0.itb.inst_misses                      3854                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2421                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2421                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         6288                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    36759532                       # ITB inst hits
+system.cpu0.itb.inst_misses                      3867                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -522,131 +520,131 @@ system.cpu0.itb.flush_tlb                          66                       # Nu
 system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2221                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2224                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     7326                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     7295                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                36671386                       # ITB inst accesses
-system.cpu0.itb.hits                         36667532                       # DTB hits
-system.cpu0.itb.misses                           3854                       # DTB misses
-system.cpu0.itb.accesses                     36671386                       # DTB accesses
-system.cpu0.numCycles                       154642199                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                36763399                       # ITB inst accesses
+system.cpu0.itb.hits                         36759532                       # DTB hits
+system.cpu0.itb.misses                           3867                       # DTB misses
+system.cpu0.itb.accesses                     36763399                       # DTB accesses
+system.cpu0.numCycles                       154883476                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   75578579                       # Number of instructions committed
-system.cpu0.committedOps                     90977347                       # Number of ops (including micro ops) committed
-system.cpu0.discardedOps                      4937651                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends                     2060                       # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles                  5537489017                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi                              2.046111                       # CPI: cycles per instruction
-system.cpu0.ipc                              0.488732                       # IPC: instructions per cycle
+system.cpu0.committedInsts                   75627253                       # Number of instructions committed
+system.cpu0.committedOps                     91033342                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                      4957970                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                     2062                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                  5537267530                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                              2.047985                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.488285                       # IPC: instructions per cycle
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    2062                       # number of quiesce instructions executed
-system.cpu0.tickCycles                      120829876                       # Number of cycles that the object actually ticked
-system.cpu0.idleCycles                       33812323                       # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements           679563                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          486.133146                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           28909958                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           680075                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            42.509956                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        345411000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   486.133146                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.949479                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.949479                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                    2064                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      121009607                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                       33873869                       # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements           680149                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          489.017964                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           28930962                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           680661                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            42.504216                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        345600000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   489.017964                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.955113                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.955113                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0          135                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          316                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           61                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          315                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           62                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         60679422                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        60679422                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     14995018                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       14995018                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     12788335                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      12788335                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       306891                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       306891                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       356622                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       356622                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       352102                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       352102                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     27783353                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        27783353                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     28090244                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       28090244                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       441719                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       441719                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       557349                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       557349                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       131939                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       131939                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21205                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        21205                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        21309                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        21309                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       999068                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        999068                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1131007                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1131007                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5838844500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   5838844500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   8827018500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   8827018500                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    323291000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    323291000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    480994000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    480994000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       412000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total       412000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  14665863000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  14665863000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  14665863000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  14665863000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     15436737                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     15436737                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     13345684                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     13345684                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       438830                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       438830                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       377827                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       377827                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       373411                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       373411                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     28782421                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     28782421                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     29221251                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     29221251                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.028615                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.028615                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.041762                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.041762                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.300661                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.300661                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056124                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056124                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.057066                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.057066                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.tags.tag_accesses         60723709                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        60723709                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     15008806                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       15008806                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     12795540                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      12795540                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       306691                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       306691                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       356713                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       356713                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       352309                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       352309                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     27804346                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        27804346                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     28111037                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       28111037                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       442745                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       442745                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       557072                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       557072                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       131875                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       131875                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21262                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        21262                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        21236                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        21236                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       999817                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        999817                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1131692                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1131692                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5845429500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   5845429500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   8925410000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   8925410000                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    323710500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    323710500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    479970000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    479970000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       445000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total       445000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  14770839500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  14770839500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  14770839500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  14770839500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     15451551                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     15451551                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     13352612                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     13352612                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       438566                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       438566                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       377975                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       377975                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       373545                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       373545                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     28804163                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     28804163                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     29242729                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     29242729                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.028654                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.028654                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.041720                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.041720                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.300696                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.300696                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056252                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056252                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.056850                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.056850                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.demand_miss_rate::cpu0.data     0.034711                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::total     0.034711                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.038705                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.038705                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13218.459020                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13218.459020                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15837.506661                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 15837.506661                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15245.979722                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15245.979722                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22572.340326                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22572.340326                       # average StoreCondReq miss latency
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.038700                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.038700                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13202.700200                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13202.700200                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16022.004337                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 16022.004337                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15224.837739                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15224.837739                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22601.714070                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22601.714070                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14679.544335                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 14679.544335                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12967.084200                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 12967.084200                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14773.543058                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 14773.543058                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13051.996038                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 13051.996038                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -655,149 +653,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       493293                       # number of writebacks
-system.cpu0.dcache.writebacks::total           493293                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        69842                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        69842                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       244235                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       244235                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15018                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15018                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data       314077                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       314077                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data       314077                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       314077                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       371877                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       371877                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       313114                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       313114                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        99356                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total        99356                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6187                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6187                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        21309                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        21309                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       684991                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       684991                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       784347                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       784347                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        18002                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        18002                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16758                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        16758                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        34760                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        34760                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4380232500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4380232500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4918203500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4918203500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1623471000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1623471000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     94288500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     94288500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    459695000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    459695000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       402000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       402000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9298436000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   9298436000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10921907000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  10921907000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3751545500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3751545500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2725656000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2725656000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6477201500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6477201500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.024090                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024090                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023462                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.023462                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.226411                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.226411                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016375                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016375                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.057066                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.057066                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023799                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.023799                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026842                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.026842                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11778.713123                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11778.713123                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15707.389321                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15707.389321                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16339.939209                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16339.939209                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15239.776952                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15239.776952                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21572.809611                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21572.809611                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       493052                       # number of writebacks
+system.cpu0.dcache.writebacks::total           493052                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        69962                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        69962                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       244118                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       244118                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15072                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15072                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data       314080                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       314080                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data       314080                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       314080                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       372783                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       372783                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       312954                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       312954                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        99314                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total        99314                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6190                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6190                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        21236                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        21236                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       685737                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       685737                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       785051                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       785051                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        18001                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        18001                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16756                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        16756                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        34757                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        34757                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4391149500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4391149500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4970740000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4970740000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1612906500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1612906500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     94756000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     94756000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    458745000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    458745000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       434000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       434000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9361889500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   9361889500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10974796000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  10974796000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3751362500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3751362500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2725552500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2725552500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6476915000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6476915000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.024126                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024126                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023438                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.023438                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.226452                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.226452                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016377                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016377                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.056850                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.056850                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023807                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.023807                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026846                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.026846                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11779.371645                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11779.371645                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15883.292752                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15883.292752                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16240.474656                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16240.474656                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15307.915994                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15307.915994                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21602.232059                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21602.232059                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13574.537476                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13574.537476                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13924.840664                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13924.840664                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208396.039329                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208396.039329                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162648.048693                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162648.048693                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 186340.664557                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 186340.664557                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13652.303288                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13652.303288                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13979.723610                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13979.723610                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208397.450142                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208397.450142                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162661.285510                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162661.285510                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 186348.505337                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 186348.505337                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1878063                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.785549                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           34781277                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1878575                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            18.514713                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       6156628000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.785549                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.replacements          1879741                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.785261                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           34871642                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1880253                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            18.546250                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       6165545000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.785261                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999581                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999581                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          179                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          226                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          107                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          182                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          231                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           99                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         75198332                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        75198332                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     34781277                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       34781277                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     34781277                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        34781277                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     34781277                       # number of overall hits
-system.cpu0.icache.overall_hits::total       34781277                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1878593                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1878593                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1878593                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1878593                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1878593                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1878593                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  17494191500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  17494191500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  17494191500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  17494191500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  17494191500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  17494191500                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     36659870                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     36659870                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     36659870                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     36659870                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     36659870                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     36659870                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.051244                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.051244                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.051244                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.051244                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.051244                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.051244                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9312.390443                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9312.390443                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9312.390443                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  9312.390443                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9312.390443                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  9312.390443                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses         75384087                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        75384087                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     34871642                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       34871642                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     34871642                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        34871642                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     34871642                       # number of overall hits
+system.cpu0.icache.overall_hits::total       34871642                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1880268                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1880268                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1880268                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1880268                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1880268                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1880268                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  17494991000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  17494991000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  17494991000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  17494991000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  17494991000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  17494991000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     36751910                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     36751910                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     36751910                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     36751910                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     36751910                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     36751910                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.051161                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.051161                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.051161                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.051161                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.051161                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.051161                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9304.519888                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9304.519888                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9304.519888                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9304.519888                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9304.519888                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9304.519888                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -806,463 +804,463 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1878593                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1878593                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1878593                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1878593                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1878593                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1878593                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1880268                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1880268                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      1880268                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1880268                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      1880268                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1880268                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3426                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total         3426                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3426                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total         3426                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  16554895500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  16554895500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  16554895500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  16554895500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  16554895500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  16554895500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  16554857500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  16554857500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  16554857500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  16554857500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  16554857500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  16554857500                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    314279000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    314279000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    314279000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total    314279000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.051244                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.051244                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.051244                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.051244                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.051244                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.051244                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8812.390709                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8812.390709                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8812.390709                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  8812.390709                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8812.390709                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  8812.390709                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.051161                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.051161                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.051161                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.051161                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.051161                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.051161                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8804.520154                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8804.520154                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8804.520154                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  8804.520154                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8804.520154                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  8804.520154                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91733.508465                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91733.508465                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      1765882                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      1765970                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit           77                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      1762988                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      1763146                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit          137                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       224118                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements          286262                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16059.277635                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           4797112                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          302498                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs           15.858326                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage       223158                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements          285163                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16064.441291                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           4801094                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          301400                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs           15.929310                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  8723.236364                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    43.341002                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.066911                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4602.822845                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1559.466000                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1130.344513                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.532424                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002645                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_blocks::writebacks  8613.892017                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    45.679204                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.072727                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4663.239886                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1620.721287                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1120.836170                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.525750                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002788                       # Average percentage of cache occupancy
 system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000004                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.280934                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.095182                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.068991                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.980181                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1044                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           15                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15177                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.284622                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.098921                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.068410                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.980496                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1029                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023            9                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15199                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           13                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          332                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          429                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          270                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          305                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          401                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          310                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           10                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            4                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4328                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7768                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2750                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.063721                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000916                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.926331                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        85339399                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       85339399                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        80048                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4433                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total         84481                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks       493290                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total       493290                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28251                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total        28251                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1773                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total         1773                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       213027                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       213027                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1814336                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      1814336                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       376020                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total       376020                       # number of ReadSharedReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        80048                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4433                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      1814336                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       589047                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        2487864                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        80048                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4433                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      1814336                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       589047                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       2487864                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          723                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          114                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total          837                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        27851                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        27851                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19535                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        19535                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4239                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7941                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2698                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.062805                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000549                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.927673                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        85389688                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses       85389688                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        78899                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4233                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total         83132                       # number of ReadReq hits
+system.cpu0.l2cache.Writeback_hits::writebacks       493050                       # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total       493050                       # number of Writeback hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28200                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total        28200                       # number of UpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1701                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::total         1701                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       212815                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       212815                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1816263                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      1816263                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       377267                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total       377267                       # number of ReadSharedReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        78899                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4233                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      1816263                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data       590082                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total        2489477                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        78899                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4233                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      1816263                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data       590082                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total       2489477                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          767                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          105                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total          872                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        27843                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total        27843                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19534                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total        19534                       # number of SCUpgradeReq misses
 system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            1                       # number of SCUpgradeFailReq misses
 system.cpu0.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data        43989                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total        43989                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        64257                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total        64257                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       101397                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total       101397                       # number of ReadSharedReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          723                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker          114                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst        64257                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data       145386                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total       210480                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          723                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker          114                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst        64257                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data       145386                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total       210480                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     24794500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2781500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total     27576000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    513504000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total    513504000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    395434500                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    395434500                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       385999                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       385999                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2149567499                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total   2149567499                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   2872366000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total   2872366000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   2916301996                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total   2916301996                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     24794500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2781500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst   2872366000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data   5065869495                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total   7965811495                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     24794500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2781500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst   2872366000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data   5065869495                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total   7965811495                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        80771                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4547                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total        85318                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks       493290                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total       493290                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        56102                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total        56102                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        21308                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total        21308                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data        44100                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total        44100                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        64005                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total        64005                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       101018                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total       101018                       # number of ReadSharedReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          767                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker          105                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst        64005                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data       145118                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total       209995                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          767                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker          105                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst        64005                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data       145118                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total       209995                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     26175500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2558000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total     28733500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    514961000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total    514961000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    395123500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    395123500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       417500                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       417500                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2206381000                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total   2206381000                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   2858183000                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total   2858183000                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   2907472497                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total   2907472497                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     26175500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2558000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst   2858183000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data   5113853497                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total   8000769997                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     26175500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2558000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst   2858183000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data   5113853497                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total   8000769997                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        79666                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4338                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total        84004                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::writebacks       493050                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total       493050                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        56043                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total        56043                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        21235                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total        21235                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
 system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       257016                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total       257016                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1878593                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      1878593                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       477417                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total       477417                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        80771                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4547                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      1878593                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data       734433                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total      2698344                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        80771                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4547                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      1878593                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data       734433                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total      2698344                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.008951                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.025071                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.009810                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.496435                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.496435                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.916792                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.916792                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       256915                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total       256915                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1880268                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      1880268                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       478285                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total       478285                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        79666                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4338                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      1880268                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data       735200                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total      2699472                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        79666                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4338                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      1880268                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data       735200                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      2699472                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.009628                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.024205                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.010380                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.496815                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.496815                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.919896                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.919896                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.171153                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.171153                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.034205                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.034205                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.212387                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.212387                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.008951                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.025071                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.034205                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.197957                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.078003                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.008951                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.025071                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.034205                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.197957                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.078003                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34293.914246                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24399.122807                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32946.236559                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18437.542638                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18437.542638                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20242.359867                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20242.359867                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       385999                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       385999                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48866.023301                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48866.023301                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 44701.215432                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 44701.215432                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 28761.225638                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 28761.225638                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34293.914246                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24399.122807                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 44701.215432                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34844.273142                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 37845.930706                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34293.914246                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24399.122807                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 44701.215432                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34844.273142                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 37845.930706                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs           68                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.171652                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.171652                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.034040                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.034040                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.211209                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.211209                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.009628                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.024205                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.034040                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.197386                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.077791                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.009628                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.024205                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.034040                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.197386                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.077791                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34127.118644                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24361.904762                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32951.261468                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18495.169342                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18495.169342                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20227.475171                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20227.475171                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       417500                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       417500                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50031.315193                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50031.315193                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 44655.620655                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 44655.620655                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 28781.726989                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 28781.726989                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34127.118644                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24361.904762                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 44655.620655                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35239.277671                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 38099.811886                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34127.118644                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24361.904762                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 44655.620655                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35239.277671                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 38099.811886                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs           60                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           34                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           30                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       196466                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          196466                       # number of writebacks
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         2877                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         2877                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           67                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           67                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          395                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          395                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           67                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         3272                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         3339                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           67                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         3272                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         3339                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          723                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          114                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total          837                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks         9399                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::total         9399                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       235023                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       235023                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        27851                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        27851                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19535                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19535                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.writebacks::writebacks       195910                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          195910                       # number of writebacks
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         2609                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         2609                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           70                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           70                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          363                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          363                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           70                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         2972                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total         3042                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           70                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         2972                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total         3042                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          767                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          105                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total          872                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks         9288                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::total         9288                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       233934                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       233934                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        27843                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        27843                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19534                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19534                       # number of SCUpgradeReq MSHR misses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeFailReq MSHR misses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41112                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        41112                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        64190                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        64190                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       101002                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       101002                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          723                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          114                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        64190                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data       142114                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total       207141                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          723                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          114                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        64190                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data       142114                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       235023                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total       442164                       # number of overall MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41491                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total        41491                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        63935                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        63935                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       100655                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       100655                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          767                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          105                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        63935                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data       142146                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total       206953                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          767                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          105                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        63935                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data       142146                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       233934                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total       440887                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3426                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        18002                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        21428                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        16758                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        16758                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        18001                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        21427                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        16756                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        16756                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3426                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        34760                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        38186                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     20456500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2097500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     22554000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  14138051507                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  14138051507                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    556929500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    556929500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    298503500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    298503500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       325999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       325999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1579585500                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1579585500                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2485678500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2485678500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2287922496                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2287922496                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     20456500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2097500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2485678500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   3867507996                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total   6375740496                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     20456500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2097500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2485678500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   3867507996                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  14138051507                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  20513792003                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        34757                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        38183                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     21573500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1928000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     23501500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  13851204796                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  13851204796                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    554776500                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    554776500                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    298118500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    298118500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       351500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       351500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1669946000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1669946000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2472260000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2472260000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2283319997                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2283319997                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     21573500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1928000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2472260000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   3953265997                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total   6449027497                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     21573500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1928000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2472260000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   3953265997                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  13851204796                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  20300232293                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    286870500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3607450000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   3894320500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   2599707500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2599707500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3607256500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   3894127000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   2599622000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2599622000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    286870500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   6207157500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   6494028000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.008951                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.025071                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.009810                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   6206878500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   6493749000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.009628                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.024205                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.010380                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.496435                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.496435                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.916792                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.916792                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.496815                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.496815                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.919896                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.919896                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.159959                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.159959                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.034169                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.034169                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.211559                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.211559                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.008951                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.025071                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.034169                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.193502                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.076766                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.008951                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.025071                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.034169                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.193502                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.161497                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.161497                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.034003                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.034003                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.210450                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.210450                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.009628                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.024205                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.034003                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.193343                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.076664                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.009628                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.024205                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.034003                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.193343                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.163865                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28293.914246                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18399.122807                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26946.236559                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60156.033695                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60156.033695                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19996.750566                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19996.750566                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15280.445354                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15280.445354                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       325999                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       325999                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38421.519264                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38421.519264                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38723.765384                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38723.765384                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22652.249421                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22652.249421                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28293.914246                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18399.122807                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38723.765384                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27214.123844                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30779.712833                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28293.914246                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18399.122807                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38723.765384                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27214.123844                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60156.033695                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46394.080031                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.163323                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28127.118644                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18361.904762                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26951.261468                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59209.883112                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59209.883112                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19925.169702                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19925.169702                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15261.518378                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15261.518378                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       351500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       351500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40248.391217                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40248.391217                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38668.335028                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38668.335028                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22684.615737                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22684.615737                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28127.118644                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18361.904762                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38668.335028                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27811.306664                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31161.797592                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28127.118644                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18361.904762                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38668.335028                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27811.306664                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59209.883112                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46044.070914                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200391.623153                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181739.803061                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155132.324860                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155132.324860                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200392.006000                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181739.254212                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155145.738840                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155145.738840                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 178571.849827                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 170063.059760                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 178579.235837                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 170069.114527                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq        136409                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      2524037                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        31171                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        16758                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback       866064                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict      2177189                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       293784                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        92828                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43742                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       114509                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           10                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           19                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       285377                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       271332                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1878593                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq       603707                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadReq        136175                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      2526619                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        31161                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        16756                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback       865136                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      2178805                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       280675                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        92865                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43660                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       114593                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           14                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           24                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       285252                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       271172                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1880268                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       604912                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      5608538                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2465365                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        11948                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       171096                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          8256947                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    120449152                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     82718835                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        18188                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       323084                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         203509259                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    1215113                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      6486372                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       1.185022                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.388316                       # Request fanout histogram
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      5613549                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2467613                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        11765                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       169746                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          8262673                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    120556352                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     82765674                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        17352                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       318664                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         203658042                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    1202366                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      6476462                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       1.183069                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.386723                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1           5286248     81.50%     81.50% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2           1200124     18.50%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1           5290820     81.69%     81.69% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2           1185642     18.31%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       6486372                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    3193659992                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       6476462                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    3195593995                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    113350499                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    113765999                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   2823287977                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   2825774529                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1167322846                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1168364927                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy      7403495                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy      7430992                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     90327994                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     90084491                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups               20515510                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          7101066                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           968769                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            10637682                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                7757881                       # Number of BTB hits
+system.cpu1.branchPred.lookups               20439224                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          7037667                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           906738                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            10483361                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                7695105                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            72.928303                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                8827818                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            689615                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            73.403034                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                8822837                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            629691                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1292,60 +1290,58 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    30617                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               30617                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        22895                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         7722                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples        30617                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0          30617    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        30617                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         2694                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 10773.014105                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean  9833.978032                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  6170.794386                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191          858     31.85%     31.85% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383         1697     62.99%     94.84% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575           63      2.34%     97.18% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-32767           63      2.34%     99.52% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::40960-49151            7      0.26%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-57343            1      0.04%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::90112-98303            4      0.15%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::106496-114687            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         2694                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   1565807264                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     1565807264    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   1565807264                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         2001     74.28%     74.28% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          693     25.72%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         2694                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        30617                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks                    30282                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               30282                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        22625                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         7657                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples        30282                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0          30282    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        30282                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         2657                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 10518.253670                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean  9441.717442                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  7245.373074                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-16383         2512     94.54%     94.54% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-32767          130      4.89%     99.44% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-49151            7      0.26%     99.70% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::81920-98303            5      0.19%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-114687            2      0.08%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::147456-163839            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         2657                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples   1594102264                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     1594102264    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total   1594102264                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         1972     74.22%     74.22% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          685     25.78%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         2657                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        30282                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        30617                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2694                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        30282                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2657                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2694                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        33311                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2657                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        32939                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    12131046                       # DTB read hits
-system.cpu1.dtb.read_misses                     27925                       # DTB read misses
-system.cpu1.dtb.write_hits                    7724726                       # DTB write hits
-system.cpu1.dtb.write_misses                     2692                       # DTB write misses
+system.cpu1.dtb.read_hits                    12124185                       # DTB read hits
+system.cpu1.dtb.read_misses                     27903                       # DTB read misses
+system.cpu1.dtb.write_hits                    7716793                       # DTB write hits
+system.cpu1.dtb.write_misses                     2379                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    2067                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      318                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   531                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    2053                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      374                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   549                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      287                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                12158971                       # DTB read accesses
-system.cpu1.dtb.write_accesses                7727418                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      291                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                12152088                       # DTB read accesses
+system.cpu1.dtb.write_accesses                7719172                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         19855772                       # DTB hits
-system.cpu1.dtb.misses                          30617                       # DTB misses
-system.cpu1.dtb.accesses                     19886389                       # DTB accesses
+system.cpu1.dtb.hits                         19840978                       # DTB hits
+system.cpu1.dtb.misses                          30282                       # DTB misses
+system.cpu1.dtb.accesses                     19871260                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1375,39 +1371,41 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     2297                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                2297                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walks                     2290                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                2290                       # Table walker walks initiated with short descriptors
 system.cpu1.itb.walker.walksShortTerminationLevel::Level1          182                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2115                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples         2297                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0           2297    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         2297                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         1122                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 10860.516934                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 10080.267537                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  5206.907244                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-8191          274     24.42%     24.42% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-16383          814     72.55%     96.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-24575            4      0.36%     97.33% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-32767           27      2.41%     99.73% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-49151            2      0.18%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::90112-98303            1      0.09%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         1122                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples   1565238764                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     1565238764    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total   1565238764                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K          953     84.94%     84.94% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          169     15.06%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total         1122                       # Table walker page sizes translated
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2108                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples         2290                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0           2290    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         2290                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         1123                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 10627.337489                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean  9754.511529                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  5025.096618                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191          329     29.30%     29.30% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287          526     46.84%     76.14% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383          229     20.39%     96.53% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575            2      0.18%     96.71% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671           14      1.25%     97.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767           21      1.87%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-45055            1      0.09%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::45056-49151            1      0.09%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         1123                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples   1593536764                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     1593536764    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total   1593536764                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K          954     84.95%     84.95% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          169     15.05%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         1123                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2297                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2297                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2290                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2290                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1122                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1122                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         3419                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    41950603                       # ITB inst hits
-system.cpu1.itb.inst_misses                      2297                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1123                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1123                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         3413                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    41919801                       # ITB inst hits
+system.cpu1.itb.inst_misses                      2290                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1416,130 +1414,130 @@ system.cpu1.itb.flush_tlb                          66                       # Nu
 system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1160                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1161                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1848                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1868                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                41952900                       # ITB inst accesses
-system.cpu1.itb.hits                         41950603                       # DTB hits
-system.cpu1.itb.misses                           2297                       # DTB misses
-system.cpu1.itb.accesses                     41952900                       # DTB accesses
-system.cpu1.numCycles                       125141481                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                41922091                       # ITB inst accesses
+system.cpu1.itb.hits                         41919801                       # DTB hits
+system.cpu1.itb.misses                           2290                       # DTB misses
+system.cpu1.itb.accesses                     41922091                       # DTB accesses
+system.cpu1.numCycles                       125017818                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   51908432                       # Number of instructions committed
-system.cpu1.committedOps                     63413187                       # Number of ops (including micro ops) committed
-system.cpu1.discardedOps                      5363692                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends                     2715                       # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles                  5566331294                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi                              2.410812                       # CPI: cycles per instruction
-system.cpu1.ipc                              0.414798                       # IPC: instructions per cycle
+system.cpu1.committedInsts                   51886096                       # Number of instructions committed
+system.cpu1.committedOps                     63386159                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                      5353179                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                     2738                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                  5566469050                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              2.409467                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.415030                       # IPC: instructions per cycle
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2717                       # number of quiesce instructions executed
-system.cpu1.tickCycles                      105428618                       # Number of cycles that the object actually ticked
-system.cpu1.idleCycles                       19712863                       # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements           231919                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          484.812111                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           19337078                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           232252                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            83.259038                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      90437090000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   484.812111                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.946899                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.946899                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          333                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          279                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3           54                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.650391                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         39720944                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        39720944                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     11670097                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       11670097                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      7386354                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       7386354                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        66295                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        66295                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        88787                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        88787                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        80732                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        80732                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     19056451                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        19056451                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     19122746                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       19122746                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       184750                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       184750                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       167503                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       167503                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        35001                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        35001                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17741                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        17741                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23478                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23478                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       352253                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        352253                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       387254                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       387254                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2719987000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   2719987000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   4150031500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   4150031500                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    326839500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    326839500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    548823500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    548823500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       416500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total       416500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   6870018500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   6870018500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   6870018500                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   6870018500                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     11854847                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     11854847                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      7553857                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      7553857                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       101296                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       101296                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       106528                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total       106528                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       104210                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total       104210                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     19408704                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     19408704                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     19510000                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     19510000                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.015584                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.015584                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.022174                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.022174                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.345532                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.345532                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.166538                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.166538                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.225295                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.225295                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.018149                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.018149                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.019849                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.019849                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14722.527740                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14722.527740                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24775.863716                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 24775.863716                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18422.834113                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18422.834113                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23376.075475                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23376.075475                       # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce                    2740                       # number of quiesce instructions executed
+system.cpu1.tickCycles                      105304281                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                       19713537                       # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements           231375                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          483.037999                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs           19321104                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           231701                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            83.388091                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      90467560500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   483.037999                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.943434                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.943434                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          326                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          253                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           73                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.636719                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         39693132                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        39693132                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     11664966                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       11664966                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      7379255                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       7379255                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        66113                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        66113                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        88582                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        88582                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        80498                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        80498                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     19044221                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        19044221                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     19110334                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       19110334                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       184342                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       184342                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       167268                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       167268                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        34982                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        34982                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17676                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        17676                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23450                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23450                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       351610                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        351610                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       386592                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       386592                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2719374500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2719374500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   4153510500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   4153510500                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    325753000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    325753000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    548137000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    548137000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       684500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total       684500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   6872885000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   6872885000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   6872885000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   6872885000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     11849308                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     11849308                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      7546523                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      7546523                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       101095                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       101095                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       106258                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total       106258                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       103948                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total       103948                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     19395831                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     19395831                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     19496926                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     19496926                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.015557                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.015557                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.022165                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.022165                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.346031                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.346031                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.166350                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.166350                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.225594                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.225594                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.018128                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.018128                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.019828                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.019828                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14751.790151                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14751.790151                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24831.471052                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 24831.471052                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18429.112921                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18429.112921                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23374.712154                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23374.712154                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19503.080172                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 19503.080172                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17740.342256                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 17740.342256                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19546.898552                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 19546.898552                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17778.135605                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 17778.135605                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1548,148 +1546,148 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       138789                       # number of writebacks
-system.cpu1.dcache.writebacks::total           138789                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        18309                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        18309                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        62144                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total        62144                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12262                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12262                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data        80453                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total        80453                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data        80453                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total        80453                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       166441                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       166441                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       105359                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       105359                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        33489                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        33489                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5479                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5479                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23478                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23478                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       271800                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       271800                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       305289                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       305289                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        17142                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        17142                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        14413                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        14413                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        31555                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        31555                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2292018500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2292018500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2517101000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2517101000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    540422500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    540422500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     93861500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     93861500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    525354500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    525354500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       407500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       407500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4809119500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   4809119500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5349542000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   5349542000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2935336500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2935336500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2447202500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   2447202500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   5382539000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   5382539000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.014040                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.014040                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.013948                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.013948                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.330605                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.330605                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.051432                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.051432                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.225295                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.225295                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.014004                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.014004                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.015648                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.015648                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13770.756604                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13770.756604                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23890.707011                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23890.707011                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16137.313745                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16137.313745                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17131.137069                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17131.137069                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22376.458813                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22376.458813                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       138377                       # number of writebacks
+system.cpu1.dcache.writebacks::total           138377                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        18221                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        18221                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        62038                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total        62038                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12225                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12225                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data        80259                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total        80259                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data        80259                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total        80259                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       166121                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       166121                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       105230                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       105230                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        33463                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        33463                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5451                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5451                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23450                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23450                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       271351                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       271351                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       304814                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       304814                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        17128                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total        17128                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        14405                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total        14405                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        31533                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        31533                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2295109000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2295109000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2517034000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2517034000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    544638000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    544638000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     92810500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     92810500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    524700000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    524700000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       671500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       671500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4812143000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4812143000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5356781000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   5356781000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2934873000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2934873000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2446602500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   2446602500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   5381475500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   5381475500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.014019                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.014019                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.013944                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.013944                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.331005                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.331005                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.051300                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.051300                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.225594                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.225594                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.013990                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.013990                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.015634                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.015634                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13815.887215                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13815.887215                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23919.357598                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23919.357598                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16275.827033                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16275.827033                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17026.325445                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17026.325445                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22375.266525                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22375.266525                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17693.596394                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17693.596394                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17522.878322                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17522.878322                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171236.524326                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171236.524326                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169791.334212                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169791.334212                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170576.422120                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170576.422120                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17734.016090                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17734.016090                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17573.933612                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17573.933612                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171349.427837                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171349.427837                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169843.977785                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169843.977785                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170661.703612                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170661.703612                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          1046573                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          499.334165                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           40901496                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          1047085                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            39.062250                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      72079197500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.334165                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975262                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.975262                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements          1042125                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          499.329120                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           40875126                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          1042637                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            39.203602                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      72106351500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.329120                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975252                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.975252                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::2          461                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::3           51                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         84944247                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        84944247                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     40901496                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       40901496                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     40901496                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        40901496                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     40901496                       # number of overall hits
-system.cpu1.icache.overall_hits::total       40901496                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      1047085                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      1047085                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      1047085                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       1047085                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      1047085                       # number of overall misses
-system.cpu1.icache.overall_misses::total      1047085                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   9273780500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   9273780500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   9273780500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   9273780500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   9273780500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   9273780500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     41948581                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     41948581                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     41948581                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     41948581                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     41948581                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     41948581                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024961                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.024961                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024961                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.024961                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024961                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.024961                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8856.759957                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  8856.759957                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8856.759957                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  8856.759957                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8856.759957                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  8856.759957                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         84878163                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        84878163                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     40875126                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       40875126                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     40875126                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        40875126                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     40875126                       # number of overall hits
+system.cpu1.icache.overall_hits::total       40875126                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      1042637                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      1042637                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      1042637                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       1042637                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      1042637                       # number of overall misses
+system.cpu1.icache.overall_misses::total      1042637                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   9237616500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   9237616500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   9237616500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   9237616500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   9237616500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   9237616500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     41917763                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     41917763                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     41917763                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     41917763                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     41917763                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     41917763                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024873                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.024873                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024873                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.024873                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024873                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.024873                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8859.858704                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  8859.858704                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8859.858704                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  8859.858704                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8859.858704                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  8859.858704                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1698,443 +1696,453 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      1047085                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      1047085                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      1047085                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      1047085                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      1047085                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      1047085                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      1042637                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      1042637                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      1042637                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      1042637                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      1042637                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      1042637                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          113                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          113                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          113                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          113                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   8750238000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   8750238000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   8750238000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   8750238000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   8750238000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   8750238000                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10154500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10154500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10154500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total     10154500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024961                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024961                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024961                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.024961                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024961                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.024961                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8356.759957                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8356.759957                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8356.759957                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  8356.759957                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8356.759957                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  8356.759957                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89862.831858                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89862.831858                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89862.831858                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89862.831858                       # average overall mshr uncacheable latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   8716298000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   8716298000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   8716298000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   8716298000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   8716298000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   8716298000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10126000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10126000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10126000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total     10126000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024873                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024873                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024873                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.024873                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024873                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.024873                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8359.858704                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8359.858704                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8359.858704                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8359.858704                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8359.858704                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8359.858704                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89610.619469                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89610.619469                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89610.619469                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89610.619469                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued       270311                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified       270335                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit           21                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       270674                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       270706                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit           28                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage        70297                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements           69395                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15632.228782                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs           2434679                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           84293                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           28.883525                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage        70190                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements           69559                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15624.003278                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           2421583                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           84278                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           28.733276                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  6105.214353                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    60.591846                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.935526                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  5648.623425                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2320.323151                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1496.540481                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.372633                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003698                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000057                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.344765                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.141621                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.091342                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.954116                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1218                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           62                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13618                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            8                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          684                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          526                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_blocks::writebacks  6091.947681                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    59.671167                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.103493                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  5612.930096                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2321.677903                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1537.672938                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.371823                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003642                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000006                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.342586                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.141704                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.093852                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.953613                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1225                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           50                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13444                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            6                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          697                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          522                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           13                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           21                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           28                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          315                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         6069                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         7234                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.074341                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003784                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.831177                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        43042452                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       43042452                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        33942                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2703                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total         36645                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks       138788                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total       138788                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         2017                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total         2017                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data         1035                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total         1035                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        37928                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        37928                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      1019439                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      1019439                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data       131721                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total       131721                       # number of ReadSharedReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        33942                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2703                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      1019439                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data       169649                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        1225733                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        33942                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2703                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      1019439                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data       169649                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       1225733                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          703                       # number of ReadReq misses
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           17                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           20                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          327                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5775                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         7342                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.074768                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003052                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.820557                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        42869923                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       42869923                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        33040                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2583                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total         35623                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks       138377                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total       138377                       # number of Writeback hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         2042                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total         2042                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data         1012                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total         1012                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data        37732                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total        37732                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      1015029                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      1015029                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data       131048                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total       131048                       # number of ReadSharedReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        33040                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2583                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      1015029                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data       168780                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total        1219432                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        33040                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2583                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      1015029                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data       168780                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total       1219432                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          727                       # number of ReadReq misses
 system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          221                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total          924                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29293                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        29293                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22443                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        22443                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        36124                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total        36124                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        27646                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total        27646                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        73685                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total        73685                       # number of ReadSharedReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          703                       # number of demand (read+write) misses
+system.cpu1.l2cache.ReadReq_misses::total          948                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29373                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total        29373                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22436                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total        22436                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            2                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data        36088                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total        36088                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        27608                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total        27608                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        73984                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total        73984                       # number of ReadSharedReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          727                       # number of demand (read+write) misses
 system.cpu1.l2cache.demand_misses::cpu1.itb.walker          221                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst        27646                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data       109809                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total       138379                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          703                       # number of overall misses
+system.cpu1.l2cache.demand_misses::cpu1.inst        27608                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data       110072                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total       138628                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          727                       # number of overall misses
 system.cpu1.l2cache.overall_misses::cpu1.itb.walker          221                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst        27646                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data       109809                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total       138379                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     17833500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4520500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total     22354000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    553092500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total    553092500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    450276000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    450276000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       393500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       393500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1418705500                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   1418705500                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst   1071948000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total   1071948000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1752324498                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1752324498                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     17833500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4520500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst   1071948000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data   3171029998                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total   4265331998                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     17833500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4520500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst   1071948000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data   3171029998                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total   4265331998                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        34645                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2924                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total        37569                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks       138788                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total       138788                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        31310                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        31310                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23478                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        23478                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        74052                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total        74052                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      1047085                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total      1047085                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       205406                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total       205406                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        34645                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2924                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      1047085                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data       279458                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total      1364112                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        34645                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2924                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      1047085                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data       279458                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total      1364112                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.020292                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.075581                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.024595                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.935580                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.935580                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.955916                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.955916                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.487819                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.487819                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.026403                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.026403                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.358729                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.358729                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.020292                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.075581                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.026403                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.392936                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.101443                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.020292                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.075581                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.026403                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.392936                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.101443                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25367.709815                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20454.751131                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24192.640693                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18881.388045                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18881.388045                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20063.093169                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20063.093169                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39273.211715                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39273.211715                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38774.072199                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38774.072199                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23781.291959                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23781.291959                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25367.709815                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20454.751131                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38774.072199                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28877.687603                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 30823.549802                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25367.709815                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20454.751131                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38774.072199                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28877.687603                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 30823.549802                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs           26                       # number of cycles access was blocked
+system.cpu1.l2cache.overall_misses::cpu1.inst        27608                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data       110072                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total       138628                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     18603000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4457500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total     23060500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    554124000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total    554124000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    449909000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    449909000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       652000                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       652000                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1418232500                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total   1418232500                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst   1071283000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total   1071283000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1763586495                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1763586495                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     18603000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4457500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst   1071283000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data   3181818995                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total   4276162495                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     18603000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4457500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst   1071283000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data   3181818995                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total   4276162495                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        33767                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2804                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total        36571                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks       138377                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total       138377                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        31415                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total        31415                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23448                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total        23448                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        73820                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total        73820                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      1042637                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total      1042637                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       205032                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total       205032                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        33767                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2804                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst      1042637                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data       278852                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total      1358060                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        33767                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2804                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      1042637                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data       278852                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total      1358060                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.021530                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.078816                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.025922                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.934999                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.934999                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.956841                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.956841                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.488865                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.488865                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.026479                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.026479                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.360841                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.360841                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.021530                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.078816                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.026479                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.394733                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.102078                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.021530                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.078816                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.026479                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.394733                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.102078                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25588.720770                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20169.683258                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24325.421941                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18865.080176                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18865.080176                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20052.995186                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20052.995186                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       326000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       326000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39299.282310                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39299.282310                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38803.354100                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38803.354100                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23837.403966                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23837.403966                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25588.720770                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20169.683258                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38803.354100                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28906.706474                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 30846.311676                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25588.720770                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20169.683258                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38803.354100                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28906.706474                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 30846.311676                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           26                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        36782                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           36782                       # number of writebacks
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          330                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total          330                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst           21                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total           21                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          131                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          131                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst           21                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data          461                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total          482                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst           21                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data          461                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total          482                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          703                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.writebacks::writebacks        36799                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           36799                       # number of writebacks
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          302                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total          302                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst           26                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total           26                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          134                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          134                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst           26                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data          436                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total          462                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst           26                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data          436                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total          462                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          727                       # number of ReadReq MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          221                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total          924                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks         3084                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::total         3084                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        35155                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total        35155                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29293                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29293                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22443                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22443                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        35794                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        35794                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        27625                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        27625                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        73554                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        73554                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          703                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total          948                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks         3205                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::total         3205                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        35196                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total        35196                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29373                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29373                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22436                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22436                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        35786                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total        35786                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        27582                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        27582                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        73850                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        73850                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          727                       # number of demand (read+write) MSHR misses
 system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          221                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        27625                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data       109348                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total       137897                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          703                       # number of overall MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        27582                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data       109636                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total       138166                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          727                       # number of overall MSHR misses
 system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          221                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        27625                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data       109348                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        35155                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total       173052                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        27582                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data       109636                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        35196                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total       173362                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          113                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        17142                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        17255                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        14413                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        14413                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        17128                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        17241                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        14405                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        14405                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          113                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        31555                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        31668                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     13615500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3194500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     16810000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1287870547                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1287870547                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    501412999                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    501412999                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    348285500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    348285500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       339500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       339500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1165172000                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1165172000                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    905573000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    905573000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1306537498                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1306537498                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     13615500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3194500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    905573000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2471709498                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   3394092498                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     13615500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3194500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    905573000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2471709498                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1287870547                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   4681963045                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9250500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2798164000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2807414500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   2338978500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   2338978500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9250500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   5137142500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   5146393000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.020292                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.075581                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.024595                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        31533                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        31646                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     14241000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3131500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     17372500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1238467331                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1238467331                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    502709499                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    502709499                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    348029000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    348029000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       574000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       574000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1167759000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1167759000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    904893000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    904893000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1316095995                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1316095995                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     14241000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3131500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    904893000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2483854995                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   3406120495                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     14241000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3131500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    904893000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2483854995                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1238467331                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   4644587826                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9222000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2797805500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2807027500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   2338455000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   2338455000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9222000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   5136260500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   5145482500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.021530                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.078816                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.025922                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.935580                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.935580                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.955916                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.955916                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.483363                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.483363                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.026383                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.026383                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.358091                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.358091                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.020292                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.075581                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.026383                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.391286                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.101089                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.020292                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.075581                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.026383                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.391286                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.934999                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.934999                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.956841                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.956841                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.484774                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.484774                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.026454                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.026454                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.360188                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.360188                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.021530                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.078816                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.026454                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.393169                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.101738                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.021530                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.078816                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.026454                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.393169                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.126861                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19367.709815                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14454.751131                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18192.640693                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36634.064770                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36634.064770                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17117.161062                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17117.161062                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15518.669518                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15518.669518                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32552.159580                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32552.159580                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32780.923077                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32780.923077                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17762.970036                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17762.970036                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19367.709815                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14454.751131                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32780.923077                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22604.066814                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24613.243928                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19367.709815                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14454.751131                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32780.923077                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22604.066814                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36634.064770                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27055.237992                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81862.831858                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163234.395053                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162701.506810                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162282.557413                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162282.557413                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81862.831858                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162799.635557                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162510.831123                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.127654                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19588.720770                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14169.683258                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18325.421941                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35187.729600                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35187.729600                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17114.680114                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17114.680114                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15512.078802                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15512.078802                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       287000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       287000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32631.727491                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32631.727491                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32807.374375                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32807.374375                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17821.205078                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17821.205078                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19588.720770                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14169.683258                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32807.374375                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22655.468961                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24652.378262                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19588.720770                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14169.683258                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32807.374375                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22655.468961                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35187.729600                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26791.268133                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81610.619469                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163346.888136                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162811.176846                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162336.341548                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162336.341548                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81610.619469                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162885.247201                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162595.035708                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq         81434                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp      1353329                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        31171                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        14413                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback       511562                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict      1270278                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq        44724                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        77037                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        43004                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        89317                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           10                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           19                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        97290                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        79982                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      1047085                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq       561570                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadReq         81005                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp      1348099                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        31161                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        14405                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback       510462                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict      1265020                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        43516                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        77320                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        42972                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        89288                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           13                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           24                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        97251                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        79776                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      1042637                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       559861                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      3121460                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side      1041902                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7336                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        72984                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          4243682                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     67020672                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29874703                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        11696                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       138580                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          97045651                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    1176077                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      3823827                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       1.296126                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.456547                       # Request fanout histogram
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      3108261                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side      1040223                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7202                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        71706                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          4227392                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     66736000                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29812791                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        11216                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       135068                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          96695075                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    1172897                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      3809713                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       1.296141                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.456554                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1           2691491     70.39%     70.39% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2           1132336     29.61%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1           2681500     70.39%     70.39% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2           1128213     29.61%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       3823827                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy    1513117496                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       3809713                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy    1507501992                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     87426499                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     87443999                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   1570862868                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   1564193862                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    471839695                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    470956198                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      4412000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy      4398499                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy     38355467                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy     37948980                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                31014                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               31014                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                31013                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               31013                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59422                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              59422                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56602                       # Packet count per connected master and slave (bytes)
@@ -2142,7 +2150,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          846                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          844                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2158,16 +2166,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       107912                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       107910                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72960                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total        72960                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  180872                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  180870                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71546                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          447                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          446                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2183,10 +2191,10 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       162794                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       162793                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321280                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321280                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2484074                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2484073                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy             40091000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
@@ -2197,7 +2205,7 @@ system.iobus.reqLayer3.occupancy                12000                       # La
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy               504000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy               503000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
@@ -2227,23 +2235,23 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           187550442                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           187545199                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            84714000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            84712000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36784000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                36446                       # number of replacements
-system.iocache.tags.tagsinuse               14.479147                       # Cycle average of tags in use
+system.iocache.tags.replacements                36462                       # number of replacements
+system.iocache.tags.tagsinuse               14.479963                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36462                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                36478                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         270355599000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.479147                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.904947                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.904947                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         270370198000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.479963                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.904998                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.904998                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -2257,14 +2265,14 @@ system.iocache.demand_misses::realview.ide          256                       #
 system.iocache.demand_misses::total               256                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          256                       # number of overall misses
 system.iocache.overall_misses::total              256                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     32686877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     32686877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4278417565                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4278417565                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     32686877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     32686877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     32686877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     32686877                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     32688877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     32688877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4277206322                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4277206322                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     32688877                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     32688877                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     32688877                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     32688877                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          256                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            256                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -2281,24 +2289,24 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 127683.113281                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 127683.113281                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118110.025536                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118110.025536                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 127683.113281                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 127683.113281                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 127683.113281                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 127683.113281                       # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 127690.925781                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 127690.925781                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118076.587953                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118076.587953                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 127690.925781                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 127690.925781                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 127690.925781                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 127690.925781                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs            21                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    4                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     5.250000                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    10.500000                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           36190                       # number of writebacks
-system.iocache.writebacks::total                36190                       # number of writebacks
+system.iocache.writebacks::writebacks           36206                       # number of writebacks
+system.iocache.writebacks::total                36206                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          256                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          256                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
@@ -2307,14 +2315,14 @@ system.iocache.demand_mshr_misses::realview.ide          256
 system.iocache.demand_mshr_misses::total          256                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          256                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          256                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     19886877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     19886877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2467217565                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2467217565                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     19886877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     19886877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     19886877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     19886877                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     19888877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     19888877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2466006322                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2466006322                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     19888877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     19888877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     19888877                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     19888877                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -2323,602 +2331,576 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 77683.113281                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 77683.113281                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68110.025536                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68110.025536                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 77683.113281                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 77683.113281                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 77683.113281                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 77683.113281                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 77690.925781                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 77690.925781                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68076.587953                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68076.587953                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 77690.925781                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 77690.925781                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 77690.925781                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 77690.925781                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   135320                       # number of replacements
-system.l2c.tags.tagsinuse                64080.552826                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     445963                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   199765                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.232438                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   134724                       # number of replacements
+system.l2c.tags.tagsinuse                64068.233504                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     443602                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   199053                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.228562                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   12788.353662                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    69.367527                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.034390                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     7205.553479                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2096.784928                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32107.700654                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    26.808299                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker     0.851993                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     4024.713832                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1527.951308                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  4232.432754                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.195135                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001058                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.109948                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.031994                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.489925                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000409                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.000013                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.061412                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.023315                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.064582                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.977792                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        29238                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023           72                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        35135                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          119                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         5585                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        23534                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           72                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           15                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          319                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         3030                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        31767                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.446136                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.001099                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.536118                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  5845545                       # Number of tag accesses
-system.l2c.tags.data_accesses                 5845545                       # Number of data accesses
-system.l2c.Writeback_hits::writebacks          233248                       # number of Writeback hits
-system.l2c.Writeback_hits::total               233248                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            3007                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             942                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                3949                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           254                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            81                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               335                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data             4095                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data             2177                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                 6272                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          343                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker           65                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst        44646                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data        47683                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        46675                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker          154                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker           31                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst        21738                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data        11221                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         8044                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           180600                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker           343                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker            65                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst               44646                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data               51778                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher        46675                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker           154                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker            31                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst               21738                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               13398                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher         8044                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  186872                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker          343                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker           65                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst              44646                       # number of overall hits
-system.l2c.overall_hits::cpu0.data              51778                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher        46675                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker          154                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker           31                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst              21738                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              13398                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher         8044                       # number of overall hits
-system.l2c.overall_hits::total                 186872                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data          8773                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          4095                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             12868                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          811                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         1218                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            2029                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          10812                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data           8416                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total              19228                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker          116                       # number of ReadSharedReq misses
+system.l2c.tags.occ_blocks::writebacks   12835.902941                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    68.531822                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.025215                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     7257.127456                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2101.817094                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32009.024605                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    30.126345                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     4045.876721                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     1535.093827                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  4184.707478                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.195860                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001046                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.110735                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.032071                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.488419                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000460                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.061735                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.023424                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.063854                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.977604                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        29296                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023           67                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        34966                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          113                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3         5383                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4        23800                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4           66                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          313                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         2923                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        31711                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.447021                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.001022                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.533539                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  5827626                       # Number of tag accesses
+system.l2c.tags.data_accesses                 5827626                       # Number of data accesses
+system.l2c.Writeback_hits::writebacks          232709                       # number of Writeback hits
+system.l2c.Writeback_hits::total               232709                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data            3025                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             939                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                3964                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data           257                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            83                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total               340                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data             4055                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data             2183                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total                 6238                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          387                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker           52                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst        44381                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data        47292                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        46189                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker          171                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker           33                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst        21681                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data        11241                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         8230                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total           179657                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker           387                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker            52                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst               44381                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data               51347                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher        46189                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker           171                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker            33                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst               21681                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data               13424                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher         8230                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                  185895                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker          387                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker           52                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst              44381                       # number of overall hits
+system.l2c.overall_hits::cpu0.data              51347                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher        46189                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker          171                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker           33                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst              21681                       # number of overall hits
+system.l2c.overall_hits::cpu1.data              13424                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher         8230                       # number of overall hits
+system.l2c.overall_hits::total                 185895                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data          8753                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          4074                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             12827                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          797                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data         1213                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            2010                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          10969                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data           8454                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total              19423                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker          121                       # number of ReadSharedReq misses
 system.l2c.ReadSharedReq_misses::cpu0.itb.walker            1                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        19540                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data         8519                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       129160                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker           40                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker            1                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst         5871                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data         2660                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         9190                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         175098                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.dtb.walker          116                       # number of demand (read+write) misses
+system.l2c.ReadSharedReq_misses::cpu0.inst        19546                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data         8542                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       128715                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.dtb.walker           43                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.inst         5890                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data         2696                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         8977                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         174531                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.dtb.walker          121                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             19540                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             19331                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       129160                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker           40                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              5871                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             11076                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher         9190                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                194326                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker          116                       # number of overall misses
+system.l2c.demand_misses::cpu0.inst             19546                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             19511                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.l2cache.prefetcher       128715                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker           43                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              5890                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             11150                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.l2cache.prefetcher         8977                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                193954                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker          121                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            19540                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            19331                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       129160                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker           40                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             5871                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            11076                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher         9190                       # number of overall misses
-system.l2c.overall_misses::total               194326                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data      9401500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      5084500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     14486000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1177000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1665000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      2842000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data    989600500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data    687604500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   1677205000                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker     10015500                       # number of ReadSharedReq miss cycles
+system.l2c.overall_misses::cpu0.inst            19546                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            19511                       # number of overall misses
+system.l2c.overall_misses::cpu0.l2cache.prefetcher       128715                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker           43                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             5890                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            11150                       # number of overall misses
+system.l2c.overall_misses::cpu1.l2cache.prefetcher         8977                       # number of overall misses
+system.l2c.overall_misses::total               193954                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data      9167000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data      5104000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     14271000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1330000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1451500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      2781500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   1087997000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data    696148000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   1784145000                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker     10392000                       # number of ReadSharedReq miss cycles
 system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       303000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   1567254000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data    747042500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  13330410791                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker      3705500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker        82500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst    483609000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data    234711500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher   1119629067                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  17496763358                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker     10015500                       # number of demand (read+write) miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.inst   1558395000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data    749223000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  13067901493                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker      3962000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst    483846500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data    240245000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher   1069849511                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  17184117504                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker     10392000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu0.itb.walker       303000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   1567254000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   1736643000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  13330410791                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker      3705500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker        82500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    483609000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data    922316000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   1119629067                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     19173968358                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker     10015500                       # number of overall miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   1558395000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   1837220000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  13067901493                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker      3962000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    483846500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data    936393000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   1069849511                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     18968262504                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker     10392000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu0.itb.walker       303000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   1567254000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   1736643000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  13330410791                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker      3705500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker        82500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    483609000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data    922316000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   1119629067                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    19173968358                       # number of overall miss cycles
-system.l2c.Writeback_accesses::writebacks       233248                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           233248                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        11780                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         5037                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           16817                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data         1065                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data         1299                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          2364                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data        14907                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        10593                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total            25500                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          459                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           66                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst        64186                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data        56202                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       175835                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker          194                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           32                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst        27609                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data        13881                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        17234                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total       355698                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker          459                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker           66                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst           64186                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data           71109                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       175835                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker          194                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker           32                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst           27609                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data           24474                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher        17234                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              381198                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker          459                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker           66                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst          64186                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data          71109                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       175835                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker          194                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker           32                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst          27609                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          24474                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher        17234                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             381198                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.744737                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.812984                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.765178                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.761502                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.937644                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.858291                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.725297                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.794487                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.754039                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.252723                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.015152                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.304428                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.151578                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.734552                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.206186                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.031250                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.212648                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.191629                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.533248                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.492266                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.252723                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.015152                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.304428                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.271850                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.734552                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.206186                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.031250                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.212648                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.452562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.533248                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.509777                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.252723                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.015152                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.304428                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.271850                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.734552                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.206186                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.031250                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.212648                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.452562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.533248                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.509777                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1071.640260                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1241.636142                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  1125.738265                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1451.294698                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1366.995074                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  1400.689995                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91527.978172                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81702.055608                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 87227.220720                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 86340.517241                       # average ReadSharedReq miss latency
+system.l2c.overall_miss_latency::cpu0.inst   1558395000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   1837220000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  13067901493                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker      3962000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    483846500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data    936393000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   1069849511                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    18968262504                       # number of overall miss cycles
+system.l2c.Writeback_accesses::writebacks       232709                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           232709                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        11778                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         5013                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           16791                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data         1054                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data         1296                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          2350                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data        15024                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        10637                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            25661                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          508                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           53                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst        63927                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data        55834                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       174904                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker          214                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           33                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst        27571                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data        13937                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        17207                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       354188                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker          508                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker           53                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst           63927                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data           70858                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       174904                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker          214                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker           33                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst           27571                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           24574                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher        17207                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              379849                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker          508                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker           53                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst          63927                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data          70858                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       174904                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker          214                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker           33                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst          27571                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          24574                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher        17207                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             379849                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.743165                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.812687                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.763921                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.756167                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.935957                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.855319                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.730099                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.794773                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.756907                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.238189                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.018868                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.305755                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.152989                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.735918                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.200935                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.213630                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.193442                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.521706                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.492764                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.238189                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.018868                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.305755                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.275354                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.735918                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.200935                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.213630                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.453732                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.521706                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.510608                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.238189                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.018868                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.305755                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.275354                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.735918                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.200935                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.213630                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.453732                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.521706                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.510608                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1047.298069                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1252.822779                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  1112.575037                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1668.757842                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1196.619951                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  1383.830846                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 99188.348983                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82345.398628                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 91857.334088                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 85884.297521                       # average ReadSharedReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker       303000                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 80207.471853                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87691.337011                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 103208.507208                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 92637.500000                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker        82500                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82372.508942                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 88237.406015                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 121831.236888                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 99925.546597                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86340.517241                       # average overall miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 79729.612197                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87710.489347                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 101525.863287                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 92139.534884                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82147.113752                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89111.646884                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 119176.730645                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 98458.826822                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85884.297521                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker       303000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 80207.471853                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 89837.204490                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 103208.507208                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92637.500000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker        82500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 82372.508942                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 83271.578187                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 121831.236888                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 98669.083694                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86340.517241                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 79729.612197                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 94163.292502                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 101525.863287                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92139.534884                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 82147.113752                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 83981.434978                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 119176.730645                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 97797.738144                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 85884.297521                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker       303000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 80207.471853                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 89837.204490                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 103208.507208                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92637.500000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker        82500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 82372.508942                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 83271.578187                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 121831.236888                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 98669.083694                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                73                       # number of cycles access was blocked
+system.l2c.overall_avg_miss_latency::cpu0.inst 79729.612197                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 94163.292502                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 101525.863287                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92139.534884                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 82147.113752                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 83981.434978                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 119176.730645                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 97797.738144                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs               442                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        5                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        2                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     14.600000                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           221                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              103312                       # number of writebacks
-system.l2c.writebacks::total                   103312                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            2                       # number of ReadSharedReq MSHR hits
+system.l2c.writebacks::writebacks              103131                       # number of writebacks
+system.l2c.writebacks::total                   103131                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            5                       # number of ReadSharedReq MSHR hits
 system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            4                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total            6                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              2                       # number of demand (read+write) MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total            9                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              5                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                  6                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             2                       # number of overall MSHR hits
+system.l2c.demand_mshr_hits::total                  9                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst             5                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                 6                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks         3718                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total         3718                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         8773                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         4095                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        12868                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          811                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1218                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         2029                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        10812                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         8416                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         19228                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker          116                       # number of ReadSharedReq MSHR misses
+system.l2c.overall_mshr_hits::total                 9                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks         3812                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total         3812                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         8753                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         4074                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        12827                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          797                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1213                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         2010                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        10969                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data         8454                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         19423                       # number of ReadExReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker          121                       # number of ReadSharedReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        19538                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data         8519                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       129160                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker           40                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         5867                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data         2660                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         9190                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       175092                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker          116                       # number of demand (read+write) MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        19541                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data         8542                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       128715                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker           43                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         5886                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data         2696                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         8977                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total       174522                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker          121                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        19538                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        19331                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       129160                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker           40                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         5867                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        11076                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         9190                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           194320                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker          116                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        19541                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        19511                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       128715                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker           43                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         5886                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        11150                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         8977                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           193945                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker          121                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        19538                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        19331                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       129160                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker           40                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         5867                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        11076                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         9190                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          194320                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        19541                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        19511                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       128715                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker           43                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         5886                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        11150                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         8977                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          193945                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3426                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        18002                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data        18001                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          113                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data        17138                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        38679                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        16758                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data        14413                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        31171                       # number of WriteReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data        17124                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        38664                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        16756                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data        14405                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        31161                       # number of WriteReq MSHR uncacheable
 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3426                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        34760                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        34757                       # number of overall MSHR uncacheable misses
 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          113                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        31551                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        69850                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    182968000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     85020001                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    267988001                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     16936500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     25297000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     42233500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    881480500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    603444500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   1484925000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker      8855500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        31529                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        69825                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    181795500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     84589501                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    266385001                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     16646000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     25174500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     41820500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    978307000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    611608000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   1589915000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker      9182000                       # number of ReadSharedReq MSHR miss cycles
 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       293000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1371777500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    661852500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  12038810791                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker      3305500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker        72500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1362728000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    663803000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  11780751493                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker      3532000                       # number of ReadSharedReq MSHR miss cycles
 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    424750500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    208111500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1027729067                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  15745558358                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      8855500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    213285000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    980079511                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  15438404504                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      9182000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       293000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   1371777500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   1543333000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  12038810791                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      3305500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        72500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   1362728000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   1642110000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  11780751493                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      3532000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.inst    424750500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    811556000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher   1027729067                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  17230483358                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      8855500                       # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    824893000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    980079511                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  17028319504                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      9182000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       293000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   1371777500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   1543333000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  12038810791                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      3305500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        72500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   1362728000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   1642110000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  11780751493                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      3532000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.inst    424750500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    811556000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1027729067                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  17230483358                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    824893000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    980079511                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  17028319504                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    214924500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3283407500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6877000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2489619500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   5994828500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2314728500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2093956000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   4408684500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3283233500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6848500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2489515500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   5994522000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2314676500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2093562500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   4408239000                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    214924500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5598136000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6877000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   4583575500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  10403513000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5597910000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6848500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   4583078000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  10402761000                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.744737                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.812984                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.765178                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.761502                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.937644                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.858291                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.725297                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.794487                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.754039                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.252723                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.015152                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.304397                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.151578                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.734552                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.206186                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.031250                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.212503                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.191629                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.533248                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.492249                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.252723                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.015152                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.304397                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.271850                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.734552                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.206186                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.031250                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.212503                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.452562                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.533248                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.509761                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.252723                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.015152                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.304397                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.271850                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.734552                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.206186                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.031250                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.212503                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.452562                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.533248                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.509761                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20855.807591                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20761.905006                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20825.924852                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20883.477189                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20769.293924                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20814.933465                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 81527.978172                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71702.055608                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 77227.220720                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 76340.517241                       # average ReadSharedReq mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.743165                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.812687                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.763921                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.756167                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.935957                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.855319                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.730099                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.794773                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.756907                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.238189                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.018868                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.305677                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.152989                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735918                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.200935                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.213485                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.193442                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.521706                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.492738                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.238189                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.018868                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.305677                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.275354                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735918                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.200935                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.213485                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.453732                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.521706                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.510584                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.238189                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.018868                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.305677                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.275354                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735918                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.200935                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.213485                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.453732                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.521706                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.510584                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20769.507597                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20763.255032                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20767.521712                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20885.821832                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20753.915911                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20806.218905                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89188.348983                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72345.398628                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 81857.334088                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 75884.297521                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker       293000                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 70210.743167                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77691.337011                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 93208.507208                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82637.500000                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker        72500                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72396.539969                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78237.406015                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111831.236888                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 89927.343100                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76340.517241                       # average overall mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 69736.860959                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77710.489347                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91525.863287                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82139.534884                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72162.844037                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79111.646884                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109176.730645                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 88461.079428                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75884.297521                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       293000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70210.743167                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79837.204490                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 93208.507208                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82637.500000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        72500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72396.539969                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73271.578187                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111831.236888                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 88670.663637                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76340.517241                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69736.860959                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84163.292502                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91525.863287                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82139.534884                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72162.844037                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73981.434978                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109176.730645                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 87799.734481                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75884.297521                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       293000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70210.743167                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79837.204490                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 93208.507208                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82637.500000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        72500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72396.539969                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73271.578187                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111831.236888                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 88670.663637                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69736.860959                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84163.292502                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91525.863287                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82139.534884                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72162.844037                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73981.434978                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109176.730645                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 87799.734481                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182391.262082                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60858.407080                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145268.963706                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154989.231883                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 138126.775272                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145282.453341                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141435.452825                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182391.728237                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60606.194690                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145381.657323                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 155041.433892                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 138140.158749                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145335.820896                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141466.544719                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 161051.093211                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60858.407080                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145275.125986                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 148940.773085                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 161058.491815                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60606.194690                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145360.715532                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 148983.329753                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               38679                       # Transaction distribution
-system.membus.trans_dist::ReadResp             214027                       # Transaction distribution
-system.membus.trans_dist::WriteReq              31171                       # Transaction distribution
-system.membus.trans_dist::WriteResp             31171                       # Transaction distribution
-system.membus.trans_dist::Writeback            139502                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            18408                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            78648                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          41625                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           15041                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             39591                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            19084                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        175348                       # Transaction distribution
+system.membus.trans_dist::ReadReq               38664                       # Transaction distribution
+system.membus.trans_dist::ReadResp             213442                       # Transaction distribution
+system.membus.trans_dist::WriteReq              31161                       # Transaction distribution
+system.membus.trans_dist::WriteResp             31161                       # Transaction distribution
+system.membus.trans_dist::Writeback            139337                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            18210                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            78893                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          41609                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           14967                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             39746                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            19293                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        174778                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107912                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107910                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           42                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14764                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       682494                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       805212                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108922                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       108922                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 914134                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162794                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14714                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       681524                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       804190                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108938                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108938                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 913128                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162793                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1344                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        29528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19261796                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     19455462                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                21772582                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           126350                       # Total snoops (count)
-system.membus.snoop_fanout::samples            599467                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        29428                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19228072                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     19421637                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                21739781                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           126569                       # Total snoops (count)
+system.membus.snoop_fanout::samples            598906                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  599467    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  598906    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              599467                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            91393000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              598906                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            91147500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               24328                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               23828                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            12942500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            12904500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1014707988                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1003618732                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1166663343                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1163956699                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64473559                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64493538                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -2951,46 +2933,46 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq              38683                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            520875                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             31171                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            31171                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           372774                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          100063                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           82453                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         41960                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         124413                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           19                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           19                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            51599                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           51599                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       482207                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq              38668                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            519865                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             31161                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            31161                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           372085                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict           99404                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           82727                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         41949                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         124676                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           24                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           24                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            51768                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           51768                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       481212                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1095171                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       404182                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1499353                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     32852839                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6925951                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               39778790                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          466118                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          1289558                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.161505                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.367996                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1091980                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       404567                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1496547                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     32727326                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6930535                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               39657861                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          466410                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          1287380                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.161360                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.367862                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                1081288     83.85%     83.85% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 208270     16.15%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                1079649     83.86%     83.86% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 207731     16.14%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            1289558                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          856703495                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            1287380                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          861414818                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           361500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         633166148                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         631551677                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         285761511                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         286263459                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
index 82662bafe571a85a3ae25f711505d17f210fc906..409c3a759384c56ffd5016829e58cbb77f36db33 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.625395                       # Number of seconds simulated
-sim_ticks                                2625394935000                       # Number of ticks simulated
-final_tick                               2625394935000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.825406                       # Number of seconds simulated
+sim_ticks                                2825405893500                       # Number of ticks simulated
+final_tick                               2825405893500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  71798                       # Simulator instruction rate (inst/s)
-host_op_rate                                    87106                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1566670818                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 647044                       # Number of bytes of host memory used
-host_seconds                                  1675.78                       # Real time elapsed on the host
-sim_insts                                   120317196                       # Number of instructions simulated
-sim_ops                                     145970023                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  89977                       # Simulator instruction rate (inst/s)
+host_op_rate                                   109159                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2115602490                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 657340                       # Number of bytes of host memory used
+host_seconds                                  1335.51                       # Real time elapsed on the host
+sim_insts                                   120165205                       # Number of instructions simulated
+sim_ops                                     145782922                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker         1600                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker          448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1152320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1224232                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      8325184                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          640                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           318816                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           736276                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher       690624                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1275648                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1290856                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8427776                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          576                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           182944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           606480                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       427776                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12451228                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1152320                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       318816                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1471136                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9003520                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12214872                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1275648                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       182944                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1458592                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8756928                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9021084                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8774492                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker           25                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker            7                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             20252                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             19649                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       130081                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           10                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              5049                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             11525                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher        10791                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             22179                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             20690                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       131684                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker            9                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2926                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              9496                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher         6684                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                197406                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          140680                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                193712                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          136827                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               145071                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker           609                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker           171                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              438913                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              466304                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      3171022                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           244                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker            49                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              121435                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              280444                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       263055                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide              366                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4742611                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         438913                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         121435                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             560348                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3429396                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6675                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data                 15                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3436086                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3429396                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          609                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker          171                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             438913                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             472979                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      3171022                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          244                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker           49                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             121435                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             280459                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       263055                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide             366                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                8178698                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        197407                       # Number of read requests accepted
-system.physmem.writeReqs                       145071                       # Number of write requests accepted
-system.physmem.readBursts                      197407                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     145071                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12624448                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9600                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9033728                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12451292                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                9021084                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      150                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_writes::total               141218                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker           566                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker            68                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              451492                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              456875                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      2982855                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           204                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               64750                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              214652                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       151403                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4323227                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         451492                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          64750                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             516242                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3099352                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6202                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3105569                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3099352                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          566                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           68                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             451492                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             463077                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      2982855                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          204                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              64750                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             214667                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       151403                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7428796                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        193713                       # Number of read requests accepted
+system.physmem.writeReqs                       141218                       # Number of write requests accepted
+system.physmem.readBursts                      193713                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     141218                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12387136                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     10496                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8786752                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12214936                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8774492                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      164                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          50333                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               12702                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               12398                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12869                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               12803                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               14881                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               12147                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12755                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               12276                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               11968                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               12044                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11861                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11195                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11579                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              12354                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              11791                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11634                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                9169                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9145                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9512                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9193                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8772                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8759                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9221                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8821                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8638                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          49946                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               12421                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11965                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               12291                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               13088                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               14558                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12211                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11940                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               12041                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               12092                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               12171                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11769                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10768                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11340                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12292                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11321                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11281                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                9078                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8838                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9120                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9597                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8379                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8806                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8536                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8489                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8658                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                8679                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8601                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8338                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8547                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8875                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8631                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8251                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8573                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               8021                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8348                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8584                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7909                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7678                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          15                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2625394672500                       # Total gap between requests
+system.physmem.numWrRetry                          13                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2825405630500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                     551                       # Read request sizes (log2)
+system.physmem.readPktSize::2                     550                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                    3086                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  193742                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  190049                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 140680                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     60453                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     70781                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     16881                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     12152                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      8838                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      7520                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      6581                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      5428                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      4952                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1308                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      972                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      775                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      324                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      266                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        3                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 136827                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     58643                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     71509                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     15316                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     12788                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      8414                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      7274                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      6278                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      5174                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      4590                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      1392                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      933                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      695                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      285                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      252                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -188,159 +188,160 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2665                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4593                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5456                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6711                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8346                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8856                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    10182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9756                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9787                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     9219                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9902                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    11207                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     9191                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8461                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7930                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      662                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      456                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      371                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      274                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2640                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3080                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4486                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5343                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5977                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6530                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     8098                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8572                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     9894                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9480                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9411                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8905                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     9400                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    10669                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8786                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     8210                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7795                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      707                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      426                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      426                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      288                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      241                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      219                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      216                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      184                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      171                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      149                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      135                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::48                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       68                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       40                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        90794                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      238.541225                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     134.856216                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     301.373578                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          48956     53.92%     53.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17750     19.55%     73.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6013      6.62%     80.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3452      3.80%     83.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2808      3.09%     86.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1564      1.72%     88.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          893      0.98%     89.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          995      1.10%     90.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8363      9.21%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          90794                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7077                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.872686                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      551.008017                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           7075     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::49                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       51                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       24                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       41                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        87370                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      242.346618                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     136.604135                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     304.406981                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          46631     53.37%     53.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17108     19.58%     72.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5841      6.69%     79.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3374      3.86%     83.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2711      3.10%     86.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1534      1.76%     88.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          893      1.02%     89.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1014      1.16%     90.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8264      9.46%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          87370                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6825                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        28.358242                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      561.081040                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6823     99.97%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7077                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7077                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.945175                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.553311                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       11.579174                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5904     83.43%     83.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             368      5.20%     88.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             217      3.07%     91.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              59      0.83%     92.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              82      1.16%     93.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             159      2.25%     95.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              25      0.35%     96.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              12      0.17%     96.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              13      0.18%     96.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              11      0.16%     96.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              10      0.14%     96.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               6      0.08%     97.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             165      2.33%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               6      0.08%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               3      0.04%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               6      0.08%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               1      0.01%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               3      0.04%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               3      0.04%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               2      0.03%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.01%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.01%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.01%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            10      0.14%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             5      0.07%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7077                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     6986626052                       # Total ticks spent queuing
-system.physmem.totMemAccLat               10685194802                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    986285000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       35418.90                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6825                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6825                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.116190                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.646323                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.038338                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5646     82.73%     82.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             406      5.95%     88.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             199      2.92%     91.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              55      0.81%     92.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              78      1.14%     93.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             151      2.21%     95.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              25      0.37%     96.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              11      0.16%     96.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              15      0.22%     96.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               9      0.13%     96.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               8      0.12%     96.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               6      0.09%     96.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             163      2.39%     99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               7      0.10%     99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               2      0.03%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               8      0.12%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               2      0.03%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.01%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.03%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.03%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             2      0.03%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.01%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             2      0.03%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            16      0.23%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.03%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6825                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     6500326386                       # Total ticks spent queuing
+system.physmem.totMemAccLat               10129370136                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    967745000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       33584.91                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  54168.90                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.81                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.44                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.74                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.44                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  52334.91                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.38                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.11                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.32                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.11                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.22                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.34                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     164764                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     82850                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.53                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  58.69                       # Row buffer hit rate for writes
-system.physmem.avgGap                      7665878.31                       # Average gap between requests
-system.physmem.pageHitRate                      73.17                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  357081480                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  194836125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 802081800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                470396160                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           171477786480                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            75099546585                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1509358032750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1757759761380                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.522942                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2510844795677                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     87667580000                       # Time in different power states
+system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        27.47                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     161846                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     81625                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.62                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  59.44                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8435784.18                       # Average gap between requests
+system.physmem.pageHitRate                      73.58                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  343821240                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  187600875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 784017000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                459062640                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           184541675760                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            79593993450                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1625423449500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1891333620465                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.402761                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2703936458200                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     94346460000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     26879018073                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     27121665550                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  329321160                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  179689125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 736515000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                444268800                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           171477786480                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            74435410800                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1509940608000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1757543599365                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.440607                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2511823665901                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     87667580000                       # Time in different power states
+system.physmem_1.actEnergy                  316695960                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  172800375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 725657400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                430596000                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           184541675760                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            78590048175                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1626304103250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1891081576920                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.313555                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2705408031049                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     94346460000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     25903669599                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     25651382451                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          128                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          192                       # Number of bytes read from this memory
@@ -351,30 +352,30 @@ system.realview.nvmem.bytes_inst_read::total          320
 system.realview.nvmem.num_reads::cpu0.inst            8                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::total             20                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst           49                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst           73                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total              122                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst           49                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst           73                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total          122                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst           49                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst           73                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total             122                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.inst           45                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst           68                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total              113                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst           45                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst           68                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total          113                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst           45                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst           68                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total             113                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               51763361                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         23412597                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           921572                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            31250401                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               23297364                       # Number of BTB hits
+system.cpu0.branchPred.lookups               24021626                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         15717395                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           977579                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            14633586                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               10784998                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            74.550608                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               15315613                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             29376                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            73.700308                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                3879887                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             32532                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -405,80 +406,78 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                    63347                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               63347                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        24259                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        18763                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore        20325                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples        43022                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean   472.792990                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev  2838.942862                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-8191        41882     97.35%     97.35% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::8192-16383          877      2.04%     99.39% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::16384-24575          115      0.27%     99.66% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::24576-32767          113      0.26%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-40959            6      0.01%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::40960-49151           23      0.05%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::49152-57343            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::57344-65535            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-73727            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        43022                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        16160                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean  9833.168317                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean  8304.443400                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  6846.428458                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383        15169     93.87%     93.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767          911      5.64%     99.50% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151           54      0.33%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::49152-65535            3      0.02%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-98303            2      0.01%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-114687           20      0.12%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-212991            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        16160                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples  95658285656                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.461466                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.505385                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1  95607533656     99.95%     99.95% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3     37952000      0.04%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5      6012000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7      3722000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9      1321500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11       760000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13       604000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15       360500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17        20000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  95658285656                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         5176     77.00%     77.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1546     23.00%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         6722                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        63347                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                    65547                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               65547                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        26411                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        18806                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore        20330                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples        45217                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean   420.151713                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev  2682.973536                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-8191        44150     97.64%     97.64% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::8192-16383          821      1.82%     99.46% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-24575           92      0.20%     99.66% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::24576-32767          122      0.27%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-40959            7      0.02%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::40960-49151           22      0.05%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::57344-65535            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-73727            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::73728-81919            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        45217                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        15532                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean  9209.084471                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean  7773.401889                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  5863.053322                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383        14685     94.55%     94.55% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767          794      5.11%     99.66% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151           47      0.30%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::81920-98303            5      0.03%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::163840-180223            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        15532                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples  89510783948                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.549501                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.505567                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1  89461994948     99.95%     99.95% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3     35577000      0.04%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5      6153500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7      3637000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9      1264000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11       750500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13       798000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15       605000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17         4000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  89510783948                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         5141     79.20%     79.20% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1350     20.80%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         6491                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        65547                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        63347                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6722                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        65547                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6491                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6722                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        70069                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6491                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        72038                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    22737235                       # DTB read hits
-system.cpu0.dtb.read_misses                     54172                       # DTB read misses
-system.cpu0.dtb.write_hits                   16921500                       # DTB write hits
-system.cpu0.dtb.write_misses                     9175                       # DTB write misses
+system.cpu0.dtb.read_hits                    17771522                       # DTB read hits
+system.cpu0.dtb.read_misses                     55962                       # DTB read misses
+system.cpu0.dtb.write_hits                   14661221                       # DTB write hits
+system.cpu0.dtb.write_misses                     9585                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3524                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      141                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1882                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3484                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      322                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  2338                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      854                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                22791407                       # DTB read accesses
-system.cpu0.dtb.write_accesses               16930675                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      800                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                17827484                       # DTB read accesses
+system.cpu0.dtb.write_accesses               14670806                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         39658735                       # DTB hits
-system.cpu0.dtb.misses                          63347                       # DTB misses
-system.cpu0.dtb.accesses                     39722082                       # DTB accesses
+system.cpu0.dtb.hits                         32432743                       # DTB hits
+system.cpu0.dtb.misses                          65547                       # DTB misses
+system.cpu0.dtb.accesses                     32498290                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -508,62 +507,57 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    10275                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort               10275                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1         4076                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         6085                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore          114                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples        10161                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean   480.267690                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  2390.213266                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-4095         9738     95.84%     95.84% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::4096-8191          133      1.31%     97.15% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::8192-12287          215      2.12%     99.26% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::12288-16383           37      0.36%     99.63% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::16384-20479            9      0.09%     99.71% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::20480-24575           15      0.15%     99.86% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::24576-28671            3      0.03%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::28672-32767            3      0.03%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-36863            2      0.02%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::36864-40959            4      0.04%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::40960-45055            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::45056-49151            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        10161                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         2702                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 11438.934123                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 10140.740913                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  6204.580963                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191          871     32.24%     32.24% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383         1681     62.21%     94.45% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575           53      1.96%     96.41% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-32767           85      3.15%     99.56% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-40959            7      0.26%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::40960-49151            1      0.04%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::49152-57343            1      0.04%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::81920-90111            1      0.04%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::90112-98303            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::98304-106495            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         2702                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples  22643799124                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.979659                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.141451                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0      461404000      2.04%      2.04% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1    22181693124     97.96%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2         593000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3         109000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total  22643799124                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         2268     87.64%     87.64% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          320     12.36%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2588                       # Table walker page sizes translated
+system.cpu0.itb.walker.walks                    10460                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort               10460                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1         4240                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         6125                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore           95                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        10365                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean   435.745297                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  2168.024140                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-4095         9957     96.06%     96.06% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::4096-8191          147      1.42%     97.48% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::8192-12287          193      1.86%     99.34% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::12288-16383           32      0.31%     99.65% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::16384-20479           11      0.11%     99.76% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::20480-24575           17      0.16%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::24576-28671            2      0.02%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::28672-32767            1      0.01%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-36863            2      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::36864-40959            3      0.03%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        10365                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         2678                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 10848.207618                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean  9582.239797                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  5620.252827                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191         1037     38.72%     38.72% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383         1516     56.61%     95.33% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575           52      1.94%     97.27% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-32767           65      2.43%     99.70% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-40959            5      0.19%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::40960-49151            2      0.07%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::81920-90111            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total         2678                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples  20779406712                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.976236                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.152563                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0      494503000      2.38%      2.38% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    20284294712     97.62%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2         517000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3          92000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total  20779406712                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         2260     87.50%     87.50% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          323     12.50%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2583                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        10275                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        10275                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        10460                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        10460                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2588                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2588                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total        12863                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    70928349                       # ITB inst hits
-system.cpu0.itb.inst_misses                     10275                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2583                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2583                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total        13043                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    37759439                       # ITB inst hits
+system.cpu0.itb.inst_misses                     10460                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -572,1041 +566,1029 @@ system.cpu0.itb.flush_tlb                          66                       # Nu
 system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2365                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2357                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1936                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     1912                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                70938624                       # ITB inst accesses
-system.cpu0.itb.hits                         70928349                       # DTB hits
-system.cpu0.itb.misses                          10275                       # DTB misses
-system.cpu0.itb.accesses                     70938624                       # DTB accesses
-system.cpu0.numCycles                       192976868                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                37769899                       # ITB inst accesses
+system.cpu0.itb.hits                         37759439                       # DTB hits
+system.cpu0.itb.misses                          10460                       # DTB misses
+system.cpu0.itb.accesses                     37769899                       # DTB accesses
+system.cpu0.numCycles                       130135672                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          19363908                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     190332929                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   51763361                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          38612977                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    166709106                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                5608958                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                    145099                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               54692                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles       348676                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       420281                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles        85262                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 70928958                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               257958                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   4691                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         189931503                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.225932                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.310916                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          18741348                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     112674064                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   24021626                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          14664885                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    105564363                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                2824766                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                    148935                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               59402                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles       359448                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       427042                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles        91226                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 37760092                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               271445                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   4846                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         126804147                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.071967                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.260919                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                88125904     46.40%     46.40% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                29232702     15.39%     61.79% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                14108338      7.43%     69.22% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                58464559     30.78%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                64261882     50.68%     50.68% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                21462384     16.93%     67.60% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 8772204      6.92%     74.52% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                32307677     25.48%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           189931503                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.268236                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.986299                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                24608865                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            101406874                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 56677604                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              4757932                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               2480228                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             2944179                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred               328448                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             148845488                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts              3759445                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               2480228                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                33020653                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               11928133                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      79389996                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 52895431                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             10217062                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             132354164                       # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts              1007004                       # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents              1382043                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                149840                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                 52195                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               6188026                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands          135879963                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            611395498                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       146969281                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups             9373                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            124973310                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                10906650                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           2656416                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts       2518561                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 22027855                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            23660512                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           18424443                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1639164                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         2432445                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 129487187                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1661777                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                127665829                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           454854                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       10484678                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     21309646                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        116701                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    189931503                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.672168                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       0.963951                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           126804147                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.184589                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.865820                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                19721438                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             59617090                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 41434685                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              4962697                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1068237                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             3055964                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred               348356                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             110795648                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts              3978318                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1068237                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                25470078                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               12211623                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      36823403                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 40512045                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             10718761                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             105720614                       # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts              1057290                       # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents              1452767                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                161700                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                 58122                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               6514709                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands          109806374                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            482725120                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       121004760                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups             9383                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             98259136                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                11547235                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1229554                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts       1088238                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 12335468                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            18754417                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           16214275                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1701393                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         2256069                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 102765106                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1695392                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                100794287                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           484302                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        9532947                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     22407435                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        122350                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    126804147                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.794882                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.031887                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          116041258     61.10%     61.10% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           32572628     17.15%     78.25% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2           29941917     15.76%     94.01% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           10293469      5.42%     99.43% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            1082195      0.57%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5                 36      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           70515231     55.61%     55.61% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           23338464     18.41%     74.01% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2           22507800     17.75%     91.76% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            9330414      7.36%     99.12% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            1112209      0.88%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                 29      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      189931503                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      126804147                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu               10298963     43.90%     43.90% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                   129      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     43.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               5415712     23.09%     66.99% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite              7742693     33.01%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                9354884     40.60%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                    74      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     40.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               5601126     24.31%     64.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite              8088042     35.10%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass             2272      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             86175456     67.50%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult              106512      0.08%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc          7179      0.01%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            23410232     18.34%     85.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           17964178     14.07%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass             2273      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             66470143     65.95%     65.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               93430      0.09%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  1      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc          8105      0.01%     66.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            18478690     18.33%     84.38% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           15741645     15.62%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             127665829                       # Type of FU issued
-system.cpu0.iq.rate                          0.661560                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                   23457497                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.183741                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         469142790                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        141641253                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    124187141                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              32722                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes             11272                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         9724                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             151099696                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                  21358                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          349091                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             100794287                       # Type of FU issued
+system.cpu0.iq.rate                          0.774532                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                   23044126                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.228625                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         351888789                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        114001116                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     98678663                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              32360                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes             11294                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         9725                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             123815106                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                  21034                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          363531                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1883461                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2555                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        18950                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       972383                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1999131                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2544                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        19035                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      1014690                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads       113459                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       340118                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads       107294                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       362990                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               2480228                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                1536268                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               176000                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          131320075                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles               1068237                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                1634305                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               175316                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          104635112                       # Number of instructions dispatched to IQ
 system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             23660512                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            18424443                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            851631                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 24928                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               129599                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         18950                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        275039                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       375413                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              650452                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            126634007                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             22982824                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           968597                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts             18754417                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            16214275                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            876681                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 26796                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents               125236                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         19035                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        291770                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       399939                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              691709                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             99697701                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             18022679                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          1031168                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       171111                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    40767921                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                24572908                       # Number of branches executed
-system.cpu0.iew.exec_stores                  17785097                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.656213                       # Inst execution rate
-system.cpu0.iew.wb_sent                     126104266                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    124196865                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 63208416                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                102222094                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       174614                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    33573838                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                16859604                       # Number of branches executed
+system.cpu0.iew.exec_stores                  15551159                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.766106                       # Inst execution rate
+system.cpu0.iew.wb_sent                      99140543                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     98688388                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 51348142                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 84871692                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.643584                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.618344                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.758350                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.605009                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts        9488534                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls        1545076                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           597321                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    186809549                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.646573                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.344397                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts        8492759                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls        1573042                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           633433                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    125053157                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.760074                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.473514                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    128903317     69.00%     69.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     31993486     17.13%     86.13% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     12242174      6.55%     92.68% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      3077822      1.65%     94.33% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      4650551      2.49%     96.82% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      2601023      1.39%     98.21% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      1367878      0.73%     98.94% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       526295      0.28%     99.23% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1447003      0.77%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     80626724     64.47%     64.47% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     24772258     19.81%     84.28% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      8266840      6.61%     90.89% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      3238221      2.59%     93.48% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      3432782      2.75%     96.23% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      1539199      1.23%     97.46% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      1134355      0.91%     98.37% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       546479      0.44%     98.80% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1496299      1.20%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    186809549                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            99693903                       # Number of instructions committed
-system.cpu0.commit.committedOps             120785976                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    125053157                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            78998098                       # Number of instructions committed
+system.cpu0.commit.committedOps              95049599                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      39229111                       # Number of memory references committed
-system.cpu0.commit.loads                     21777051                       # Number of loads committed
-system.cpu0.commit.membars                     629182                       # Number of memory barriers committed
-system.cpu0.commit.branches                  23976855                       # Number of branches committed
+system.cpu0.commit.refs                      31954871                       # Number of memory references committed
+system.cpu0.commit.loads                     16755286                       # Number of loads committed
+system.cpu0.commit.membars                     647733                       # Number of memory barriers committed
+system.cpu0.commit.branches                  16226575                       # Number of branches committed
 system.cpu0.commit.fp_insts                      9708                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                105625598                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls             4749745                       # Number of function calls committed.
+system.cpu0.commit.int_insts                 81983360                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls             1932291                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        81445291     67.43%     67.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult         104395      0.09%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc         7179      0.01%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       21777051     18.03%     85.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      17452060     14.45%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        62995577     66.28%     66.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          91046      0.10%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc         8105      0.01%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       16755286     17.63%     84.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      15199585     15.99%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        120785976                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1447003                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   292572702                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  263669539                       # The number of ROB writes
-system.cpu0.timesIdled                         123127                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        3045365                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  5057813082                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   99572209                       # Number of Instructions Simulated
-system.cpu0.committedOps                    120664282                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.938060                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.938060                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.515980                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.515980                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               137228019                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               78727155                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                     8192                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                    2264                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                446969794                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes                47254034                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads              263157526                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes               1194331                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements           673421                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          483.801587                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           36230548                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           673933                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            53.759866                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        274448500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   483.801587                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.944925                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.944925                       # Average percentage of cache occupancy
+system.cpu0.commit.op_class_0::total         95049599                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1496299                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                   222908078                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  208834787                       # The number of ROB writes
+system.cpu0.timesIdled                         129596                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        3331525                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  5520676264                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   78876046                       # Number of Instructions Simulated
+system.cpu0.committedOps                     94927547                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.649876                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.649876                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.606106                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.606106                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               110754452                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               59798186                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                     8167                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                    2269                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                351214590                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes                41113323                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads              177297499                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes               1225193                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements           713718                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          494.250179                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           28854841                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           714230                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            40.399929                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        274766500                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   494.250179                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.965332                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.965332                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          180                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          181                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          310                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           22                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         78023145                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        78023145                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     20647656                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       20647656                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     14394101                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      14394101                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       296444                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       296444                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       354739                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       354739                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       351671                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       351671                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     35041757                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        35041757                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     35338201                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       35338201                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       609728                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       609728                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1806132                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1806132                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       141710                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       141710                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        24359                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        24359                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        21165                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        21165                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2415860                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2415860                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      2557570                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2557570                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   8120126000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   8120126000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  26313440366                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  26313440366                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    385463000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    385463000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    480627500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    480627500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       430000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total       430000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  34433566366                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  34433566366                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  34433566366                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  34433566366                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     21257384                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     21257384                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     16200233                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     16200233                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       438154                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       438154                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       379098                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       379098                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       372836                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       372836                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     37457617                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     37457617                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     37895771                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     37895771                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.028683                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.028683                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.111488                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.111488                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.323425                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.323425                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.064255                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.064255                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.056768                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.056768                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.064496                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.064496                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.067490                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.067490                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13317.620316                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13317.620316                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14568.946437                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 14568.946437                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15824.253869                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15824.253869                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22708.599102                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22708.599102                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         63563549                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        63563549                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     15604955                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       15604955                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     12027073                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      12027073                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       310316                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       310316                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       363058                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       363058                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       361354                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       361354                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     27632028                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        27632028                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     27942344                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       27942344                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       644494                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       644494                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1893203                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1893203                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       147485                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       147485                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        25333                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        25333                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20104                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        20104                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2537697                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2537697                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      2685182                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2685182                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   8536879000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   8536879000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  27482436369                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  27482436369                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    389618000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    389618000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    450883500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    450883500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       454000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total       454000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  36019315369                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  36019315369                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  36019315369                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  36019315369                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     16249449                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     16249449                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     13920276                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     13920276                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       457801                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       457801                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       388391                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       388391                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381458                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       381458                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     30169725                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     30169725                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     30627526                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     30627526                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.039663                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.039663                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.136003                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.136003                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.322160                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.322160                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.065226                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.065226                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.052703                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.052703                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.084114                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.084114                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.087672                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.087672                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13245.862646                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13245.862646                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14516.370600                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 14516.370600                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15379.860261                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15379.860261                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22427.551731                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22427.551731                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14253.129886                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 14253.129886                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13463.391565                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 13463.391565                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs          747                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets      3913122                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs               47                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets         192454                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    15.893617                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    20.332765                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14193.702152                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 14193.702152                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13414.105773                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 13414.105773                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs          682                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets      4150493                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs               48                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets         202595                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.208333                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    20.486651                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       491417                       # number of writebacks
-system.cpu0.dcache.writebacks::total           491417                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       243049                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       243049                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1494093                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1494093                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        18165                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18165                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1737142                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1737142                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1737142                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1737142                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       366679                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       366679                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       312039                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       312039                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        98387                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total        98387                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6194                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6194                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        21165                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        21165                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       678718                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       678718                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       777105                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       777105                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        29394                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        29394                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        26127                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        26127                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        55521                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        55521                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4291687500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4291687500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5394914387                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5394914387                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1614083000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1614083000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     96183500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     96183500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    459474500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    459474500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       418000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       418000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9686601887                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   9686601887                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  11300684887                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  11300684887                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5681056500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5681056500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   4312326500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4312326500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   9993383000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   9993383000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017249                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017249                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019261                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019261                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.224549                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224549                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016339                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016339                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.056768                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.056768                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.018120                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.018120                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.020506                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.020506                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11704.208586                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11704.208586                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17289.231112                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17289.231112                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16405.449907                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16405.449907                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15528.495318                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15528.495318                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21709.166076                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21709.166076                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       517170                       # number of writebacks
+system.cpu0.dcache.writebacks::total           517170                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       254611                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       254611                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1567828                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1567828                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        18755                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18755                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1822439                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1822439                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1822439                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1822439                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       389883                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       389883                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       325375                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       325375                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       102048                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       102048                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6578                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6578                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20104                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        20104                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       715258                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       715258                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       817306                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       817306                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        20386                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20386                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        19086                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        19086                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        39472                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        39472                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4555035000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4555035000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5512912898                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5512912898                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1660765500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1660765500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    101006000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    101006000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    430792500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    430792500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       441000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       441000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10067947898                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  10067947898                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  11728713398                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  11728713398                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4315293000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4315293000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3299266500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3299266500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7614559500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7614559500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.023994                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.023994                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023374                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.023374                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.222909                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.222909                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016937                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016937                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.052703                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.052703                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023708                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.023708                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026685                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.026685                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11683.081848                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11683.081848                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16943.259003                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16943.259003                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16274.356185                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16274.356185                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15355.123138                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15355.123138                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21428.198368                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21428.198368                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14271.909522                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14271.909522                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14542.030854                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14542.030854                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193272.657685                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193272.657685                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165052.493589                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165052.493589                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179992.849552                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179992.849552                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14075.966851                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14075.966851                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14350.455518                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14350.455518                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 211679.240655                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 211679.240655                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172863.171959                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172863.171959                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 192910.404844                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 192910.404844                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1208444                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.748718                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           69666115                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1208956                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            57.625021                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       6421480000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.748718                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999509                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999509                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          1264231                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.765651                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           36438607                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1264743                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            28.811076                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       6439669000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.765651                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999542                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999542                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          134                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          231                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          147                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          140                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          241                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          131                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        143059850                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       143059850                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     69666115                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       69666115                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     69666115                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        69666115                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     69666115                       # number of overall hits
-system.cpu0.icache.overall_hits::total       69666115                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1259322                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1259322                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1259322                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1259322                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1259322                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1259322                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  12306647041                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  12306647041                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  12306647041                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  12306647041                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  12306647041                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  12306647041                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     70925437                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     70925437                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     70925437                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     70925437                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     70925437                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     70925437                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.017756                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.017756                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.017756                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.017756                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.017756                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.017756                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9772.438694                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9772.438694                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9772.438694                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  9772.438694                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9772.438694                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  9772.438694                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs      1459740                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets          453                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs           110714                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets             10                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.184782                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets    45.300000                       # average number of cycles each access was blocked
+system.cpu0.icache.tags.tag_accesses         76777836                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        76777836                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     36438607                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       36438607                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     36438607                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        36438607                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     36438607                       # number of overall hits
+system.cpu0.icache.overall_hits::total       36438607                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1317920                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1317920                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1317920                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1317920                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1317920                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1317920                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13045197783                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  13045197783                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  13045197783                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  13045197783                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  13045197783                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  13045197783                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     37756527                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     37756527                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     37756527                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     37756527                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     37756527                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     37756527                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.034906                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.034906                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.034906                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.034906                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.034906                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.034906                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9898.322951                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9898.322951                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9898.322951                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9898.322951                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9898.322951                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9898.322951                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs      1585730                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets          630                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs           117915                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets             11                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.448077                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets    57.272727                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        50344                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        50344                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        50344                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        50344                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        50344                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        50344                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1208978                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1208978                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1208978                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1208978                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1208978                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1208978                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        53136                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        53136                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        53136                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        53136                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        53136                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        53136                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1264784                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1264784                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      1264784                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1264784                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      1264784                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1264784                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3004                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total         3004                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3004                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total         3004                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11179466333                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  11179466333                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11179466333                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  11179466333                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11179466333                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  11179466333                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11837775153                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  11837775153                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11837775153                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  11837775153                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11837775153                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  11837775153                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    265874998                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    265874998                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    265874998                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total    265874998                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.017046                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017046                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.017046                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.017046                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.017046                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.017046                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9247.038683                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9247.038683                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9247.038683                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  9247.038683                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9247.038683                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  9247.038683                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.033498                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.033498                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.033498                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.033498                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.033498                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.033498                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9359.523170                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9359.523170                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9359.523170                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  9359.523170                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9359.523170                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  9359.523170                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88506.990013                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88506.990013                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88506.990013                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88506.990013                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      1763942                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      1769107                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit         4567                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      1848695                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      1851312                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit         2366                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       220637                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements          266650                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16052.098762                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           3449668                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          282876                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs           12.194983                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  9287.877050                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    13.757624                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.215297                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4106.053527                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1602.376504                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1041.818760                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.566887                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000840                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000013                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.250614                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.097801                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.063588                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.979742                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1056                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           12                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15158                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           44                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          321                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          415                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          276                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            6                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            6                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          414                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4651                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7186                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2852                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.064453                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000732                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.925171                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        63497786                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       63497786                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        50315                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker        12479                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total         62794                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks       491416                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total       491416                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28453                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total        28453                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1608                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total         1608                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       210730                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       210730                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1158323                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      1158323                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       372689                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total       372689                       # number of ReadSharedReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        50315                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker        12479                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      1158323                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       583419                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        1804536                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        50315                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker        12479                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      1158323                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       583419                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       1804536                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          419                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          174                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total          593                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        27292                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        27292                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19556                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        19556                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            1                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data        45826                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total        45826                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        50641                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total        50641                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data        98477                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total        98477                       # number of ReadSharedReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          419                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker          174                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst        50641                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data       144303                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total       195537                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          419                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker          174                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst        50641                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data       144303                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total       195537                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     11008500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      4405500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total     15414000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    502449500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total    502449500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    396768500                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    396768500                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       399000                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       399000                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2648910998                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total   2648910998                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   2424883999                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total   2424883999                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   2835688998                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total   2835688998                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     11008500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      4405500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst   2424883999                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data   5484599996                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total   7924897995                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     11008500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      4405500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst   2424883999                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data   5484599996                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total   7924897995                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        50734                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker        12653                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total        63387                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks       491416                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total       491416                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55745                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total        55745                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        21164                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total        21164                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       256556                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total       256556                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1208964                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      1208964                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       471166                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total       471166                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        50734                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker        12653                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      1208964                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data       727722                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total      2000073                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        50734                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker        12653                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      1208964                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data       727722                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total      2000073                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.008259                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.013752                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.009355                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.489587                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.489587                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.924022                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.924022                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.178620                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.178620                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.041888                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.041888                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.209007                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.209007                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.008259                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.013752                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.041888                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.198294                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.097765                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.008259                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.013752                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.041888                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.198294                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.097765                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26273.269690                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 25318.965517                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 25993.254637                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18410.138502                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18410.138502                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20288.837186                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20288.837186                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       399000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       399000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 57803.670362                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 57803.670362                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 47883.809542                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 47883.809542                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 28795.444601                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 28795.444601                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26273.269690                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 25318.965517                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 47883.809542                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38007.525803                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 40528.892205                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26273.269690                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 25318.965517                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 47883.809542                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38007.525803                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 40528.892205                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs          236                       # number of cycles access was blocked
+system.cpu0.l2cache.prefetcher.pfSpanPage       233112                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements          279786                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16110.932478                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           3625969                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          296031                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs           12.248612                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle    2809841331000                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks  7402.389300                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    11.896732                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     1.359713                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  5003.167978                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1996.783797                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1695.334959                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.451806                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000726                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000083                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.305369                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.121874                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.103475                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.983333                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1041                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023            9                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15195                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           33                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          317                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          403                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          288                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          425                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4805                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7004                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2900                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.063538                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000549                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.927429                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        66593364                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses       66593364                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        52693                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker        12386                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total         65079                       # number of ReadReq hits
+system.cpu0.l2cache.Writeback_hits::writebacks       517165                       # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total       517165                       # number of Writeback hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28793                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total        28793                       # number of UpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1744                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::total         1744                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       223098                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       223098                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1208893                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      1208893                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       400319                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total       400319                       # number of ReadSharedReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        52693                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker        12386                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      1208893                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data       623417                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total        1897389                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        52693                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker        12386                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      1208893                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data       623417                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total       1897389                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          398                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          157                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total          555                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        26381                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total        26381                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        18360                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total        18360                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data        47293                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total        47293                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        55856                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total        55856                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data        98075                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total        98075                       # number of ReadSharedReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          398                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker          157                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst        55856                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data       145368                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total       201779                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          398                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker          157                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst        55856                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data       145368                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total       201779                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     10822500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      3611000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total     14433500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    484495000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total    484495000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    371083000                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    371083000                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       421500                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       421500                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2673446497                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total   2673446497                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   2697437499                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total   2697437499                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   2928360998                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total   2928360998                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     10822500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      3611000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst   2697437499                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data   5601807495                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total   8313678494                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     10822500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      3611000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst   2697437499                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data   5601807495                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total   8313678494                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        53091                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker        12543                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total        65634                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::writebacks       517165                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total       517165                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55174                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total        55174                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20104                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total        20104                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       270391                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total       270391                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1264749                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      1264749                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       498394                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total       498394                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        53091                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker        12543                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      1264749                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data       768785                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total      2099168                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        53091                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker        12543                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      1264749                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data       768785                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      2099168                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.007497                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.012517                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.008456                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.478142                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.478142                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.913251                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.913251                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.174906                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.174906                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.044164                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.044164                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.196782                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.196782                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.007497                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.012517                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.044164                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.189088                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.096123                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.007497                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.012517                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.044164                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.189088                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.096123                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27192.211055                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker        23000                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26006.306306                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18365.300785                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18365.300785                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20211.492375                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20211.492375                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 56529.433468                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 56529.433468                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 48292.708017                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 48292.708017                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29858.383869                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29858.383869                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27192.211055                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker        23000                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 48292.708017                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38535.355064                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 41201.901556                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27192.211055                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker        23000                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 48292.708017                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38535.355064                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 41201.901556                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs          214                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               8                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    29.500000                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    26.750000                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       193260                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          193260                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            1                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.writebacks::writebacks       197696                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          197696                       # number of writebacks
 system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            1                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total            2                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         6054                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         6054                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           30                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           30                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          713                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          713                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5476                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         5476                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           32                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           32                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          797                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          797                       # number of ReadSharedReq MSHR hits
 system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            1                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           30                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         6767                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         6799                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            1                       # number of overall MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           32                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         6273                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total         6306                       # number of demand (read+write) MSHR hits
 system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            1                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           30                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         6767                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         6799                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          418                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          173                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total          591                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks         8374                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::total         8374                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       232540                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       232540                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        27292                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        27292                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19556                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19556                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        39772                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        39772                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        50611                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        50611                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data        97764                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total        97764                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          418                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          173                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        50611                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data       137536                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total       188738                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          418                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          173                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        50611                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data       137536                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       232540                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total       421278                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           32                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         6273                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total         6306                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          398                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          156                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total          554                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks         8991                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::total         8991                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       245693                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       245693                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        26381                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        26381                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        18360                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        18360                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41817                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total        41817                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        55824                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        55824                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data        97278                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total        97278                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          398                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          156                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        55824                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data       139095                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total       195473                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          398                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          156                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        55824                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data       139095                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       245693                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total       441166                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3004                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        29394                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        32398                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        26127                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        26127                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        20386                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        23390                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        19086                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        19086                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3004                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        55521                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        58525                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      8479500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      3355000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     11834500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  15228773142                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  15228773142                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    539452500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    539452500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    299483497                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    299483497                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       327000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       327000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1648200500                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1648200500                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2120543999                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2120543999                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2210587998                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2210587998                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      8479500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      3355000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2120543999                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   3858788498                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total   5991166997                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      8479500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      3355000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2120543999                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   3858788498                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  15228773142                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  21219940139                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        39472                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        42476                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      8434500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2662500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     11097000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  15042795977                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  15042795977                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    537912499                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    537912499                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    278663498                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    278663498                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       343500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       343500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1730970000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1730970000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2361388499                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2361388499                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2303131998                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2303131998                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      8434500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2662500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2361388499                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   4034101998                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total   6406587497                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      8434500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2662500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2361388499                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   4034101998                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  15042795977                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  21449383474                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    243342000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5445807000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   5689149000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   4113464958                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4113464958                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4152104000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4395446000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3153204958                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3153204958                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    243342000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   9559271958                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   9802613958                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.008239                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.013673                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.009324                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   7305308958                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7548650958                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.007497                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.012437                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.008441                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.489587                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.489587                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.924022                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.924022                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.155023                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.155023                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.041863                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.041863                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.207494                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.207494                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.008239                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.013673                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.041863                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.188995                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.094366                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.008239                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.013673                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.041863                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.188995                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.478142                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.478142                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.913251                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.913251                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.154654                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.154654                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.044138                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.044138                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.195183                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.195183                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.007497                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.012437                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.044138                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.180928                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.093119                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.007497                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.012437                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.044138                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.180928                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.210631                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20285.885167                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19393.063584                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20024.534687                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65488.832640                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65488.832640                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19765.957057                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19765.957057                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15314.148957                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15314.148957                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       327000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       327000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41441.227497                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41441.227497                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 41898.875719                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 41898.875719                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22611.472505                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22611.472505                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20285.885167                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19393.063584                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 41898.875719                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28056.570629                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31743.300220                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20285.885167                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19393.063584                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 41898.875719                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28056.570629                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65488.832640                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50370.397075                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.210162                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21192.211055                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17067.307692                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20030.685921                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61225.985181                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 61225.985181                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20390.148175                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20390.148175                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15177.750436                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15177.750436                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41393.930698                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41393.930698                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42300.596500                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42300.596500                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23675.774564                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23675.774564                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21192.211055                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17067.307692                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42300.596500                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29002.494683                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32774.794969                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21192.211055                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17067.307692                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42300.596500                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29002.494683                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61225.985181                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 48619.756450                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81005.992011                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185269.340682                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175601.858139                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157441.151223                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157441.151223                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203674.286275                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 187919.880291                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165210.361417                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165210.361417                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81005.992011                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 172173.987464                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 167494.471730                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 185075.723500                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 177715.673745                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq        116134                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      1839025                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        31035                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        26127                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback       864426                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict      1492254                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       304971                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        91775                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43512                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       114568                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           12                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       284553                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       270414                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1208978                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq       592867                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadReq        118491                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      1915950                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        30902                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        19086                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback       881917                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      1558941                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       295049                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        88486                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42808                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       113105                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           16                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           29                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       298585                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       285519                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1264784                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       601994                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3608808                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2486821                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        28899                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       112519                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          6237047                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     77421632                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     82196692                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        50612                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       202936                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         159871872                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    1179844                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      5097277                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       1.224281                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.417108                       # Request fanout histogram
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3774932                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2575467                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        29033                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       117114                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          6496546                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     80991872                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     86506920                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        50172                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       212364                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         167761328                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    1157195                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      5250259                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       1.213502                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.409779                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1           3954053     77.57%     77.57% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2           1143224     22.43%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1           4129320     78.65%     78.65% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2           1120939     21.35%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       5097277                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    2520550941                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       5250259                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    2631653442                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    112317000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    114940499                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   1816757420                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   1900515323                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1173564387                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1221760496                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy     16253983                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy     16493992                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     61816936                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     64044457                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups                6152669                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          3868120                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           360109                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             3337115                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                2452438                       # Number of BTB hits
+system.cpu1.branchPred.lookups               33870827                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         11547618                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           303923                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            18735544                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               14949091                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            73.489766                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                1042883                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             10537                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            79.790002                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               12480037                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect              7268                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1636,91 +1618,92 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    24322                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               24322                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        11233                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         5990                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore         7099                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        17223                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean   438.425361                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev  2740.461547                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-4095        16689     96.90%     96.90% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::4096-8191          124      0.72%     97.62% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::8192-12287          219      1.27%     98.89% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::12288-16383           86      0.50%     99.39% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::16384-20479           20      0.12%     99.51% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::20480-24575           13      0.08%     99.58% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::24576-28671           39      0.23%     99.81% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::28672-32767           13      0.08%     99.88% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-36863           16      0.09%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::45056-49151            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::49152-53247            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::53248-57343            2      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        17223                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         5609                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 10144.232484                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean  8674.966878                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  6379.427582                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191         2437     43.45%     43.45% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383         2571     45.84%     89.29% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575          453      8.08%     97.36% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-32767          115      2.05%     99.41% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-40959            3      0.05%     99.47% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::40960-49151           25      0.45%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::90112-98303            4      0.07%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks                    21101                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               21101                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         8660                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         5796                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore         6645                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        14456                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean   508.058937                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev  2886.331667                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-4095        13910     96.22%     96.22% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::4096-8191          137      0.95%     97.17% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::8192-12287          242      1.67%     98.84% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::12288-16383           68      0.47%     99.32% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::16384-20479           20      0.14%     99.45% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::20480-24575           12      0.08%     99.54% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::24576-28671           37      0.26%     99.79% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::28672-32767           11      0.08%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-36863           15      0.10%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::36864-40959            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::40960-45055            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::45056-49151            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::49152-53247            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        14456                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         5194                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean  9424.913362                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean  8003.762670                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  6175.333367                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-8191         2569     49.46%     49.46% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-16383         2132     41.05%     90.51% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-24575          361      6.95%     97.46% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-32767           99      1.91%     99.36% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-40959            3      0.06%     99.42% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::40960-49151           27      0.52%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::90112-98303            2      0.04%     99.98% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::106496-114687            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         5609                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  69613371380                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.373428                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.487046                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0    43658416792     62.72%     62.72% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1    25935559588     37.26%     99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2       12091000      0.02%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::3        3523500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4        1046500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::5         593000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6         908500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::7         323500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8         151000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::9         143500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10         80500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::11         88500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12        153000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::13         38000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14         28000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::15        226500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  69613371380                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         1968     73.85%     73.85% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          697     26.15%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         2665                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        24322                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkCompletionTime::total         5194                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  72058045764                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.162272                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.372420                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    60402096044     83.82%     83.82% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1    11637981720     16.15%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2       11426500      0.02%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::3        2950500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4         950000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::5         753000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6         773000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::7         312500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8         161500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::9         148500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10         75000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::11         48000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12        134500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::13         51500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14         27000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::15        156500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  72058045764                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         1910     75.91%     75.91% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          606     24.09%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         2516                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        21101                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        24322                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2665                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        21101                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2516                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2665                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        26987                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2516                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        23617                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     5224196                       # DTB read hits
-system.cpu1.dtb.read_misses                     21002                       # DTB read misses
-system.cpu1.dtb.write_hits                    4300766                       # DTB write hits
-system.cpu1.dtb.write_misses                     3320                       # DTB write misses
+system.cpu1.dtb.read_hits                    10151644                       # DTB read hits
+system.cpu1.dtb.read_misses                     18305                       # DTB read misses
+system.cpu1.dtb.write_hits                    6523716                       # DTB write hits
+system.cpu1.dtb.write_misses                     2796                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    2043                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                       67                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   616                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    2013                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                       50                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   456                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      364                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 5245198                       # DTB read accesses
-system.cpu1.dtb.write_accesses                4304086                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      384                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                10169949                       # DTB read accesses
+system.cpu1.dtb.write_accesses                6526512                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          9524962                       # DTB hits
-system.cpu1.dtb.misses                          24322                       # DTB misses
-system.cpu1.dtb.accesses                      9549284                       # DTB accesses
+system.cpu1.dtb.hits                         16675360                       # DTB hits
+system.cpu1.dtb.misses                          21101                       # DTB misses
+system.cpu1.dtb.accesses                     16696461                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1750,58 +1733,60 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     6842                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                6842                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1         4094                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2680                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore           68                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples         6774                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean   241.142604                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  1918.263476                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-4095         6651     98.18%     98.18% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::4096-8191           49      0.72%     98.91% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::8192-12287           35      0.52%     99.42% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::12288-16383           15      0.22%     99.65% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::16384-20479            5      0.07%     99.72% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::20480-24575           10      0.15%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::24576-28671            5      0.07%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::28672-32767            2      0.03%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::36864-40959            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::49152-53247            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         6774                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         1233                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 11141.524736                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean  9875.363796                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  6280.061079                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-8191          357     28.95%     28.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-16383          797     64.64%     93.59% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-24575           18      1.46%     95.05% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-32767           48      3.89%     98.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-40959            5      0.41%     99.35% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-49151            7      0.57%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-73727            1      0.08%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         1233                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  18042065828                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.988332                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.107619                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0      210878764      1.17%      1.17% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1    17830879064     98.83%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2         267500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3          19000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4          21500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  18042065828                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K          995     85.41%     85.41% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          170     14.59%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total         1165                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                     6899                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                6899                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1         4113                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2729                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore           57                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples         6842                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean   198.333821                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  1594.183488                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-4095         6730     98.36%     98.36% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::4096-8191           59      0.86%     99.23% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::8192-12287           21      0.31%     99.53% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::12288-16383           14      0.20%     99.74% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::16384-20479            7      0.10%     99.84% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::20480-24575            5      0.07%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::24576-28671            4      0.06%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::28672-32767            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-36863            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         6842                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         1221                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 10738.329238                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean  9530.760976                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  5854.425690                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-4095           35      2.87%      2.87% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191          374     30.63%     33.50% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287          497     40.70%     74.20% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383          243     19.90%     94.10% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479            3      0.25%     94.35% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575            9      0.74%     95.09% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671           37      3.03%     98.12% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767           16      1.31%     99.43% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::36864-40959            2      0.16%     99.59% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-45055            3      0.25%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::45056-49151            1      0.08%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::53248-57343            1      0.08%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         1221                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  11897679120                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.980675                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.137806                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0      230157764      1.93%      1.93% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1    11667291856     98.06%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2         229500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  11897679120                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K          997     85.65%     85.65% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          167     14.35%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         1164                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         6842                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         6842                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         6899                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         6899                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1165                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1165                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         8007                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    10488200                       # ITB inst hits
-system.cpu1.itb.inst_misses                      6842                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1164                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1164                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         8063                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    43584522                       # ITB inst hits
+system.cpu1.itb.inst_misses                      6899                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1810,1035 +1795,1025 @@ system.cpu1.itb.flush_tlb                          66                       # Nu
 system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1196                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1193                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                      530                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                      547                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                10495042                       # ITB inst accesses
-system.cpu1.itb.hits                         10488200                       # DTB hits
-system.cpu1.itb.misses                           6842                       # DTB misses
-system.cpu1.itb.accesses                     10495042                       # DTB accesses
-system.cpu1.numCycles                        43023242                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                43591421                       # ITB inst accesses
+system.cpu1.itb.hits                         43584522                       # DTB hits
+system.cpu1.itb.misses                           6899                       # DTB misses
+system.cpu1.itb.accesses                     43591421                       # DTB accesses
+system.cpu1.numCycles                       105332010                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles           9545006                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      31536140                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    6152669                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           3495321                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     31308638                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                 988880                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                     91081                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               40105                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles       214294                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       338691                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles        30719                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 10487595                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               131638                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   2429                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples          42062974                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.911933                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.224898                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          10132151                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     108981973                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                   33870827                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          27429128                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     92017725                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                3770452                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                     88186                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               36483                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles       195284                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       298638                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles        22598                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                 43583923                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               117443                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   2417                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         104676291                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.289820                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.339564                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                24350235     57.89%     57.89% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                 6287044     14.95%     72.84% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                 2205515      5.24%     78.08% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 9220180     21.92%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                47827120     45.69%     45.69% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                14002469     13.38%     59.07% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 7529046      7.19%     66.26% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                35317656     33.74%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            42062974                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.143008                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.733002                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                 8267663                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             20626897                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                 11490517                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles              1337775                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                340122                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              874675                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               157334                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              30100708                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts              1379443                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles                340122                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                10041900                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                2603998                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      14921640                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                 11019721                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              3135593                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              28621166                       # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts               281517                       # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents               330506                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                 50454                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                 20125                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents               1923436                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands           29030542                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            132294985                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        32813170                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups             1657                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             25609862                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 3420680                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            453393                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts        375590                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  3438293                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             5562789                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            4719499                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           701110                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          705314                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  27634808                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             626900                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 27144127                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued           143701                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        2955966                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined      6891737                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved         53840                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     42062974                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.645321                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       0.965357                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           104676291                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.321563                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       1.034652                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                13137871                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             61997568                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                 26684640                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles              1104927                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               1751285                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              750757                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               136902                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              67935331                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts              1160131                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               1751285                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                17557644                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                2234457                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      57207184                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                 23346153                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              2579568                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              55040039                       # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts               231549                       # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents               250107                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                 36576                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                 14638                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents               1569614                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           54888875                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            259969011                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        58535420                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups             1673                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             52136282                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 2752593                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts           1876398                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts       1803595                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 13068910                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            10432997                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            6892596                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           625658                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          847753                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  54148527                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             587967                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 53807238                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued           110933                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        3881118                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined      5762517                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved         48708                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    104676291                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.514035                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       0.850765                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           26343154     62.63%     62.63% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            7337268     17.44%     80.07% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            5660550     13.46%     93.53% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            2402263      5.71%     99.24% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             319725      0.76%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5                 14      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           71469096     68.28%     68.28% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1           16529250     15.79%     84.07% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2           13041841     12.46%     96.53% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            3350126      3.20%     99.73% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             285962      0.27%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5                 16      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       42062974                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      104676291                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                1996325     32.40%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                   609      0.01%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     32.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               1885144     30.59%     63.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite              2280359     37.00%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                2912792     45.01%     45.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                   674      0.01%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     45.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               1671813     25.83%     70.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite              1886405     29.15%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass               67      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             17084879     62.94%     62.94% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               34880      0.13%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          4083      0.02%     63.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     63.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     63.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     63.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead             5473288     20.16%     83.25% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            4546930     16.75%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass               66      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             36660342     68.13%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               45736      0.08%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          3323      0.01%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            10366546     19.27%     87.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            6731225     12.51%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              27144127                       # Type of FU issued
-system.cpu1.iq.rate                          0.630918                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    6162437                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.227027                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         102651570                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         31226183                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     26510239                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads               5796                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              2046                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         1784                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              33302783                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   3714                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          106694                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              53807238                       # Type of FU issued
+system.cpu1.iq.rate                          0.510835                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    6471684                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.120275                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         218867204                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         58625584                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     51813824                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads               6180                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              2068                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         1785                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              60274803                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   4053                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads           90118                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       599497                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses          782                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        10594                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       400513                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       483730                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses          680                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation        10069                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       351136                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads        46755                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        99859                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads        51537                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        78201                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                340122                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                 663664                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               112730                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           28316728                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles               1751285                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                 538520                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               104583                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           54788620                       # Number of instructions dispatched to IQ
 system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              5562789                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             4719499                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            329074                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 12650                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents                90576                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         10594                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         71921                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       150578                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              222499                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             26808358                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts              5342958                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           311471                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts             10432997                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             6892596                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            301008                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                  9394                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents                87795                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents         10069                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         55171                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       126265                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              181436                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             53538867                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             10265396                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           247288                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                        55020                       # number of nop insts executed
-system.cpu1.iew.exec_refs                     9813397                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 4108906                       # Number of branches executed
-system.cpu1.iew.exec_stores                   4470439                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.623113                       # Inst execution rate
-system.cpu1.iew.wb_sent                      26632744                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     26512023                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 13415515                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 21195279                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                        52126                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    16932944                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                11793778                       # Number of branches executed
+system.cpu1.iew.exec_stores                   6667548                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.508287                       # Inst execution rate
+system.cpu1.iew.wb_sent                      53390597                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     51815609                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 25160275                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 38370093                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.616226                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.632948                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.491927                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.655726                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts        2659330                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         573060                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           205791                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples     41503303                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.610529                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.356545                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts        3631838                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         539259                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           169982                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    102749355                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.495266                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.156980                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     29410485     70.86%     70.86% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      7042051     16.97%     87.83% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      2116509      5.10%     92.93% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       864843      2.08%     95.01% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       769424      1.85%     96.87% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       435639      1.05%     97.92% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       276731      0.67%     98.58% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       147889      0.36%     98.94% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       439732      1.06%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     77230128     75.16%     75.16% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1     14246960     13.87%     89.03% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      6071957      5.91%     94.94% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       703815      0.68%     95.62% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4      1976351      1.92%     97.55% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      1539288      1.50%     99.05% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       468880      0.46%     99.50% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       125021      0.12%     99.62% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       386955      0.38%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total     41503303                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            20778200                       # Number of instructions committed
-system.cpu1.commit.committedOps              25338954                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    102749355                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            41322014                       # Number of instructions committed
+system.cpu1.commit.committedOps              50888230                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                       9282278                       # Number of memory references committed
-system.cpu1.commit.loads                      4963292                       # Number of loads committed
-system.cpu1.commit.membars                     229830                       # Number of memory barriers committed
-system.cpu1.commit.branches                   3902679                       # Number of branches committed
+system.cpu1.commit.refs                      16490727                       # Number of memory references committed
+system.cpu1.commit.loads                      9949267                       # Number of loads committed
+system.cpu1.commit.membars                     209363                       # Number of memory barriers committed
+system.cpu1.commit.branches                  11627773                       # Number of branches committed
 system.cpu1.commit.fp_insts                      1784                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 22267919                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              549742                       # Number of function calls committed.
+system.cpu1.commit.int_insts                 45743033                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls             3362907                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu        16018762     63.22%     63.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          33831      0.13%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc         4083      0.02%     63.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     63.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     63.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     63.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead        4963292     19.59%     82.96% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite       4318986     17.04%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        34349326     67.50%     67.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          44854      0.09%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc         3323      0.01%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        9949267     19.55%     87.15% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       6541460     12.85%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         25338954                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events               439732                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                    67911551                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   56552827                       # The number of ROB writes
-system.cpu1.timesIdled                          67532                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                         960268                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  5207215501                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   20744987                       # Number of Instructions Simulated
-system.cpu1.committedOps                     25305741                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              2.073910                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        2.073910                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.482181                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.482181                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                29917814                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               16874088                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                     1382                       # number of floating regfile reads
+system.cpu1.commit.op_class_0::total         50888230                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events               386955                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                   136861200                       # The number of ROB reads
+system.cpu1.rob.rob_writes                  110963404                       # The number of ROB writes
+system.cpu1.timesIdled                          59136                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                         655719                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  5544933026                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   41289159                       # Number of Instructions Simulated
+system.cpu1.committedOps                     50855375                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              2.551082                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        2.551082                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.391991                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.391991                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                56164709                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               35664798                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                     1398                       # number of floating regfile reads
 system.cpu1.fp_regfile_writes                     516                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                 95785070                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes                 9455596                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads               60806398                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                422782                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements           228231                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          478.409113                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            8403253                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           228545                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            36.768483                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     103444079500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   478.409113                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.934393                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.934393                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          314                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          282                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3           32                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.613281                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         18586968                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        18586968                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      4548259                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        4548259                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      3563356                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       3563356                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        63759                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        63759                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        87271                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        87271                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        79516                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        79516                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      8111615                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         8111615                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      8175374                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        8175374                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       254647                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       254647                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       480567                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       480567                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        35928                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        35928                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        19211                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        19211                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23462                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23462                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       735214                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        735214                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       771142                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       771142                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   4017153000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   4017153000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  11025282924                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  11025282924                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    376163500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    376163500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    545526500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    545526500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       528500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total       528500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  15042435924                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  15042435924                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  15042435924                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  15042435924                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      4802906                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      4802906                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      4043923                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      4043923                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        99687                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total        99687                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       106482                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total       106482                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       102978                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total       102978                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      8846829                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      8846829                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      8946516                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      8946516                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.053019                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.053019                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.118837                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.118837                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.360408                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.360408                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.180415                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.180415                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.227835                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.227835                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.083105                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.083105                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.086195                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.086195                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15775.379250                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15775.379250                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22942.238905                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 22942.238905                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19580.630889                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19580.630889                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23251.491774                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23251.491774                       # average StoreCondReq miss latency
+system.cpu1.cc_regfile_reads                190801964                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes                15538939                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads              145958777                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                388038                       # number of misc regfile writes
+system.cpu1.dcache.tags.replacements           188683                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          469.137779                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs           15712566                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           189037                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            83.118998                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      93446032500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   469.137779                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.916285                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.916285                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          354                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          342                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           12                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.691406                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         32914145                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        32914145                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      9558582                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        9558582                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      5897409                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       5897409                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        49196                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        49196                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        78850                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        78850                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        70461                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        70461                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     15455991                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        15455991                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     15505187                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       15505187                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       218229                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       218229                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       396239                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       396239                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        29850                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        29850                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        18125                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        18125                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23674                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23674                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       614468                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        614468                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       644318                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       644318                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3487669000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   3487669000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   9663134455                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   9663134455                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    358154500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    358154500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    554726500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    554726500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       887500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total       887500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  13150803455                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  13150803455                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  13150803455                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  13150803455                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      9776811                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      9776811                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      6293648                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      6293648                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        79046                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        79046                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        96975                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        96975                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94135                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        94135                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     16070459                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     16070459                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     16149505                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     16149505                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.022321                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.022321                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.062959                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.062959                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.377628                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.377628                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.186904                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.186904                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.251490                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.251490                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.038236                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.038236                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.039897                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.039897                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15981.693542                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15981.693542                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24387.136185                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 24387.136185                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19760.248276                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19760.248276                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23431.887303                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23431.887303                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20459.942172                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 20459.942172                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19506.700354                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 19506.700354                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs          359                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets      1638919                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs               40                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets          49248                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     8.975000                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    33.278895                       # average number of cycles each access was blocked
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21401.933795                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 21401.933795                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20410.423820                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 20410.423820                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs          334                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets      1417697                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs               34                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets          39735                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs     9.823529                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    35.678797                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       137260                       # number of writebacks
-system.cpu1.dcache.writebacks::total           137260                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        91413                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        91413                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       375801                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       375801                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        13808                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        13808                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       467214                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       467214                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       467214                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       467214                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       163234                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       163234                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       104766                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       104766                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        32551                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        32551                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5403                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5403                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23462                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23462                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       268000                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       268000                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       300551                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       300551                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         5603                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total         5603                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         4908                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         4908                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        10511                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        10511                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2247760000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2247760000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2639771935                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2639771935                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    542309000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    542309000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    101732500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    101732500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    522075500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    522075500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       517500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       517500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4887531935                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   4887531935                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5429840935                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   5429840935                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    989470000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    989470000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    857954500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    857954500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1847424500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1847424500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033987                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.033987                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.025907                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.025907                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.326532                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.326532                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.050741                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.050741                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.227835                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.227835                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.030293                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.030293                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033594                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.033594                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13770.170430                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13770.170430                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25196.838049                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25196.838049                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16660.286934                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16660.286934                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18828.891357                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18828.891357                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22251.960617                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22251.960617                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       116769                       # number of writebacks
+system.cpu1.dcache.writebacks::total           116769                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        80049                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        80049                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       306072                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       306072                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        13108                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        13108                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       386121                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       386121                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       386121                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       386121                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       138180                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       138180                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        90167                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        90167                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        28614                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        28614                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5017                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5017                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23674                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23674                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       228347                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       228347                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       256961                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       256961                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        14486                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total        14486                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        11815                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total        11815                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        26301                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        26301                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1915104500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1915104500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2355138466                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2355138466                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    482351500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    482351500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     90011000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     90011000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    531068500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    531068500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       871500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       871500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4270242966                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4270242966                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4752594466                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   4752594466                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2349248500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2349248500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1864740000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   1864740000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   4213988500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   4213988500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.014133                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.014133                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014327                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.014327                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.361992                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.361992                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.051735                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.051735                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.251490                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.251490                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.014209                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.014209                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.015911                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.015911                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13859.491243                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13859.491243                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26119.738552                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26119.738552                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16857.185294                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16857.185294                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17941.199920                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17941.199920                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22432.563149                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22432.563149                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18237.059459                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18237.059459                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18066.288034                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18066.288034                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176596.466179                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176596.466179                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174807.355338                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 174807.355338                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 175761.059842                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 175761.059842                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18700.674701                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18700.674701                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18495.392165                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18495.392165                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162173.719453                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162173.719453                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157828.184511                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 157828.184511                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 160221.607543                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 160221.607543                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           661426                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          498.525577                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            9800007                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           661938                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            14.805023                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      78861824000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.525577                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973683                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.973683                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements           603214                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          499.475238                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           42957427                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           603726                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            71.153846                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      78885354000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.475238                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975538                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.975538                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          495                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          494                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           18                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         21636569                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        21636569                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst      9800007                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        9800007                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      9800007                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         9800007                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      9800007                       # number of overall hits
-system.cpu1.icache.overall_hits::total        9800007                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       687303                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       687303                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       687303                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        687303                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       687303                       # number of overall misses
-system.cpu1.icache.overall_misses::total       687303                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6263235013                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   6263235013                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   6263235013                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   6263235013                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   6263235013                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   6263235013                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     10487310                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     10487310                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     10487310                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     10487310                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     10487310                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     10487310                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.065537                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.065537                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.065537                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.065537                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.065537                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.065537                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9112.771242                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  9112.771242                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9112.771242                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  9112.771242                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9112.771242                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  9112.771242                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs       638996                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets          564                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs            53890                       # number of cycles access was blocked
+system.cpu1.icache.tags.tag_accesses         87771063                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        87771063                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     42957427                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       42957427                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     42957427                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        42957427                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     42957427                       # number of overall hits
+system.cpu1.icache.overall_hits::total       42957427                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       626240                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       626240                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       626240                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        626240                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       626240                       # number of overall misses
+system.cpu1.icache.overall_misses::total       626240                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5487739407                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   5487739407                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   5487739407                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   5487739407                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   5487739407                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   5487739407                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     43583667                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     43583667                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     43583667                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     43583667                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     43583667                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     43583667                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014369                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.014369                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014369                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.014369                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014369                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.014369                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8762.997265                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  8762.997265                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8762.997265                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  8762.997265                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8762.997265                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  8762.997265                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs       503899                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets           26                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs            46132                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              1                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    11.857413                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          564                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    10.922982                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets           26                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        25354                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total        25354                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst        25354                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total        25354                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst        25354                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total        25354                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       661949                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       661949                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       661949                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       661949                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       661949                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       661949                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        22511                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        22511                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        22511                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        22511                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        22511                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        22511                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       603729                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       603729                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       603729                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       603729                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       603729                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       603729                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          102                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          102                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          102                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          102                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5721508360                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   5721508360                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5721508360                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   5721508360                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5721508360                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   5721508360                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8594000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8594000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8594000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      8594000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.063119                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.063119                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.063119                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.063119                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.063119                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.063119                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8643.427757                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8643.427757                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8643.427757                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  8643.427757                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8643.427757                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  8643.427757                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84254.901961                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 84254.901961                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84254.901961                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 84254.901961                       # average overall mshr uncacheable latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5031797233                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   5031797233                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5031797233                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   5031797233                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5031797233                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   5031797233                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9110000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      9110000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      9110000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      9110000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.013852                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.013852                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.013852                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.013852                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.013852                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.013852                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8334.529620                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8334.529620                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8334.529620                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8334.529620                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8334.529620                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8334.529620                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89313.725490                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89313.725490                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89313.725490                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89313.725490                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued       269622                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified       270613                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit          884                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       189065                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       189671                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit          541                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage        67787                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements           66660                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15577.889137                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs           1655246                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           81265                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           20.368498                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage        56769                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements           48663                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15171.630527                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           1474911                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           63236                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           23.323914                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  6747.638156                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    12.637913                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.167789                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  4673.355619                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2625.058292                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1517.031368                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.411843                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000771                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000132                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.285239                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.160221                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.092592                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.950799                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1291                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           24                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13290                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2           17                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          868                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          406                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            8                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           12                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          470                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         8605                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         4215                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.078796                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001465                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.811157                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        30536660                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       30536660                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        19077                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         7323                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total         26400                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks       137259                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total       137259                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         2433                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total         2433                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data         1103                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total         1103                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        38090                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        38090                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       639615                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total       639615                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data       127678                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total       127678                       # number of ReadSharedReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        19077                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         7323                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       639615                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data       165768                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total         831783                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        19077                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         7323                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst       639615                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data       165768                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total        831783                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          431                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          286                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total          717                       # number of ReadReq misses
+system.cpu1.l2cache.tags.occ_blocks::writebacks  8232.224686                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    11.332834                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     3.684874                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3831.793838                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2451.411988                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   641.182307                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.502455                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000692                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000225                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.233874                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.149622                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.039135                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.926003                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1118                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           35                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13420                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2           21                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          930                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          167                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            7                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           10                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           18                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          468                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         8633                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         4319                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.068237                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002136                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.819092                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        27275895                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       27275895                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        15350                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         7200                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total         22550                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks       116768                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total       116768                       # number of Writeback hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1559                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total         1559                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data          954                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total          954                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data        27353                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total        27353                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       586865                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total       586865                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data       101704                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total       101704                       # number of ReadSharedReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        15350                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker         7200                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst       586865                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data       129057                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total         738472                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        15350                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker         7200                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst       586865                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data       129057                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total        738472                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          400                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          278                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total          678                       # number of ReadReq misses
 system.cpu1.l2cache.Writeback_misses::writebacks            1                       # number of Writeback misses
 system.cpu1.l2cache.Writeback_misses::total            1                       # number of Writeback misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29127                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        29127                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22358                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        22358                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            1                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        35752                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total        35752                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        22316                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total        22316                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        73485                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total        73485                       # number of ReadSharedReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          431                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker          286                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst        22316                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data       109237                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total       132270                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          431                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker          286                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst        22316                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data       109237                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total       132270                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      9445500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5864000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total     15309500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    555921000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total    555921000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    449033000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    449033000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       501000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       501000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1528833498                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   1528833498                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    894673000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total    894673000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1746677998                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1746677998                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      9445500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5864000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst    894673000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data   3275511496                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total   4185493996                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      9445500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5864000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst    894673000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data   3275511496                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total   4185493996                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        19508                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         7609                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total        27117                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks       137260                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total       137260                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        31560                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        31560                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23461                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        23461                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        73842                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total        73842                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       661931                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total       661931                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       201163                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total       201163                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        19508                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         7609                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst       661931                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data       275005                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total       964053                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        19508                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         7609                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst       661931                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data       275005                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total       964053                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.022094                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.037587                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.026441                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000007                       # miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_miss_rate::total     0.000007                       # miss rate for Writeback accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.922909                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.922909                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.952986                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.952986                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.484169                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.484169                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.033713                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.033713                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.365301                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.365301                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.022094                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.037587                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.033713                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.397218                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.137202                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.022094                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.037587                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.033713                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.397218                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.137202                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21915.313225                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20503.496503                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21352.161785                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19086.105675                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19086.105675                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20083.773146                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20083.773146                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       501000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       501000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42762.181081                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42762.181081                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40091.100556                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40091.100556                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23769.177356                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23769.177356                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21915.313225                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20503.496503                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40091.100556                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29985.366643                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 31643.562380                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21915.313225                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20503.496503                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40091.100556                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29985.366643                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 31643.562380                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs          124                       # number of cycles access was blocked
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28175                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total        28175                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22720                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total        22720                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data        33751                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total        33751                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        16862                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total        16862                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        70088                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total        70088                       # number of ReadSharedReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          400                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker          278                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst        16862                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data       103839                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total       121379                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          400                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker          278                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst        16862                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data       103839                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total       121379                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      8778500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5791500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total     14570000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    536726500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total    536726500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    459045500                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    459045500                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       847500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       847500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1378926000                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total   1378926000                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    607258000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total    607258000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1556092998                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1556092998                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      8778500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5791500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst    607258000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data   2935018998                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total   3556846998                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      8778500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5791500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst    607258000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data   2935018998                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total   3556846998                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        15750                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         7478                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total        23228                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks       116769                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total       116769                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29734                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total        29734                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23674                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total        23674                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        61104                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total        61104                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       603727                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total       603727                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       171792                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total       171792                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        15750                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         7478                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst       603727                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data       232896                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total       859851                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        15750                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         7478                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst       603727                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data       232896                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total       859851                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.025397                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.037176                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.029189                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000009                       # miss rate for Writeback accesses
+system.cpu1.l2cache.Writeback_miss_rate::total     0.000009                       # miss rate for Writeback accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.947568                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.947568                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.959703                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.959703                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.552353                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.552353                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.027930                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.027930                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.407982                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.407982                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.025397                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.037176                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.027930                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.445860                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.141163                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.025397                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.037176                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.027930                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.445860                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.141163                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21946.250000                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20832.733813                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21489.675516                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19049.742680                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19049.742680                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20204.467430                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20204.467430                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40855.856123                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40855.856123                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36013.402918                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36013.402918                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22201.988900                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22201.988900                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21946.250000                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20832.733813                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36013.402918                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28265.093058                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 29303.643942                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21946.250000                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20832.733813                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36013.402918                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28265.093058                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 29303.643942                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs          114                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               5                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    24.800000                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    22.800000                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        39050                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           39050                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker           13                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total           13                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          854                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total          854                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst           14                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total           14                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          144                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          144                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker           13                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst           14                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data          998                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total         1025                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker           13                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst           14                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data          998                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         1025                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          431                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          273                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total          704                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.writebacks::writebacks        30215                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           30215                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker           14                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::total           14                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          420                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total          420                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            6                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            6                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           76                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           76                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker           14                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            6                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data          496                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total          516                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker           14                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            6                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data          496                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total          516                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          400                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          264                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total          664                       # number of ReadReq MSHR misses
 system.cpu1.l2cache.Writeback_mshr_misses::writebacks            1                       # number of Writeback MSHR misses
 system.cpu1.l2cache.Writeback_mshr_misses::total            1                       # number of Writeback MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks         3034                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::total         3034                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        37433                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total        37433                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29127                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29127                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22358                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22358                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        34898                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        34898                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        22302                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        22302                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        73341                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        73341                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          431                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          273                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        22302                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data       108239                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total       131245                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          431                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          273                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        22302                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data       108239                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        37433                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total       168678                       # number of overall MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks         2169                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::total         2169                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        23681                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total        23681                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        28175                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28175                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22720                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22720                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        33331                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total        33331                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        16856                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        16856                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        70012                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        70012                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          400                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          264                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        16856                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data       103343                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total       120863                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          400                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          264                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        16856                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data       103343                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        23681                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total       144544                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          102                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         5603                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         5705                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         4908                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         4908                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        14486                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        14588                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        11815                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        11815                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          102                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        10511                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        10613                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      6859500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4063500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     10923000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1619868588                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1619868588                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    495927500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    495927500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    345361500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    345361500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       435000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       435000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1215520500                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1215520500                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    760109500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    760109500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1300287998                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1300287998                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      6859500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4063500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    760109500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2515808498                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   3286840998                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      6859500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4063500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    760109500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2515808498                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1619868588                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   4906709586                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7829000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    944359000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    952188000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    821025498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    821025498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7829000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1765384498                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1773213498                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.022094                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.035879                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.025962                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000007                       # mshr miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000007                       # mshr miss rate for Writeback accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        26301                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        26403                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      6378500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4031500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     10410000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1037990412                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1037990412                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    463119500                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    463119500                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    352921500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    352921500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       751500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       751500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1120597500                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1120597500                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    506014500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    506014500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1134157998                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1134157998                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      6378500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4031500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    506014500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2254755498                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   2771179998                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      6378500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4031500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    506014500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2254755498                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1037990412                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   3809170410                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8345000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2233165500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2241510500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1776007998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1776007998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8345000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   4009173498                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   4017518498                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.025397                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.035304                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.028586                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000009                       # mshr miss rate for Writeback accesses
+system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000009                       # mshr miss rate for Writeback accesses
 system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.922909                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.922909                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.952986                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.952986                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.472604                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.472604                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.033692                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.033692                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.364585                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.364585                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.022094                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.035879                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.033692                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.393589                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.136139                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.022094                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.035879                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.033692                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.393589                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.947568                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.947568                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.959703                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.959703                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.545480                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.545480                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.027920                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.027920                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.407539                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.407539                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.025397                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.035304                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.027920                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.443730                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.140563                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.025397                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.035304                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.027920                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.443730                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.174968                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15915.313225                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14884.615385                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15515.625000                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43273.811557                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43273.811557                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17026.384454                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17026.384454                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15446.887020                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15446.887020                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       435000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       435000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34830.663648                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34830.663648                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34082.571070                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34082.571070                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17729.346450                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17729.346450                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15915.313225                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14884.615385                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34082.571070                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23243.087039                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25043.552120                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15915.313225                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14884.615385                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34082.571070                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23243.087039                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43273.811557                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29089.208942                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 76754.901961                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168545.243619                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166904.119194                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167283.108802                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 167283.108802                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 76754.901961                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 167955.903149                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 167079.383586                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.168104                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15946.250000                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15270.833333                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15677.710843                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43832.203539                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43832.203539                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16437.249335                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16437.249335                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15533.516725                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15533.516725                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33620.278419                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33620.278419                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30019.844566                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30019.844566                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16199.480061                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16199.480061                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15946.250000                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15270.833333                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30019.844566                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21818.173442                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22928.274145                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15946.250000                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15270.833333                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30019.844566                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21818.173442                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43832.203539                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26353.016452                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81813.725490                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154160.258180                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 153654.407732                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150318.070080                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150318.070080                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81813.725490                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 152434.260979                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 152161.439912                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq         70770                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp       942311                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        31035                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         4908                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback       510267                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict       868505                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq        48336                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        75730                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        43006                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        89941                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadReq         67801                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp       858839                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        30901                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        11815                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback       481520                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict       790490                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        28803                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        75635                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        42021                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        86708                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           13                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        96740                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        79738                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq       661949                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq       536905                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           29                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        83417                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        65666                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq       603729                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       520017                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1973224                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       988189                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        17063                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        42721                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          3021197                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     42365216                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29405313                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        30436                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        78032                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          71878997                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    1156869                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      2994555                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       1.368102                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.482289                       # Request fanout histogram
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1799792                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       888351                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        17049                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        36002                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          2741194                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     38640160                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     25264094                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        29912                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        63000                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          63997166                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    1119232                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      2773999                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       1.384160                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.486396                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1           1892252     63.19%     63.19% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2           1102303     36.81%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1           1708339     61.58%     61.58% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2           1065660     38.42%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       2994555                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy    1102178989                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       2773999                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy     991762490                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     87567999                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     81878499                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy    993110829                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy    905763364                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    449674318                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    398007900                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      9464978                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy      9580481                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy     23224976                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy     20262978                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                31011                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               31011                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                31012                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               31012                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59421                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              59421                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56600                       # Packet count per connected master and slave (bytes)
@@ -2846,7 +2821,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          848                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2862,16 +2837,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       107912                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       107914                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72952                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total        72952                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  180864                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  180866                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71544                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          448                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2887,10 +2862,10 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       162793                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       162794                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321248                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2484041                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2484042                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy             40089000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
@@ -2901,7 +2876,7 @@ system.iobus.reqLayer3.occupancy                12000                       # La
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy               505000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
@@ -2935,19 +2910,19 @@ system.iobus.reqLayer27.occupancy           187554438                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            84715000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            84717000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36776000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36458                       # number of replacements
-system.iocache.tags.tagsinuse               14.446879                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse               14.557293                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36474                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         254837974000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.446879                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.902930                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.902930                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         254755320000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.557293                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.909831                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.909831                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -2961,14 +2936,14 @@ system.iocache.demand_misses::realview.ide          252                       #
 system.iocache.demand_misses::total               252                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          252                       # number of overall misses
 system.iocache.overall_misses::total              252                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     32277877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     32277877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4275018561                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4275018561                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     32277877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     32277877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     32277877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     32277877                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     32401877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     32401877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4274240561                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4274240561                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     32401877                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     32401877                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     32401877                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     32401877                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          252                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            252                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -2985,14 +2960,14 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 128086.813492                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 128086.813492                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118016.192607                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118016.192607                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 128086.813492                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 128086.813492                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 128086.813492                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 128086.813492                       # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 128578.876984                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 128578.876984                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117994.715134                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 117994.715134                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 128578.876984                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 128578.876984                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 128578.876984                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 128578.876984                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -3011,14 +2986,14 @@ system.iocache.demand_mshr_misses::realview.ide          252
 system.iocache.demand_mshr_misses::total          252                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          252                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          252                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     19677877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     19677877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2463818561                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2463818561                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     19677877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     19677877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     19677877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     19677877                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     19801877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     19801877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2463040561                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2463040561                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     19801877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     19801877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     19801877                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     19801877                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -3027,603 +3002,601 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78086.813492                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 78086.813492                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68016.192607                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68016.192607                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 78086.813492                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 78086.813492                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 78086.813492                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 78086.813492                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78578.876984                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 78578.876984                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67994.715134                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67994.715134                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 78578.876984                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 78578.876984                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 78578.876984                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 78578.876984                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   136014                       # number of replacements
-system.l2c.tags.tagsinuse                64041.678257                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     410908                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   200324                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.051217                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   130408                       # number of replacements
+system.l2c.tags.tagsinuse                64065.129893                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     410009                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   194847                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.104261                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   12985.002975                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    12.737581                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     3.016987                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     6471.116722                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     1893.814522                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32628.788989                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     7.896219                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker     1.746917                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3305.203826                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1817.254812                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  4915.098707                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.198135                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000194                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000046                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.098741                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.028897                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.497876                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000120                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.000027                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.050433                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.027729                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.074998                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.977198                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        30547                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023           27                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        33736                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          132                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         6158                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        24257                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           26                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           23                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          442                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5063                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        28206                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.466110                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000412                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.514771                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  5562101                       # Number of tag accesses
-system.l2c.tags.data_accesses                 5562101                       # Number of data accesses
-system.l2c.Writeback_hits::writebacks          232311                       # number of Writeback hits
-system.l2c.Writeback_hits::total               232311                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            2454                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             792                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                3246                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           247                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            65                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               312                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data             3756                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data             1862                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                 5618                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          184                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker           89                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst        33340                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data        45362                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        43171                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           54                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker           50                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst        17322                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data        11995                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         7539                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           159106                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker           184                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker            89                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst               33340                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data               49118                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher        43171                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker            54                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker            50                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst               17322                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               13857                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher         7539                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  164724                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker          184                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker           89                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst              33340                       # number of overall hits
-system.l2c.overall_hits::cpu0.data              49118                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher        43171                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker           54                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker           50                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst              17322                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              13857                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher         7539                       # number of overall hits
-system.l2c.overall_hits::total                 164724                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data          8230                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          3781                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             12011                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          840                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         1148                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1988                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          11269                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data           9058                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total              20327                       # number of ReadExReq misses
+system.l2c.tags.occ_blocks::writebacks   11642.697009                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    13.974901                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.090106                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     8094.672337                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2978.207969                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37076.471677                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     6.445472                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker     0.909924                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     1874.720720                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      683.354796                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1693.584982                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.177653                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000213                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.123515                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.045444                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.565742                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000098                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.000014                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.028606                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.010427                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.025842                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.977556                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        31097                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023           22                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        33320                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          200                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3         5745                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4        25152                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4           22                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          514                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         6128                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        26654                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.474503                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000336                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.508423                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  5488101                       # Number of tag accesses
+system.l2c.tags.data_accesses                 5488101                       # Number of data accesses
+system.l2c.Writeback_hits::writebacks          227912                       # number of Writeback hits
+system.l2c.Writeback_hits::total               227912                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data            2549                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             581                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                3130                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data           167                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data           166                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total               333                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data             3885                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data             1531                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total                 5416                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          182                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker           78                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst        36625                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data        47695                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        45738                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           45                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker           34                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst        14003                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data         9344                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         4694                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total           158438                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker           182                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker            78                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst               36625                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data               51580                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher        45738                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker            45                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker            34                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst               14003                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data               10875                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher         4694                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                  163854                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker          182                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker           78                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst              36625                       # number of overall hits
+system.l2c.overall_hits::cpu0.data              51580                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher        45738                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker           45                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker           34                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst              14003                       # number of overall hits
+system.l2c.overall_hits::cpu1.data              10875                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher         4694                       # number of overall hits
+system.l2c.overall_hits::total                 163854                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data          8869                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          2831                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             11700                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          686                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data         1243                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            1929                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          11279                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data           8332                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total              19611                       # number of ReadExReq misses
 system.l2c.ReadSharedReq_misses::cpu0.dtb.walker           25                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker            7                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        17264                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data         8071                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       130238                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker           10                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker            2                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst         4969                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data         2483                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher        10791                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         173860                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.itb.walker            3                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.inst        19189                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data         9101                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       131841                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.dtb.walker            9                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.itb.walker            1                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.inst         2845                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data         1165                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         6684                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         170863                       # number of ReadSharedReq misses
 system.l2c.demand_misses::cpu0.dtb.walker           25                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker            7                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             17264                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             19340                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       130238                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker           10                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              4969                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             11541                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher        10791                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                194187                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker            3                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             19189                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             20380                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.l2cache.prefetcher       131841                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker            9                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              2845                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data              9497                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.l2cache.prefetcher         6684                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                190474                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.dtb.walker           25                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker            7                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            17264                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            19340                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       130238                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker           10                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             4969                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            11541                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher        10791                       # number of overall misses
-system.l2c.overall_misses::total               194187                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data      7636500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      4088000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     11724500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1275500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data       739500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      2015000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   1086401000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data    758222000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   1844623000                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker      2203000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       699000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   1415731001                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data    721065000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  14450210544                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker       855000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker       165500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst    421639500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data    224776000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher   1455323289                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  18692667834                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker      2203000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker       699000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   1415731001                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   1807466000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  14450210544                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker       855000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker       165500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    421639500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data    982998000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   1455323289                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     20537290834                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker      2203000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker       699000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   1415731001                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   1807466000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  14450210544                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker       855000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker       165500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    421639500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data    982998000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   1455323289                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    20537290834                       # number of overall miss cycles
-system.l2c.Writeback_accesses::writebacks       232311                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           232311                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        10684                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         4573                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           15257                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data         1087                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data         1213                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          2300                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data        15025                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        10920                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total            25945                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          209                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           96                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst        50604                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data        53433                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       173409                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           64                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           52                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst        22291                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data        14478                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        18330                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total       332966                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker          209                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker           96                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst           50604                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data           68458                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       173409                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker           64                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker           52                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst           22291                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data           25398                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher        18330                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              358911                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker          209                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker           96                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst          50604                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data          68458                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       173409                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker           64                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker           52                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst          22291                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          25398                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher        18330                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             358911                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.770311                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.826810                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.787245                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.772769                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.946414                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.864348                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.750017                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.829487                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.783465                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.119617                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.072917                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.341159                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.151049                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.751045                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.156250                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.038462                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.222915                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.171502                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.588707                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.522155                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.119617                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.072917                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.341159                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.282509                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.751045                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.156250                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.038462                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.222915                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.454406                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.588707                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.541045                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.119617                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.072917                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.341159                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.282509                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.751045                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.156250                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.038462                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.222915                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.454406                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.588707                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.541045                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   927.885784                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1081.195451                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   976.146865                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1518.452381                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   644.163763                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  1013.581489                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 96406.158488                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83707.440936                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 90747.429527                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker        88120                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 99857.142857                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 82004.807750                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 89340.230455                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 110952.337597                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker        85500                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker        82750                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 84853.994768                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90525.976641                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 134864.543508                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 107515.632313                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        88120                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 99857.142857                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 82004.807750                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 93457.394002                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 110952.337597                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        85500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker        82750                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 84853.994768                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 85174.421627                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 134864.543508                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 105760.379603                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        88120                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 99857.142857                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 82004.807750                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 93457.394002                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 110952.337597                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        85500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker        82750                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 84853.994768                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 85174.421627                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 134864.543508                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 105760.379603                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs              1319                       # number of cycles access was blocked
+system.l2c.overall_misses::cpu0.itb.walker            3                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            19189                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            20380                       # number of overall misses
+system.l2c.overall_misses::cpu0.l2cache.prefetcher       131841                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker            9                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             2845                       # number of overall misses
+system.l2c.overall_misses::cpu1.data             9497                       # number of overall misses
+system.l2c.overall_misses::cpu1.l2cache.prefetcher         6684                       # number of overall misses
+system.l2c.overall_misses::total               190474                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data      8584000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data      2028000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     10612000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1081500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1017000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      2098500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   1148001500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data    689593000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   1837594500                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker      2446500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       248000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.inst   1585577501                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data    820774000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  14236289443                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker       820000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker       310000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst    240581000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data    107330500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher    936970593                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  17931347537                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker      2446500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker       248000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   1585577501                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   1968775500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  14236289443                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker       820000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker       310000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    240581000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data    796923500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    936970593                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     19768942037                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker      2446500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker       248000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   1585577501                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   1968775500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  14236289443                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker       820000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker       310000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    240581000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data    796923500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    936970593                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    19768942037                       # number of overall miss cycles
+system.l2c.Writeback_accesses::writebacks       227912                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           227912                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        11418                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         3412                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           14830                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          853                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data         1409                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          2262                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data        15164                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data         9863                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            25027                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          207                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           81                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst        55814                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data        56796                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       177579                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           54                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           35                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst        16848                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data        10509                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        11378                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       329301                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker          207                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker           81                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst           55814                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data           71960                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       177579                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker           54                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker           35                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst           16848                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           20372                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher        11378                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              354328                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker          207                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker           81                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst          55814                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data          71960                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       177579                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker           54                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker           35                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst          16848                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          20372                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher        11378                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             354328                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.776756                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.829719                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.788941                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.804220                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.882186                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.852785                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.743801                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.844773                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.783594                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.120773                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.037037                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.343803                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.160240                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.742436                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.166667                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.028571                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.168863                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.110857                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.587449                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.518866                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.120773                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.037037                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.343803                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.283213                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.742436                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.166667                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.028571                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.168863                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.466179                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.587449                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.537564                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.120773                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.037037                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.343803                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.283213                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.742436                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.166667                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.028571                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.168863                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.466179                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.587449                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.537564                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   967.865599                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   716.354645                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   907.008547                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1576.530612                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   818.181818                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  1087.869362                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 101782.205869                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82764.402304                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 93702.233440                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker        97860                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 82666.666667                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 82629.501329                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 90185.034612                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 107980.745314                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 91111.111111                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker       310000                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 84562.741652                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 92129.184549                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 140181.118043                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 104945.760855                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        97860                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82666.666667                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 82629.501329                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 96603.312071                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107980.745314                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 91111.111111                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker       310000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 84562.741652                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 83913.183110                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 140181.118043                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 103788.139258                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        97860                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82666.666667                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 82629.501329                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 96603.312071                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107980.745314                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 91111.111111                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker       310000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 84562.741652                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 83913.183110                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 140181.118043                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 103788.139258                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                       21                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     62.809524                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              104474                       # number of writebacks
-system.l2c.writebacks::total                   104474                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            5                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst           10                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total           15                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              5                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst             10                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 15                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             5                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst            10                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                15                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks         3557                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total         3557                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         8230                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         3781                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        12011                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          840                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1148                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1988                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        11269                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         9058                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         20327                       # number of ReadExReq MSHR misses
+system.l2c.writebacks::writebacks              100621                       # number of writebacks
+system.l2c.writebacks::total                   100621                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            3                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            9                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total           12                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              3                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst              9                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 12                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst             3                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst             9                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                12                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks         3122                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total         3122                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         8869                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         2831                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        11700                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          686                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1243                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1929                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        11279                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data         8332                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         19611                       # number of ReadExReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker           25                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            7                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        17259                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data         8071                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       130238                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker           10                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker            2                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         4959                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data         2483                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher        10791                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       173845                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            3                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        19186                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data         9101                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       131841                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker            9                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         2836                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data         1165                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         6684                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total       170851                       # number of ReadSharedReq MSHR misses
 system.l2c.demand_mshr_misses::cpu0.dtb.walker           25                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker            7                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        17259                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        19340                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       130238                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker           10                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         4959                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        11541                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher        10791                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           194172                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker            3                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        19186                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        20380                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       131841                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker            9                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         2836                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data         9497                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         6684                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           190462                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu0.dtb.walker           25                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker            7                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        17259                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        19340                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       130238                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker           10                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         4959                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        11541                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher        10791                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          194172                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker            3                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        19186                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        20380                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       131841                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker            9                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         2836                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data         9497                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         6684                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          190462                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3004                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        29394                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data        20386                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          102                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data         5600                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        38100                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        26127                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         4908                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        31035                       # number of WriteReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data        14482                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        37974                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        19086                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data        11815                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        30901                       # number of WriteReq MSHR uncacheable
 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3004                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        55521                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        39472                       # number of overall MSHR uncacheable misses
 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          102                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        10508                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        69135                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    170692500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     78410000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    249102500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     17547003                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     23836000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     41383003                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    973711000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    667642000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   1641353000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker      1953000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       629000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1242953501                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    640355000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  13147830544                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker       755000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker       145500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    371358500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    199946000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1347413289                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  16953339334                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      1953000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       629000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   1242953501                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   1614066000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  13147830544                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       755000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker       145500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    371358500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    867588000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher   1347413289                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  18594692334                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      1953000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       629000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   1242953501                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   1614066000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  13147830544                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       755000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker       145500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    371358500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    867588000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1347413289                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  18594692334                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        26297                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        68875                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    183870501                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     58746000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    242616501                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     14335002                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     25812000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     40147002                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   1035211500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    606273000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   1641484500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker      2196500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       218000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1393418001                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    729764000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  12917879443                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker       730000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker       300000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    211664500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data     95680500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    870130593                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  16221981537                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      2196500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       218000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   1393418001                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   1764975500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  12917879443                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       730000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker       300000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    211664500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    701953500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    870130593                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  17863466037                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      2196500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       218000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   1393418001                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   1764975500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  12917879443                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       730000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker       300000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    211664500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    701953500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    870130593                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  17863466037                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    189269500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4916712000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5992000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    843515500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   5955489000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   3669260542                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    737586502                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   4406847044                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3785154000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6508000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1972430500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   5953362000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2828697042                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1575146501                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   4403843543                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    189269500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   8585972542                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5992000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1581102002                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  10362336044                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   6613851042                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6508000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3547577001                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  10357205543                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.770311                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.826810                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.787245                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.772769                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.946414                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.864348                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.750017                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.829487                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.783465                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.119617                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.072917                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.341060                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.151049                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.751045                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.156250                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.038462                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.222466                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.171502                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.588707                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.522110                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.119617                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.072917                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.341060                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.282509                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.751045                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.156250                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.038462                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.222466                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.454406                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.588707                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.541003                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.119617                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.072917                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.341060                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.282509                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.751045                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.156250                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.038462                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.222466                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.454406                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.588707                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.541003                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20740.279465                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20737.900026                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20739.530430                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20889.289286                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20763.066202                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20816.399899                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 86406.158488                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73707.440936                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 80747.429527                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker        78120                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 89857.142857                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72017.700968                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79340.230455                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 100952.337597                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker        75500                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker        72750                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74885.763259                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80525.976641                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124864.543508                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 97519.855814                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        78120                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 89857.142857                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72017.700968                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83457.394002                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 100952.337597                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        75500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        72750                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74885.763259                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75174.421627                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124864.543508                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 95764.025369                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        78120                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 89857.142857                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72017.700968                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83457.394002                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 100952.337597                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        75500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        72750                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74885.763259                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75174.421627                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124864.543508                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 95764.025369                       # average overall mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.776756                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.829719                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.788941                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.804220                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.882186                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.852785                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.743801                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.844773                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.783594                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.120773                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.037037                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.343749                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.160240                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.742436                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.166667                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.028571                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.168329                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.110857                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.587449                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.518829                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.120773                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.037037                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.343749                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.283213                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.742436                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.166667                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.028571                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.168329                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.466179                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.587449                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.537530                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.120773                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.037037                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.343749                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.283213                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.742436                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.166667                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.028571                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.168329                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.466179                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.587449                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.537530                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20731.818807                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20750.971388                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20736.453077                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20896.504373                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20765.888978                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20812.339036                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 91782.205869                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72764.402304                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 83702.233440                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker        87860                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 72666.666667                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72626.811269                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80185.034612                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97980.745314                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 81111.111111                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker       300000                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74634.873061                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82129.184549                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130181.118043                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 94948.121679                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        87860                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72666.666667                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72626.811269                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 86603.312071                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97980.745314                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81111.111111                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker       300000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74634.873061                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73913.183110                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130181.118043                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 93790.184063                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        87860                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72666.666667                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72626.811269                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 86603.312071                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97980.745314                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81111.111111                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker       300000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74634.873061                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73913.183110                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130181.118043                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 93790.184063                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63005.825566                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167269.238620                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58745.098039                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150627.767857                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 156312.047244                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 140439.412944                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150282.498370                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141996.038150                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185674.188168                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63803.921569                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136198.763983                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 156774.687944                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148207.955674                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133317.520186                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142514.596388                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63005.825566                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 154643.694134                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58745.098039                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 150466.501903                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 149885.528951                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 167558.042207                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63803.921569                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 134904.247671                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 150376.849989                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               38100                       # Transaction distribution
-system.membus.trans_dist::ReadResp             212196                       # Transaction distribution
-system.membus.trans_dist::WriteReq              31035                       # Transaction distribution
-system.membus.trans_dist::WriteResp             31035                       # Transaction distribution
-system.membus.trans_dist::Writeback            140680                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            16716                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            77066                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          41581                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           14111                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             40212                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            20215                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        174097                       # Transaction distribution
+system.membus.trans_dist::ReadReq               37974                       # Transaction distribution
+system.membus.trans_dist::ReadResp             209076                       # Transaction distribution
+system.membus.trans_dist::WriteReq              30901                       # Transaction distribution
+system.membus.trans_dist::WriteResp             30901                       # Transaction distribution
+system.membus.trans_dist::Writeback            136827                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            16300                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            76178                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          40718                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           13724                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             39427                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            19516                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        171103                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107912                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107914                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           40                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14206                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       677829                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       799987                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13686                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       663947                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       785587                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108934                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       108934                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 908921                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162793                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total                 894521                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162794                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28412                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19154168                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     19345693                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27372                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18671220                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     18861706                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                21663837                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           125106                       # Total snoops (count)
-system.membus.snoop_fanout::samples            595969                       # Request fanout histogram
+system.membus.pkt_size::total                21179850                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           123655                       # Total snoops (count)
+system.membus.snoop_fanout::samples            585907                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  595969    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  585907    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              595969                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            81639500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              585907                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            81623000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               27500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            11797490                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            11432490                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1030129184                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           989982724                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1147298884                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1127040159                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64422049                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64467297                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -3656,50 +3629,50 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq              38103                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            495292                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             31035                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            31035                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           373006                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict           88968                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           80200                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         41893                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         122093                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           23                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            50895                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           50895                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       457205                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq              37978                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            489550                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             30901                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            30901                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           364752                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict           88216                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           79213                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         41051                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         120264                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           29                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           29                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            50507                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           50507                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       451588                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1082088                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       352339                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1434427                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     31351112                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6763093                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               38114205                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          462700                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          1239270                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.168619                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.374415                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1086474                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       331144                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1417618                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     32384412                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5153902                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               37538314                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          454329                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          1220605                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.166616                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.372633                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                1030306     83.14%     83.14% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 208964     16.86%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                1017233     83.34%     83.34% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 203372     16.66%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            1239270                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          822017005                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            1220605                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          824158889                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           355500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         615196241                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         620803562                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         261600624                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         245897316                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    2069                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                    1847                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2739                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                    2769                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
index d8bee446b4693870f7cbeb4e87261159c7af753f..3557587c207fb92ebabc3f48f4eca66d65b7272a 100644 (file)
@@ -4,11 +4,11 @@ sim_seconds                                  2.804297                       # Nu
 sim_ticks                                2804296829000                       # Number of ticks simulated
 final_tick                               2804296829000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 111214                       # Simulator instruction rate (inst/s)
-host_op_rate                                   134984                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2666624096                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 631592                       # Number of bytes of host memory used
-host_seconds                                  1051.63                       # Real time elapsed on the host
+host_inst_rate                                 103542                       # Simulator instruction rate (inst/s)
+host_op_rate                                   125673                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2482681694                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 631560                       # Number of bytes of host memory used
+host_seconds                                  1129.54                       # Real time elapsed on the host
 sim_insts                                   116955586                       # Number of instructions simulated
 sim_ops                                     141953418                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
index d3ad4a4536dae847ae6500cddf83eee28aa54ed3..0c25a081bb6980c3458af6005d19ca1d7099277b 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.482330                       # Number of seconds simulated
-sim_ticks                                47482329862000                       # Number of ticks simulated
-final_tick                               47482329862000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.411962                       # Number of seconds simulated
+sim_ticks                                47411962285000                       # Number of ticks simulated
+final_tick                               47411962285000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 176341                       # Simulator instruction rate (inst/s)
-host_op_rate                                   207374                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             9393535208                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 769764                       # Number of bytes of host memory used
-host_seconds                                  5054.79                       # Real time elapsed on the host
-sim_insts                                   891365561                       # Number of instructions simulated
-sim_ops                                    1048233259                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 170497                       # Simulator instruction rate (inst/s)
+host_op_rate                                   200546                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9509503550                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 769500                       # Number of bytes of host memory used
+host_seconds                                  4985.75                       # Real time elapsed on the host
+sim_insts                                   850056300                       # Number of instructions simulated
+sim_ops                                     999871495                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       124416                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       101184                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          8041216                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         40378184                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     15310528                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       143616                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       132928                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3236032                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         17140560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     13345792                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        446144                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             98400600                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      8041216                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3236032                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total        11277248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     78262528                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker        75328                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        71168                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          7498816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         38111304                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     10728384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker        51264                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        47808                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2878784                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         12174608                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher      7747264                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        431104                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             79815832                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      7498816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2878784                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total        10377600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     62807296                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          78283112                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1944                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1581                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst            125644                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            630922                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       239227                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2244                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2077                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             50563                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            267834                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       208528                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6971                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1537535                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1222852                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          62827880                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1177                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1112                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst            117169                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            595502                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       167631                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker          801                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker          747                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             44981                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            190241                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       121051                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6736                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1247148                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          981364                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1225426                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2620                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2131                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              169352                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              850383                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       322447                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          3025                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          2800                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               68152                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              360988                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       281069                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9396                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2072363                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         169352                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          68152                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             237504                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1648245                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data                433                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               983938                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          1589                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          1501                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              158163                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              803833                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       226280                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          1081                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          1008                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               60719                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              256783                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       163403                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9093                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1683453                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         158163                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          60719                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             218881                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1324714                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1648679                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1648245                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2620                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2131                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             169352                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             850817                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       322447                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         3025                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         2800                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              68152                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             360988                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       281069                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            9396                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3721041                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1537535                       # Number of read requests accepted
-system.physmem.writeReqs                      1225426                       # Number of write requests accepted
-system.physmem.readBursts                     1537535                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1225426                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 98362112                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     40128                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  78282112                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  98400600                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               78283112                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      627                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total                1325148                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1324714                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         1589                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         1501                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             158163                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             804267                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       226280                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         1081                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         1008                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              60719                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             256784                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       163403                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9093                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3008602                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1247148                       # Number of read requests accepted
+system.physmem.writeReqs                       983938                       # Number of write requests accepted
+system.physmem.readBursts                     1247148                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     983938                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 79775360                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     42112                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  62826240                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  79815832                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               62827880                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      658                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         220170                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               94941                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               98803                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               90365                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              103122                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               90513                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              102407                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               86370                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               97727                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               90531                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              141203                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              86748                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              95428                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              92596                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              93840                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              85305                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              87009                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               77173                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               80360                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               74652                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               83758                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               75004                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               81344                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               71841                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               79366                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               74851                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               75375                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              73319                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              78054                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              76445                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              77751                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              70793                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              73072                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         218244                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               71187                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               77028                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               72273                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               78219                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               70385                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               81119                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               72267                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               76746                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               71370                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              123762                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              72044                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              80747                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              73100                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              79351                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              74612                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              72280                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               58860                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               62909                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               59749                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               64358                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               59245                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               66477                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               59553                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               62082                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               58790                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               60994                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              60508                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              63849                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              60193                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              63756                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              60310                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              60027                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          43                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47482327991500                       # Total gap between requests
+system.physmem.numWrRetry                          30                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47411960356500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1537505                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1247118                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1222852                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    944383                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    373776                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     49487                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     34651                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     29546                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     27146                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     25089                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     22356                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     19759                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      4466                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1975                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     1145                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      863                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      650                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      440                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      379                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      337                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      283                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      110                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       61                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 981364                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    795503                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    313068                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     30154                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     22514                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                     19326                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                     17861                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                     16010                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     13834                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     11987                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      2659                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     1157                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      695                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      515                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      367                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      206                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      171                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      146                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      131                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       98                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       69                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       10                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
@@ -188,164 +188,150 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    17449                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    20135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    44686                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    57274                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    64486                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    68059                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    69963                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    74225                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    75616                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    79113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    78742                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    81088                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    80039                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    81169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    88387                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    80912                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    76308                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    72380                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1847                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1076                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      779                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      575                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      452                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      472                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      442                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      426                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      351                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      352                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      393                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      360                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      419                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      384                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      350                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      311                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      317                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      378                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      306                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      292                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      248                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      337                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      250                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       68                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      122                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       940608                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      187.797442                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     115.260175                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     246.189901                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         561167     59.66%     59.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       186793     19.86%     79.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        62478      6.64%     86.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        31194      3.32%     89.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        21090      2.24%     91.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        13303      1.41%     93.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        10059      1.07%     94.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023        10062      1.07%     95.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        44462      4.73%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         940608                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         69828                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        22.009810                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      322.555489                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095          69825    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    14920                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    17590                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    38389                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    48185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    52683                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    54849                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    56160                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    59815                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    60639                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    63775                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    62891                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    64447                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    62663                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    63620                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    68672                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    63414                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    59849                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    57038                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1401                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      972                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      930                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      645                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      537                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      549                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      489                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      454                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      550                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      413                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      377                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      350                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      279                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      406                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      433                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      383                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      292                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      288                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      333                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      315                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      273                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      211                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      286                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      168                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       86                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       737647                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      193.317834                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     117.156586                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     253.851861                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         435526     59.04%     59.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       146539     19.87%     78.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        49058      6.65%     85.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        25178      3.41%     88.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        15871      2.15%     91.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        10341      1.40%     92.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         7959      1.08%     93.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         8404      1.14%     94.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        38771      5.26%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         737647                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         55115                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        22.615186                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      363.032286                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095          55112     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::24576-28671            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::77824-81919            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           69828                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         69828                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.516727                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.040521                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        6.611414                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           66194     94.80%     94.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            1213      1.74%     96.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             484      0.69%     97.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             227      0.33%     97.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             283      0.41%     97.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             499      0.71%     98.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             107      0.15%     98.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              41      0.06%     98.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              40      0.06%     98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              28      0.04%     98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              48      0.07%     99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              19      0.03%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             437      0.63%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              36      0.05%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              59      0.08%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              38      0.05%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              18      0.03%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               2      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             4      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            30      0.04%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             4      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-203             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-219             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           69828                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    47438420321                       # Total ticks spent queuing
-system.physmem.totMemAccLat               76255445321                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   7684540000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       30866.14                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           55115                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         55115                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.811122                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.212895                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        7.489514                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23           52725     95.66%     95.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31             682      1.24%     96.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             764      1.39%     98.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47             154      0.28%     98.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55              76      0.14%     98.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              61      0.11%     98.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71             472      0.86%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79             111      0.20%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              10      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95               1      0.00%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103              8      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119             1      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             1      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135            31      0.06%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143             2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151             7      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             4      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             3      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           55115                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    32865022462                       # Total ticks spent queuing
+system.physmem.totMemAccLat               56236709962                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   6232450000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       26366.05                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  49616.14                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.07                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.65                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.07                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.65                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  45116.05                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.68                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.33                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.68                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.33                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.49                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1237162                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    582295                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.50                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  47.61                       # Row buffer hit rate for writes
-system.physmem.avgGap                     17185305.18                       # Average gap between requests
-system.physmem.pageHitRate                      65.92                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 3664415160                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1999432875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                5961079800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4040267040                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3101314831680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1200459376170                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27436362274500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31753801677225                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.749891                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45642197013620                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1585539280000                       # Time in different power states
+system.physmem.avgWrQLen                        23.59                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1009662                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    480836                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.00                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  48.98                       # Row buffer hit rate for writes
+system.physmem.avgGap                     21250619.81                       # Average gap between requests
+system.physmem.pageHitRate                      66.89                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2808479520                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1532404500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4673861400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3196149840                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3096718466400                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1173181763970                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27418066728000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31700177853630                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.611477                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45611956984095                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1583189400000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    254592941380                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    216810169905                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 3446581320                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1880575125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                6026748000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3885796800                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3101314831680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1189099091205                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27446327436750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31751981060880                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.711548                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45658799171891                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1585539280000                       # Time in different power states
+system.physmem_1.actEnergy                 2768124240                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1510385250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                5048596800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3165006960                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3096718466400                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1175060323800                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27416418868500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31700689771950                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.622274                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45609169557313                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1583189400000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    237989586859                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    219597434187                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -376,18 +362,18 @@ system.realview.nvmem.bw_total::total              28                       # To
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              132987745                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         94268605                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          6098049                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups           100013530                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               72636793                       # Number of BTB hits
+system.cf0.dma_write_full_pages                  1671                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                    6846976                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                         1674                       # Number of DMA write transactions.
+system.cpu0.branchPred.lookups              130279608                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         91518189                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          6235368                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            97695080                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               70156250                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            72.626967                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               15695407                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect           1093856                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            71.811446                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               15568853                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect           1041049                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -418,66 +404,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   275636                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               275636                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         8285                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        76005                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples       275636                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0         275636    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       275636                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        84290                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 20584.826195                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 18820.617576                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 14196.942212                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-32767        79742     94.60%     94.60% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-65535         3631      4.31%     98.91% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-98303          417      0.49%     99.41% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-131071          355      0.42%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-163839           30      0.04%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::163840-196607           13      0.02%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-229375           32      0.04%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::229376-262143            8      0.01%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-294911           18      0.02%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::294912-327679           24      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-360447           12      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::360448-393215            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        84290                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks                   272738                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               272738                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         8357                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        77299                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples       272738                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0         272738    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       272738                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        85656                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 20319.907537                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 18687.643521                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 12933.686898                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535        84887     99.10%     99.10% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071          657      0.77%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607           28      0.03%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143           42      0.05%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679           27      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215           12      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        85656                       # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walksPending::samples    669754704                       # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::0      669754704    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::total    669754704                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        76005     90.17%     90.17% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M         8285      9.83%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total        84290                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       275636                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K        77299     90.24%     90.24% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M         8357      9.76%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        85656                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       272738                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       275636                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        84290                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       272738                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        85656                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        84290                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       359926                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        85656                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       358394                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    84907220                       # DTB read hits
-system.cpu0.dtb.read_misses                    227423                       # DTB read misses
-system.cpu0.dtb.write_hits                   75575788                       # DTB write hits
-system.cpu0.dtb.write_misses                    48213                       # DTB write misses
+system.cpu0.dtb.read_hits                    83911764                       # DTB read hits
+system.cpu0.dtb.read_misses                    226051                       # DTB read misses
+system.cpu0.dtb.write_hits                   74892635                       # DTB write hits
+system.cpu0.dtb.write_misses                    46687                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              41950                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1046                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   35105                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1851                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  8962                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              38178                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1015                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   35474                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1932                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  8858                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    10953                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                85134643                       # DTB read accesses
-system.cpu0.dtb.write_accesses               75624001                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    11487                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                84137815                       # DTB read accesses
+system.cpu0.dtb.write_accesses               74939322                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        160483008                       # DTB hits
-system.cpu0.dtb.misses                         275636                       # DTB misses
-system.cpu0.dtb.accesses                    160758644                       # DTB accesses
+system.cpu0.dtb.hits                        158804399                       # DTB hits
+system.cpu0.dtb.misses                         272738                       # DTB misses
+system.cpu0.dtb.accesses                    159077137                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -507,193 +488,190 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    64906                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                64906                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2          453                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        52493                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples        64906                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          64906    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        64906                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        52946                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 23323.187776                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 21129.664435                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 16367.746814                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-32767        48035     90.72%     90.72% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-65535         3919      7.40%     98.13% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-98303          305      0.58%     98.70% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::98304-131071          573      1.08%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-163839           22      0.04%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::163840-196607           23      0.04%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-229375           32      0.06%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::229376-262143           10      0.02%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-294911           11      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::294912-327679            7      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-360447            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::360448-393215            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        52946                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                    68078                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                68078                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2          722                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        61066                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples        68078                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          68078    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        68078                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        61788                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 22737.489480                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 21008.732396                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 13692.086470                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767        57025     92.29%     92.29% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535         3907      6.32%     98.61% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-98303          284      0.46%     99.07% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-131071          503      0.81%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839           12      0.02%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-196607            9      0.01%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-229375           25      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::229376-262143            7      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911            3      0.00%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-360447            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::360448-393215            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        61788                       # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walksPending::samples    669040204                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::0      669040204    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::total    669040204                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        52493     99.14%     99.14% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M          453      0.86%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        52946                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K        61066     98.83%     98.83% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M          722      1.17%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        61788                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        64906                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        64906                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        68078                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        68078                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        52946                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        52946                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       117852                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   238223958                       # ITB inst hits
-system.cpu0.itb.inst_misses                     64906                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        61788                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        61788                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       129866                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   232943519                       # ITB inst hits
+system.cpu0.itb.inst_misses                     68078                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              41950                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1046                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   24846                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              38178                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1015                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   25164                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   205008                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   198596                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               238288864                       # ITB inst accesses
-system.cpu0.itb.hits                        238223958                       # DTB hits
-system.cpu0.itb.misses                          64906                       # DTB misses
-system.cpu0.itb.accesses                    238288864                       # DTB accesses
-system.cpu0.numCycles                       971262699                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               233011597                       # ITB inst accesses
+system.cpu0.itb.hits                        232943519                       # DTB hits
+system.cpu0.itb.misses                          68078                       # DTB misses
+system.cpu0.itb.accesses                    233011597                       # DTB accesses
+system.cpu0.numCycles                       944358949                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  437915417                       # Number of instructions committed
-system.cpu0.committedOps                    515248827                       # Number of ops (including micro ops) committed
-system.cpu0.discardedOps                     45685554                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends                     4508                       # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles                 93994129820                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi                              2.217923                       # CPI: cycles per instruction
-system.cpu0.ipc                              0.450872                       # IPC: instructions per cycle
+system.cpu0.committedInsts                  433389926                       # Number of instructions committed
+system.cpu0.committedOps                    509312382                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                     43329563                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                     4813                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                 93880363578                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                              2.179005                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.458925                       # IPC: instructions per cycle
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   13434                       # number of quiesce instructions executed
-system.cpu0.tickCycles                      710739035                       # Number of cycles that the object actually ticked
-system.cpu0.idleCycles                      260523664                       # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements          5570429                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          501.849943                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          152007137                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          5570934                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            27.285754                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       4974167000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   501.849943                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.980176                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.980176                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          505                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           13                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          361                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          131                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.986328                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        323765599                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       323765599                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     77611950                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       77611950                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     69963904                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      69963904                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       263445                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       263445                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       169638                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       169638                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1758419                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1758419                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1721710                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1721710                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    147575854                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       147575854                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    147839299                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      147839299                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      3380647                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      3380647                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      2384184                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      2384184                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       670394                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       670394                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       781336                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total       781336                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       154783                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       154783                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       189820                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       189820                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      5764831                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       5764831                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      6435225                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      6435225                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  51653726500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  51653726500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  46144722000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  46144722000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  52344211500                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  52344211500                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2307846500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   2307846500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   3989603000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   3989603000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      3214000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      3214000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  97798448500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  97798448500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  97798448500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  97798448500                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     80992597                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     80992597                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     72348088                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     72348088                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       933839                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       933839                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       950974                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total       950974                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1913202                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      1913202                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1911530                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      1911530                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    153340685                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    153340685                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    154274524                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    154274524                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.041740                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.041740                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.032954                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.032954                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.717890                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.717890                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.821617                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.821617                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.080903                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.080903                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.099303                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.099303                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.037595                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.037595                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.041713                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.041713                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15279.242849                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15279.242849                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19354.513746                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 19354.513746                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 66993.216107                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 66993.216107                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14910.206547                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14910.206547                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21017.822147                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21017.822147                       # average StoreCondReq miss latency
+system.cpu0.kern.inst.quiesce                   13422                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      695520331                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                      248838618                       # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements          5405789                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          500.914885                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          150600436                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          5406301                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            27.856465                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       4974406000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   500.914885                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.978349                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.978349                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          405                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           32                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses        320300004                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       320300004                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     77010804                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       77010804                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     69515704                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      69515704                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       254236                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       254236                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       165535                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       165535                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1598340                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1598340                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1577518                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1577518                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    146526508                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       146526508                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    146780744                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      146780744                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      3243116                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      3243116                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      2266198                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      2266198                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       618205                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       618205                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       821296                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       821296                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       155401                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       155401                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       174722                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       174722                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      5509314                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       5509314                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      6127519                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      6127519                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  48375468500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  48375468500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  42499797000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  42499797000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  51670537000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  51670537000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2317304500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   2317304500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   3678685500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   3678685500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2406500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2406500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  90875265500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  90875265500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  90875265500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  90875265500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     80253920                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     80253920                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     71781902                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     71781902                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       872441                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       872441                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       986831                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total       986831                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1753741                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      1753741                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1752240                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      1752240                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    152035822                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    152035822                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    152908263                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    152908263                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.040411                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.040411                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.031571                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.031571                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.708592                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.708592                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.832256                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.832256                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.088611                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.088611                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.099714                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.099714                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.036237                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.036237                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.040073                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.040073                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14916.354672                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14916.354672                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18753.788063                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 18753.788063                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 62913.416113                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 62913.416113                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14911.773412                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14911.773412                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21054.506588                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21054.506588                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16964.668782                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 16964.668782                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15197.362718                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 15197.362718                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16494.842280                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 16494.842280                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14830.678697                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 14830.678697                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -702,161 +680,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      3773399                       # number of writebacks
-system.cpu0.dcache.writebacks::total          3773399                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       430069                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       430069                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       999795                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       999795                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data          103                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total          103                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        40774                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        40774                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           43                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::total           43                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1429864                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1429864                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1429864                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1429864                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2950578                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      2950578                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1384389                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1384389                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       664773                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       664773                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       781233                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       781233                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       114009                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       114009                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       189777                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       189777                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4334967                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4334967                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      4999740                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      4999740                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        32882                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        32882                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        32815                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        32815                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        65697                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        65697                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  40501320500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  40501320500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  25594559000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  25594559000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  15267286500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  15267286500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  51557242500                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  51557242500                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1530630500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1530630500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3798446000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3798446000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2841500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2841500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  66095879500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  66095879500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  81363166000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  81363166000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5911844500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5911844500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5682739500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5682739500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11594584000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11594584000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036430                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036430                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019135                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019135                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.711871                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.711871                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.821508                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.821508                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059591                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059591                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.099280                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.099280                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028270                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.028270                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032408                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032408                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13726.571709                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13726.571709                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18487.982063                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18487.982063                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22966.165142                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22966.165142                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 65994.706445                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 65994.706445                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13425.523424                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13425.523424                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20015.312709                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20015.312709                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      3720174                       # number of writebacks
+system.cpu0.dcache.writebacks::total          3720174                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       395501                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       395501                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       949612                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       949612                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data           96                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total           96                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        41791                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        41791                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           77                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::total           77                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1345113                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1345113                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1345113                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1345113                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2847615                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      2847615                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1316586                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1316586                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       612491                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       612491                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       821200                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       821200                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       113610                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       113610                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       174645                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       174645                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      4164201                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4164201                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      4776692                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      4776692                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        30167                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        30167                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        29885                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        29885                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60052                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60052                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  38218904500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  38218904500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  23577025500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  23577025500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13456556000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  13456556000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  50843266000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  50843266000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1513106500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1513106500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3501575000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3501575000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2054500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2054500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  61795930000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  61795930000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  75252486000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  75252486000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5426212000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5426212000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5134567500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5134567500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  10560779500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10560779500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.035483                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.035483                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018341                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018341                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.702043                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.702043                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.832159                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.832159                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064782                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064782                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.099670                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.099670                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027390                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.027390                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031239                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.031239                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13421.373500                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13421.373500                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17907.698775                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17907.698775                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21970.210175                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21970.210175                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 61913.377983                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 61913.377983                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13318.427075                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13318.427075                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20049.672192                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20049.672192                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15247.147095                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15247.147095                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16273.479421                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16273.479421                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179789.687367                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179789.687367                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173175.057139                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173175.057139                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 176485.745163                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176485.745163                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14839.804803                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14839.804803                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15754.100537                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15754.100537                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179872.443398                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179872.443398                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171810.858290                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171810.858290                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 175860.579165                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 175860.579165                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          9510825                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.926606                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          228501569                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          9511337                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            24.024127                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      29799763000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.926606                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999857                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999857                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          9471710                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.926461                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          223265309                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          9472222                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            23.570532                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      29829927000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.926461                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999856                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999856                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          431                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          346                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           62                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        485537176                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       485537176                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    228501569                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      228501569                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    228501569                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       228501569                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    228501569                       # number of overall hits
-system.cpu0.icache.overall_hits::total      228501569                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      9511346                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      9511346                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      9511346                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       9511346                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      9511346                       # number of overall misses
-system.cpu0.icache.overall_misses::total      9511346                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  94734195000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  94734195000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  94734195000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  94734195000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  94734195000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  94734195000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    238012915                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    238012915                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    238012915                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    238012915                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    238012915                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    238012915                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.039961                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.039961                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.039961                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.039961                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.039961                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.039961                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9960.124992                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9960.124992                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9960.124992                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  9960.124992                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9960.124992                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  9960.124992                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        474947313                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       474947313                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    223265309                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      223265309                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    223265309                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       223265309                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    223265309                       # number of overall hits
+system.cpu0.icache.overall_hits::total      223265309                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      9472232                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      9472232                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      9472232                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       9472232                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      9472232                       # number of overall misses
+system.cpu0.icache.overall_misses::total      9472232                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  93317915500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  93317915500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  93317915500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  93317915500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  93317915500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  93317915500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    232737541                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    232737541                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    232737541                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    232737541                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    232737541                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    232737541                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.040699                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.040699                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.040699                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.040699                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.040699                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.040699                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9851.734575                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9851.734575                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9851.734575                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9851.734575                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9851.734575                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9851.734575                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -865,252 +843,256 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      9511346                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      9511346                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      9511346                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      9511346                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      9511346                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      9511346                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      9472232                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      9472232                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      9472232                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      9472232                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      9472232                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      9472232                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        52292                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        52292                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        52292                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        52292                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  89978522000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  89978522000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  89978522000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  89978522000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  89978522000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  89978522000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  88581800000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  88581800000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  88581800000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  88581800000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  88581800000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  88581800000                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4777780500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   4777780500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   4777780500                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   4777780500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.039961                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.039961                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.039961                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.039961                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.039961                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.039961                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9460.124992                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9460.124992                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9460.124992                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  9460.124992                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9460.124992                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  9460.124992                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.040699                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.040699                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.040699                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.040699                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.040699                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.040699                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9351.734628                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9351.734628                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9351.734628                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  9351.734628                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9351.734628                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  9351.734628                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91367.331523                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91367.331523                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      7512189                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      7515615                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit         2942                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      7001248                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      7002240                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit          870                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       975521                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements         2798117                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16231.650842                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          26314432                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2814109                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            9.350893                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle     27335773000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  6405.405319                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    66.558250                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    59.359829                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  5460.175756                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3311.396146                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   928.755541                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.390955                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.004062                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003623                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.333263                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.202112                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.056687                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.990701                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1465                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           86                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14441                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          296                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          685                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          484                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            6                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           25                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           40                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           15                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          821                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4037                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5036                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         4531                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.089417                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005249                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.881409                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       507029075                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      507029075                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       480958                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       155860                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total        636818                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks      3773399                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total      3773399                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       109301                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total       109301                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        35296                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total        35296                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       877723                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       877723                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      8733791                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      8733791                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2708727                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total      2708727                       # number of ReadSharedReq hits
-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       190451                       # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total       190451                       # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       480958                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       155860                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      8733791                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      3586450                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total       12957059                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       480958                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       155860                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      8733791                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      3586450                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total      12957059                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        12195                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8813                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        21008                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       130468                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       130468                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       154478                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       154478                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            3                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            3                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       278567                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       278567                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       777554                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total       777554                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1020411                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total      1020411                       # number of ReadSharedReq misses
-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       589182                       # number of InvalidateReq misses
-system.cpu0.l2cache.InvalidateReq_misses::total       589182                       # number of InvalidateReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        12195                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8813                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       777554                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1298978                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total      2097540                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        12195                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8813                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       777554                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1298978                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      2097540                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    429581500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    328472000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total    758053500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2811659500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total   2811659500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3201796000                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3201796000                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2748498                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2748498                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  13465224999                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total  13465224999                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  23641079500                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total  23641079500                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  33953780489                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total  33953780489                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  49014503000                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::total  49014503000                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    429581500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    328472000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst  23641079500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data  47419005488                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total  71818138488                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    429581500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    328472000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst  23641079500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data  47419005488                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  71818138488                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       493153                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       164673                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total       657826                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks      3773399                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total      3773399                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       239769                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       239769                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       189774                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       189774                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1156290                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total      1156290                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      9511345                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      9511345                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3729138                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total      3729138                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       779633                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::total       779633                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       493153                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       164673                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      9511345                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data      4885428                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total     15054599                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       493153                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       164673                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      9511345                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data      4885428                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     15054599                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.024729                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.053518                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.031935                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.544140                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.544140                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.814010                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.814010                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.prefetcher.pfSpanPage       934040                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements         2602937                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16189.396586                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          26055882                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2619045                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            9.948619                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle     27364878000                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks  6164.786775                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    75.653187                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    79.660205                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  5461.877118                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3523.510222                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   883.909079                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.376269                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.004618                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.004862                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.333367                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.215058                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.053950                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.988122                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1484                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           72                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14552                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           26                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          652                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          737                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4           69                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           15                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           56                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1133                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5245                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7645                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          403                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.090576                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004395                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.888184                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       499794711                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      499794711                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       477670                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       164902                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total        642572                       # number of ReadReq hits
+system.cpu0.l2cache.Writeback_hits::writebacks      3720171                       # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total      3720171                       # number of Writeback hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       100086                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total       100086                       # number of UpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        33531                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::total        33531                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       842117                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       842117                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      8718803                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      8718803                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2638824                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total      2638824                       # number of ReadSharedReq hits
+system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       235281                       # number of InvalidateReq hits
+system.cpu0.l2cache.InvalidateReq_hits::total       235281                       # number of InvalidateReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       477670                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker       164902                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      8718803                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data      3480941                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total       12842316                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       477670                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker       164902                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      8718803                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data      3480941                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total      12842316                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        10606                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         7872                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total        18478                       # number of ReadReq misses
+system.cpu0.l2cache.Writeback_misses::writebacks            1                       # number of Writeback misses
+system.cpu0.l2cache.Writeback_misses::total            1                       # number of Writeback misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       123653                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total       123653                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       141112                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total       141112                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            2                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data       262527                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total       262527                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       753428                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total       753428                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       934617                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total       934617                       # number of ReadSharedReq misses
+system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       584428                       # number of InvalidateReq misses
+system.cpu0.l2cache.InvalidateReq_misses::total       584428                       # number of InvalidateReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        10606                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker         7872                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst       753428                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data      1197144                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total      1969050                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        10606                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker         7872                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst       753428                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data      1197144                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total      1969050                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    328744000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    264590000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total    593334000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2720179500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total   2720179500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   2942818999                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   2942818999                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1986000                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1986000                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  12019318999                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total  12019318999                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  22377694500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total  22377694500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  30534644990                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total  30534644990                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  47939774000                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::total  47939774000                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    328744000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    264590000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst  22377694500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data  42553963989                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total  65524992489                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    328744000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    264590000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  22377694500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data  42553963989                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  65524992489                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       488276                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       172774                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total       661050                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::writebacks      3720172                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total      3720172                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       223739                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total       223739                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       174643                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total       174643                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1104644                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total      1104644                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      9472231                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      9472231                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3573441                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total      3573441                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       819709                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::total       819709                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       488276                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       172774                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      9472231                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data      4678085                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total     14811366                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       488276                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       172774                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      9472231                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data      4678085                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total     14811366                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.021721                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.045562                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.027952                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000000                       # miss rate for Writeback accesses
+system.cpu0.l2cache.Writeback_miss_rate::total     0.000000                       # miss rate for Writeback accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.552666                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.552666                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.808003                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.808003                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.240914                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.240914                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.081750                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.081750                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.273632                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.273632                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.755717                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.755717                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.024729                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.053518                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.081750                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.265888                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.139329                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.024729                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.053518                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.081750                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.265888                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.139329                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35226.035260                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 37271.303756                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36084.039414                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21550.567955                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21550.567955                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20726.550059                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20726.550059                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       916166                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       916166                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48337.473567                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48337.473567                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 30404.421429                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 30404.421429                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 33274.612376                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 33274.612376                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 83190.767878                       # average InvalidateReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 83190.767878                       # average InvalidateReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35226.035260                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 37271.303756                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30404.421429                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36504.856501                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 34239.222369                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35226.035260                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 37271.303756                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30404.421429                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36504.856501                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 34239.222369                       # average overall miss latency
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.237658                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.237658                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.079541                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.079541                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.261545                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.261545                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.712970                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.712970                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.021721                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.045562                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.079541                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.255905                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.132942                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.021721                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.045562                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.079541                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.255905                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.132942                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30996.039977                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 33611.534553                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32110.293322                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21998.491747                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21998.491747                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20854.491461                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20854.491461                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       993000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       993000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 45783.172775                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45783.172775                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 29701.171844                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 29701.171844                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32670.757102                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32670.757102                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 82028.537305                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 82028.537305                       # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30996.039977                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 33611.534553                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29701.171844                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35546.236701                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 33277.465016                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30996.039977                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 33611.534553                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29701.171844                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35546.236701                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 33277.465016                       # average overall miss latency
 system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -1119,236 +1101,240 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1441697                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1441697                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            3                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total            3                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         8436                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         8436                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            8                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            8                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          865                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          865                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data           68                       # number of InvalidateReq MSHR hits
-system.cpu0.l2cache.InvalidateReq_mshr_hits::total           68                       # number of InvalidateReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            3                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            8                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         9301                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         9312                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            3                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            8                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         9301                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         9312                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        12195                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         8810                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        21005                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks       114790                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::total       114790                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       731294                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       731294                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       130468                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       130468                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       154478                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       154478                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            3                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       270131                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       270131                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       777546                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       777546                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1019546                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1019546                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       589114                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::total       589114                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        12195                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         8810                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       777546                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1289677                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total      2088228                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        12195                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         8810                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       777546                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1289677                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       731294                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total      2819522                       # number of overall MSHR misses
+system.cpu0.l2cache.writebacks::writebacks      1330364                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1330364                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            2                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::total            2                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5123                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         5123                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           12                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           12                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          628                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          628                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data            2                       # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::total            2                       # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            2                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           12                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         5751                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total         5765                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            2                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           12                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         5751                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total         5765                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        10606                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         7870                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total        18476                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.Writeback_mshr_misses::writebacks            1                       # number of Writeback MSHR misses
+system.cpu0.l2cache.Writeback_mshr_misses::total            1                       # number of Writeback MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks       106526                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::total       106526                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       667181                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       667181                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       123653                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total       123653                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       141112                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       141112                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       257404                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total       257404                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       753416                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       753416                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       933989                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       933989                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       584426                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::total       584426                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        10606                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         7870                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       753416                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1191393                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total      1963285                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        10606                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         7870                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       753416                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1191393                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       667181                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total      2630466                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        52292                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        32882                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        85174                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        32815                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        32815                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        30167                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        82459                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        29885                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        29885                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        52292                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        65697                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total       117989                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    356411500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    275560000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    631971500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  35755952523                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  35755952523                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2648670495                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2648670495                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2356042000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2356042000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2382498                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2382498                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  10796229999                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  10796229999                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  18975468000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  18975468000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  27752056489                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  27752056489                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  45478624000                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  45478624000                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    356411500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    275560000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  18975468000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  38548286488                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total  58155725988                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    356411500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    275560000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  18975468000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  38548286488                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  35755952523                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  93911678511                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60052                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total       112344                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    265108000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    217332000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    482440000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  24692938914                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  24692938914                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2507267996                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2507267996                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2173502999                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2173502999                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1716000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1716000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   9909956499                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   9909956499                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  17856881500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  17856881500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  24870500990                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  24870500990                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  44433114500                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  44433114500                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    265108000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    217332000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  17856881500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  34780457489                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total  53119778989                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    265108000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    217332000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  17856881500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  34780457489                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  24692938914                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  77812717903                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4359444500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5648614500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total  10008059000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5436600500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5436600500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5184743000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   9544187500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   4910404000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4910404000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   4359444500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11085215000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  15444659500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.024729                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.053500                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.031931                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  10095147000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  14454591500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.021721                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.045551                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.027949                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for Writeback accesses
+system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000000                       # mshr miss rate for Writeback accesses
 system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.544140                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.544140                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.814010                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.814010                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.552666                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.552666                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.808003                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.808003                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.233619                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.233619                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.081749                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.081749                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.273400                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.273400                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.755630                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.755630                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.024729                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.053500                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.081749                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.263984                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.138710                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.024729                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.053500                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.081749                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.263984                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.233020                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.233020                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.079539                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.079539                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.261370                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.261370                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.712968                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.712968                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.021721                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.045551                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.079539                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.254675                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.132553                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.021721                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.045551                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.079539                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.254675                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.187286                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30086.717448                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48894.087088                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48894.087088                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20301.303730                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20301.303730                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15251.634537                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15251.634537                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       794166                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       794166                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39966.645809                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39966.645809                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 24404.302768                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 24404.302768                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27220.014094                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27220.014094                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 77198.341917                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 77198.341917                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24404.302768                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29889.876681                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27849.318172                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24404.302768                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29889.876681                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48894.087088                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33307.659423                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.177598                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24996.039977                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27615.247776                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26111.712492                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37010.854497                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 37010.854497                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20276.645096                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20276.645096                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15402.680134                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15402.680134                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       858000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       858000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38499.621214                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38499.621214                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 23701.224158                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23701.224158                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26628.258994                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26628.258994                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 76028.640923                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 76028.640923                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24996.039977                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27615.247776                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23701.224158                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29193.102099                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27056.580674                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24996.039977                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27615.247776                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23701.224158                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29193.102099                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37010.854497                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 29581.343345                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171784.395718                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117501.338437                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165674.249581                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165674.249581                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171868.034607                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 115744.642792                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164309.988288                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164309.988288                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 168732.438315                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 130899.147378                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 168106.757477                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 128663.671402                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq        870203                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     14200168                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        38095                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        32815                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback      7469298                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict     14383795                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq      1113522                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       480939                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       348630                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       494804                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           46                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          104                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1552927                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1165328                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      9511346                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq      6196752                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq       886361                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp       779633                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     28635865                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18059535                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       358708                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1078688                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         48132796                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    612072768                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    561022439                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1317384                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      3945224                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1178357815                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                   11561310                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     42854991                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       1.281176                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.449573                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq        876246                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     14005082                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        38305                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        29885                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback      6885213                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict     13979886                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       878417                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       473566                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       319318                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       460407                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           62                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          105                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1465787                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1113779                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      9472232                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5781099                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       926693                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       819709                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     28518742                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     17480007                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       376075                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1070420                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         47445244                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    609569408                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    544120273                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1382192                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      3906208                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1158978081                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                   10243316                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     41099849                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       1.261354                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.439372                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1          30805196     71.88%     71.88% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2          12049795     28.12%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1          30358253     73.86%     73.86% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2          10741596     26.14%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      42854991                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   19582200977                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      41099849                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   19306972981                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    188679986                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    182073987                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy  14347273859                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy  14288744572                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   7985002182                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   7674112954                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    194043982                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    203313475                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    585561447                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    582176435                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups              137760504                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         98367064                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          6188278                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups           103396299                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               75843064                       # Number of BTB hits
+system.cpu1.branchPred.lookups              125904408                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         89122664                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          5902634                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            94266188                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               68486701                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            73.351817                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               15930905                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect           1003913                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            72.652456                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               15015861                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect           1004863                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1378,62 +1364,65 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   290439                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               290439                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        10797                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        87034                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples       290439                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0         290439    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       290439                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        97831                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 20885.603745                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 19076.396548                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 15781.781984                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535        96557     98.70%     98.70% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1078      1.10%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607           36      0.04%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143           66      0.07%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679           60      0.06%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215           20      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        97831                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  -1532721648                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0    -1532721648    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  -1532721648                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        87034     88.96%     88.96% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        10797     11.04%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total        97831                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       290439                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks                   261999                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               261999                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         7478                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        69980                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples       261999                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0         261999    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       261999                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        77458                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 19301.763536                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 17918.383858                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 10994.886931                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767        74315     95.94%     95.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-65535         2659      3.43%     99.38% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-98303          247      0.32%     99.69% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-131071          165      0.21%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-163839           17      0.02%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::163840-196607            5      0.01%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-229375           16      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::229376-262143            8      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-294911           10      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::294912-327679            9      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-360447            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::360448-393215            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        77458                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  -1501931648                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    -1501931648    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  -1501931648                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        69980     90.35%     90.35% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M         7478      9.65%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        77458                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       261999                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       290439                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        97831                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       261999                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        77458                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        97831                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       388270                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        77458                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       339457                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    89204123                       # DTB read hits
-system.cpu1.dtb.read_misses                    242859                       # DTB read misses
-system.cpu1.dtb.write_hits                   77378465                       # DTB write hits
-system.cpu1.dtb.write_misses                    47580                       # DTB write misses
+system.cpu1.dtb.read_hits                    82663207                       # DTB read hits
+system.cpu1.dtb.read_misses                    218762                       # DTB read misses
+system.cpu1.dtb.write_hits                   71167787                       # DTB write hits
+system.cpu1.dtb.write_misses                    43237                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              41950                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1046                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   40087                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                     1034                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  8257                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              38178                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1015                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   35788                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      902                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  6887                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    11467                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                89446982                       # DTB read accesses
-system.cpu1.dtb.write_accesses               77426045                       # DTB write accesses
+system.cpu1.dtb.perms_faults                     9904                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                82881969                       # DTB read accesses
+system.cpu1.dtb.write_accesses               71211024                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        166582588                       # DTB hits
-system.cpu1.dtb.misses                         290439                       # DTB misses
-system.cpu1.dtb.accesses                    166873027                       # DTB accesses
+system.cpu1.dtb.hits                        153830994                       # DTB hits
+system.cpu1.dtb.misses                         261999                       # DTB misses
+system.cpu1.dtb.accesses                    154092993                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1463,192 +1452,191 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    66791                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                66791                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          712                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        57147                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        66791                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          66791    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        66791                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        57859                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 23479.562384                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 21074.499694                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 18067.183609                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767        53326     92.17%     92.17% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535         3146      5.44%     97.60% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303          488      0.84%     98.45% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071          735      1.27%     99.72% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839           30      0.05%     99.77% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607           27      0.05%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375           52      0.09%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143           18      0.03%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911            8      0.01%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679            9      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-360447           10      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215            8      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                    59152                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                59152                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          461                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        48561                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        59152                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          59152    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        59152                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        49022                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 21340.612378                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 19735.982166                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 12453.289543                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767        45897     93.63%     93.63% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535         2624      5.35%     98.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303          160      0.33%     99.30% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071          295      0.60%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839           12      0.02%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607            9      0.02%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375           10      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143            5      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911            2      0.00%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::360448-393215            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        57859                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  -1533304148                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    -1533304148    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  -1533304148                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        57147     98.77%     98.77% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          712      1.23%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        57859                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkCompletionTime::total        49022                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  -1502514148                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    -1502514148    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  -1502514148                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        48561     99.06%     99.06% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          461      0.94%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        49022                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        66791                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        66791                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        59152                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        59152                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        57859                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        57859                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       124650                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   246625416                       # ITB inst hits
-system.cpu1.itb.inst_misses                     66791                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        49022                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        49022                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       108174                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   225695696                       # ITB inst hits
+system.cpu1.itb.inst_misses                     59152                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              41950                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1046                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   29073                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              38178                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1015                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   25916                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   217204                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   201769                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               246692207                       # ITB inst accesses
-system.cpu1.itb.hits                        246625416                       # DTB hits
-system.cpu1.itb.misses                          66791                       # DTB misses
-system.cpu1.itb.accesses                    246692207                       # DTB accesses
-system.cpu1.numCycles                       916577474                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               225754848                       # ITB inst accesses
+system.cpu1.itb.hits                        225695696                       # DTB hits
+system.cpu1.itb.misses                          59152                       # DTB misses
+system.cpu1.itb.accesses                    225754848                       # DTB accesses
+system.cpu1.numCycles                       837975509                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  453450144                       # Number of instructions committed
-system.cpu1.committedOps                    532984432                       # Number of ops (including micro ops) committed
-system.cpu1.discardedOps                     47678042                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends                     5221                       # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles                 94048897478                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi                              2.021341                       # CPI: cycles per instruction
-system.cpu1.ipc                              0.494721                       # IPC: instructions per cycle
+system.cpu1.committedInsts                  416666374                       # Number of instructions committed
+system.cpu1.committedOps                    490559113                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                     42698463                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                     4659                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                 93986622085                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              2.011143                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.497230                       # IPC: instructions per cycle
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    5293                       # number of quiesce instructions executed
-system.cpu1.tickCycles                      728135326                       # Number of cycles that the object actually ticked
-system.cpu1.idleCycles                      188442148                       # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements          5347951                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          430.817141                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          158458993                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5348463                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            29.627015                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8387659413500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   430.817141                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.841440                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.841440                       # Average percentage of cache occupancy
+system.cpu1.kern.inst.quiesce                    5009                       # number of quiesce instructions executed
+system.cpu1.tickCycles                      670350336                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                      167625173                       # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements          4806043                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          444.186980                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          146495712                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          4806555                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            30.478318                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8387638822500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   444.186980                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.867553                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.867553                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          377                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           56                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          141                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          320                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        335833986                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       335833986                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     81837847                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       81837847                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     72225758                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      72225758                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       239509                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       239509                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data       145455                       # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total       145455                       # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1785819                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1785819                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1759762                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1759762                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    154063605                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       154063605                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    154303114                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      154303114                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      3469404                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      3469404                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      2254005                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      2254005                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       641263                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       641263                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data       468533                       # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total       468533                       # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       172541                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       172541                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       196757                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       196757                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      5723409                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       5723409                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      6364672                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      6364672                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  51425230000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  51425230000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  38096829500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  38096829500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  16555952500                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total  16555952500                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2623224000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   2623224000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4131954500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   4131954500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2147500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2147500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  89522059500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  89522059500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  89522059500                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  89522059500                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     85307251                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     85307251                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     74479763                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     74479763                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       880772                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       880772                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       613988                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total       613988                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1958360                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      1958360                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1956519                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      1956519                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    159787014                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    159787014                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    160667786                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    160667786                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.040670                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.040670                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030263                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.030263                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.728069                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.728069                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.763098                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total     0.763098                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.088105                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.088105                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.100565                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.100565                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.035819                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.035819                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.039614                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.039614                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14822.496890                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14822.496890                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16901.838949                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 16901.838949                       # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 35335.723418                       # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 35335.723418                       # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15203.482071                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15203.482071                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21000.292239                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21000.292239                       # average StoreCondReq miss latency
+system.cpu1.dcache.tags.tag_accesses        309963007                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       309963007                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     75874550                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       75874550                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     66435000                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      66435000                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       232604                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       232604                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data       157450                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total       157450                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1693988                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1693988                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1671438                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1671438                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    142309550                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       142309550                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    142542154                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      142542154                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      3161753                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      3161753                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      1996683                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      1996683                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       552089                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       552089                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       421817                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       421817                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       158395                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       158395                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       179133                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       179133                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      5158436                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       5158436                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      5710525                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      5710525                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  43703345000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  43703345000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  33230827500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  33230827500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  13699084500                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  13699084500                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2222797000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   2222797000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   3749543500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   3749543500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3215500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3215500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  76934172500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  76934172500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  76934172500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  76934172500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     79036303                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     79036303                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     68431683                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     68431683                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       784693                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       784693                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       579267                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       579267                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1852383                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      1852383                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1850571                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      1850571                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    147467986                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    147467986                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    148252679                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    148252679                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.040004                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.040004                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.029178                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.029178                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.703573                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.703573                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.728191                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.728191                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.085509                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.085509                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.096799                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.096799                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.034980                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.034980                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.038519                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.038519                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13822.504478                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 13822.504478                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16643.016192                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 16643.016192                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 32476.368899                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 32476.368899                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14033.252312                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14033.252312                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20931.617848                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20931.617848                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15641.387764                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 15641.387764                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14065.463153                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14065.463153                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14914.243872                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 14914.243872                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13472.346676                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 13472.346676                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1657,161 +1645,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      3440440                       # number of writebacks
-system.cpu1.dcache.writebacks::total          3440440                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       392659                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       392659                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       925831                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       925831                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data           46                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::total           46                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        41204                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        41204                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           43                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::total           43                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      1318490                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      1318490                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      1318490                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      1318490                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3076745                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      3076745                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1328174                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1328174                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       640972                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       640972                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       468487                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total       468487                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       131337                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       131337                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       196714                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       196714                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4404919                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4404919                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      5045891                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      5045891                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         5366                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total         5366                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         5280                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         5280                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        10646                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        10646                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  41480566500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  41480566500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  21714665000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  21714665000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12811841000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  12811841000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  16084660000                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  16084660000                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1751023000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1751023000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3933903500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3933903500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1830000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1830000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  63195231500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  63195231500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  76007072500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  76007072500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    593786000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    593786000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    651165500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    651165500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1244951500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1244951500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036067                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036067                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017833                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017833                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.727739                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.727739                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.763023                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.763023                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.067065                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.067065                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.100543                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.100543                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027567                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.027567                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031406                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.031406                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13481.964381                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13481.964381                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16349.262220                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16349.262220                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19988.144568                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19988.144568                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 34333.204550                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 34333.204550                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13332.290215                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13332.290215                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19998.086054                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19998.086054                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      3028608                       # number of writebacks
+system.cpu1.dcache.writebacks::total          3028608                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       352163                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       352163                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       814004                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       814004                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data           58                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::total           58                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        37997                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        37997                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           57                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::total           57                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      1166167                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      1166167                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      1166167                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      1166167                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2809590                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      2809590                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1182679                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1182679                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       551754                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       551754                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       421759                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       421759                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       120398                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       120398                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       179076                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       179076                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      3992269                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      3992269                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      4544023                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      4544023                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         8249                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         8249                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         8420                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         8420                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        16669                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        16669                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  35216853500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  35216853500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  19067594000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  19067594000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  11091696000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  11091696000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  13273963000                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  13273963000                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1514299000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1514299000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3568894000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3568894000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2841500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2841500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  54284447500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  54284447500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  65376143500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  65376143500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1096081500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   1096081500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1226588000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   1226588000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   2322669500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   2322669500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035548                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035548                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017283                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017283                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.703146                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.703146                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.728091                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.728091                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.064996                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.064996                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.096768                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.096768                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027072                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.027072                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.030651                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.030651                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12534.516958                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12534.516958                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16122.374710                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16122.374710                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20102.610946                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20102.610946                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 31472.862464                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 31472.862464                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12577.443147                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12577.443147                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19929.493623                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19929.493623                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14346.513863                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14346.513863                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15063.161788                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15063.161788                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 110657.100261                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 110657.100261                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 123326.799242                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 123326.799242                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 116940.775878                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 116940.775878                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13597.392235                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13597.392235                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14387.282701                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14387.282701                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 132874.469633                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 132874.469633                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145675.534442                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 145675.534442                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 139340.662307                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 139340.662307                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          9156821                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          506.982135                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          237244674                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          9157333                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            25.907617                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8375787773000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   506.982135                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.990199                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.990199                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements          8962341                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          506.974355                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          216525917                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          8962853                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            24.158147                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8375817756000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   506.974355                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.990184                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.990184                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          151                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          336                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          351                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           52                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        501961349                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       501961349                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    237244674                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      237244674                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    237244674                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       237244674                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    237244674                       # number of overall hits
-system.cpu1.icache.overall_hits::total      237244674                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      9157334                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      9157334                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      9157334                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       9157334                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      9157334                       # number of overall misses
-system.cpu1.icache.overall_misses::total      9157334                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  90409615500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  90409615500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  90409615500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  90409615500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  90409615500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  90409615500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    246402008                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    246402008                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    246402008                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    246402008                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    246402008                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    246402008                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.037164                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.037164                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.037164                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.037164                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.037164                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.037164                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9872.918854                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  9872.918854                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9872.918854                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  9872.918854                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9872.918854                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  9872.918854                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses        459940393                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       459940393                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    216525917                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      216525917                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    216525917                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       216525917                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    216525917                       # number of overall hits
+system.cpu1.icache.overall_hits::total      216525917                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      8962853                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      8962853                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      8962853                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       8962853                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      8962853                       # number of overall misses
+system.cpu1.icache.overall_misses::total      8962853                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  87475415500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  87475415500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  87475415500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  87475415500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  87475415500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  87475415500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    225488770                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    225488770                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    225488770                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    225488770                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    225488770                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    225488770                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.039749                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.039749                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.039749                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.039749                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.039749                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.039749                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9759.773534                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  9759.773534                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9759.773534                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  9759.773534                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9759.773534                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  9759.773534                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1820,257 +1808,254 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      9157334                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      9157334                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      9157334                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      9157334                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      9157334                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      9157334                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      8962853                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      8962853                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      8962853                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      8962853                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      8962853                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      8962853                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           93                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total           93                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           93                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total           93                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  85830949000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  85830949000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  85830949000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  85830949000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  85830949000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  85830949000                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8848000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8848000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8848000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      8848000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.037164                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.037164                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.037164                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.037164                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.037164                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.037164                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9372.918908                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9372.918908                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9372.918908                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  9372.918908                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9372.918908                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  9372.918908                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95139.784946                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95139.784946                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95139.784946                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95139.784946                       # average overall mshr uncacheable latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  82993989000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  82993989000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  82993989000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  82993989000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  82993989000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  82993989000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8742000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8742000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8742000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      8742000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.039749                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.039749                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.039749                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.039749                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.039749                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.039749                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9259.773534                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9259.773534                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9259.773534                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  9259.773534                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9259.773534                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  9259.773534                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst        94000                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total        94000                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst        94000                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total        94000                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      7355033                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      7356454                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit         1193                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      6768411                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      6768469                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit           54                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       921370                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements         2420449                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13525.501015                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          25921683                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2436577                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           10.638565                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    9890893366500                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  5242.566110                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    80.941753                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    86.247702                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3561.549924                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3753.026790                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   801.168735                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.319981                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004940                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.005264                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.217380                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.229067                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.048899                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.825531                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1192                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           58                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14878                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1            6                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          317                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          534                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          335                       # Occupied blocks per task id
+system.cpu1.l2cache.prefetcher.pfSpanPage       863435                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements         2141720                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13540.912612                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          24731326                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         2157705                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           11.461866                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    9851161667500                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks  5143.146487                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    72.763483                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    75.029020                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  4350.990102                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3012.175036                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   886.808482                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.313913                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004441                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004579                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.265563                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.183849                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.054126                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.826472                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1213                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           83                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14689                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::0            5                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           25                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          401                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          707                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4           75                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            3                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           39                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           14                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1163                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5423                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4799                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3398                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.072754                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003540                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.908081                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       488189494                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      488189494                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       527706                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       160378                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        688084                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks      3440434                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total      3440434                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        69060                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total        69060                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        37815                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total        37815                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       888572                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       888572                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      8367748                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      8367748                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2856681                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total      2856681                       # number of ReadSharedReq hits
-system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       194722                       # number of InvalidateReq hits
-system.cpu1.l2cache.InvalidateReq_hits::total       194722                       # number of InvalidateReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       527706                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       160378                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      8367748                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3745253                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total       12801085                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       527706                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       160378                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      8367748                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3745253                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total      12801085                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        11992                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         8532                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        20524                       # number of ReadReq misses
-system.cpu1.l2cache.Writeback_misses::writebacks            3                       # number of Writeback misses
-system.cpu1.l2cache.Writeback_misses::total            3                       # number of Writeback misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       136249                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       136249                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       158895                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       158895                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            4                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total            4                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       235953                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       235953                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       789586                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total       789586                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       992043                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total       992043                       # number of ReadSharedReq misses
-system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       272649                       # number of InvalidateReq misses
-system.cpu1.l2cache.InvalidateReq_misses::total       272649                       # number of InvalidateReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        11992                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         8532                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       789586                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1227996                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      2038106                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        11992                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         8532                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       789586                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1227996                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      2038106                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    446382000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    354037500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total    800419500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2966896500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total   2966896500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3304625499                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3304625499                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1763998                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1763998                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   9908657497                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   9908657497                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  22229315000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total  22229315000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  31556071491                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total  31556071491                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  14034162000                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::total  14034162000                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    446382000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    354037500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  22229315000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data  41464728988                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  64494463488                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    446382000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    354037500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  22229315000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  41464728988                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  64494463488                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       539698                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       168910                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       708608                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks      3440437                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total      3440437                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       205309                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       205309                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       196710                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       196710                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            4                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            4                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1124525                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1124525                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      9157334                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total      9157334                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3848724                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total      3848724                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       467371                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::total       467371                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       539698                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       168910                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      9157334                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data      4973249                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total     14839191                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       539698                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       168910                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      9157334                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data      4973249                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     14839191                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.022220                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.050512                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.028964                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000001                       # miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_miss_rate::total     0.000001                       # miss rate for Writeback accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.663629                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.663629                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.807763                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.807763                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           53                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           26                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          662                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5268                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         8016                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          626                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.074036                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005066                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.896545                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       461861904                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      461861904                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       450787                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       134849                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        585636                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks      3028606                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total      3028606                       # number of Writeback hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        55878                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total        55878                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        34341                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total        34341                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       766672                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total       766672                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      8228059                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      8228059                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2592448                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total      2592448                       # number of ReadSharedReq hits
+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       167873                       # number of InvalidateReq hits
+system.cpu1.l2cache.InvalidateReq_hits::total       167873                       # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       450787                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       134849                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      8228059                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data      3359120                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total       12172815                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       450787                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker       134849                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      8228059                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data      3359120                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total      12172815                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        10577                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         7168                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total        17745                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       137373                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total       137373                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       144729                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total       144729                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            6                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::total            6                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data       224779                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total       224779                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       734794                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total       734794                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       888888                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total       888888                       # number of ReadSharedReq misses
+system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       252467                       # number of InvalidateReq misses
+system.cpu1.l2cache.InvalidateReq_misses::total       252467                       # number of InvalidateReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        10577                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker         7168                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst       734794                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data      1113667                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total      1866206                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        10577                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker         7168                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst       734794                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data      1113667                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total      1866206                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    295249500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    216312000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total    511561500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2960853000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total   2960853000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   2990715499                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   2990715499                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2750499                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2750499                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   8344875497                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total   8344875497                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  20496216000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total  20496216000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  25619176492                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total  25619176492                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  11469563500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::total  11469563500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    295249500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    216312000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst  20496216000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data  33964051989                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total  54971829489                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    295249500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    216312000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst  20496216000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data  33964051989                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total  54971829489                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       461364                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       142017                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total       603381                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks      3028606                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total      3028606                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       193251                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       193251                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       179070                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       179070                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            6                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            6                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data       991451                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total       991451                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      8962853                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total      8962853                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3481336                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total      3481336                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       420340                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::total       420340                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       461364                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       142017                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst      8962853                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data      4472787                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total     14039021                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       461364                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       142017                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      8962853                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data      4472787                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total     14039021                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.022925                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.050473                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.029409                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.710853                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.710853                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.808226                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.808226                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.209825                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.209825                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.086224                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.086224                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.257759                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.257759                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.583367                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.583367                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.022220                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.050512                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.086224                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.246920                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.137346                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.022220                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.050512                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.086224                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.246920                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.137346                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37223.315544                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41495.253165                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 38999.196063                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21775.546976                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21775.546976                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20797.542396                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20797.542396                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 440999.500000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 440999.500000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 41994.200103                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41994.200103                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 28153.127082                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 28153.127082                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 31809.177113                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 31809.177113                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 51473.366856                       # average InvalidateReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 51473.366856                       # average InvalidateReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37223.315544                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41495.253165                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28153.127082                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33766.175939                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 31644.312655                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37223.315544                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41495.253165                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28153.127082                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33766.175939                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 31644.312655                       # average overall miss latency
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.226717                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.226717                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.081982                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.081982                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.255330                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.255330                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.600626                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.600626                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.022925                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.050473                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.081982                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.248987                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.132930                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.022925                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.050473                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.081982                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.248987                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.132930                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 27914.295169                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 30177.455357                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 28828.486898                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21553.383853                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21553.383853                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20664.244892                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20664.244892                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 458416.500000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 458416.500000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 37124.800346                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 37124.800346                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 27893.826025                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 27893.826025                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 28821.602375                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 28821.602375                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 45429.951241                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 45429.951241                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 27914.295169                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 30177.455357                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 27893.826025                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30497.493406                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 29456.463804                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 27914.295169                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 30177.455357                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 27893.826025                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30497.493406                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 29456.463804                       # average overall miss latency
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -2079,236 +2064,232 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks      1031306                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1031306                       # number of writebacks
+system.cpu1.l2cache.writebacks::writebacks       853283                       # number of writebacks
+system.cpu1.l2cache.writebacks::total          853283                       # number of writebacks
 system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            2                       # number of ReadReq MSHR hits
 system.cpu1.l2cache.ReadReq_mshr_hits::total            2                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         7033                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total         7033                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            1                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          605                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          605                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data           17                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::total           17                       # number of InvalidateReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         3653                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total         3653                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            5                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          365                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          365                       # number of ReadSharedReq MSHR hits
 system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            2                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data         7638                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total         7641                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            5                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data         4018                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total         4025                       # number of demand (read+write) MSHR hits
 system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            2                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            1                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data         7638                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         7641                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        11992                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         8530                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        20522                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.Writeback_mshr_misses::writebacks            3                       # number of Writeback MSHR misses
-system.cpu1.l2cache.Writeback_mshr_misses::total            3                       # number of Writeback MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks       115811                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::total       115811                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       714965                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       714965                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       136249                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       136249                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       158895                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       158895                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            4                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       228920                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total       228920                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       789585                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       789585                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       991438                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       991438                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       272632                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::total       272632                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        11992                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         8530                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       789585                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1220358                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total      2030465                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        11992                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         8530                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       789585                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1220358                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       714965                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total      2745430                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            5                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data         4018                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total         4025                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        10577                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         7166                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total        17743                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks       103597                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::total       103597                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       615258                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total       615258                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       137373                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total       137373                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       144729                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       144729                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            6                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            6                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       221126                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total       221126                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       734789                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       734789                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       888523                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       888523                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       252467                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::total       252467                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        10577                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         7166                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       734789                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1109649                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total      1862181                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        10577                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         7166                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       734789                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1109649                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       615258                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total      2477439                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           93                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         5366                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         5459                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         5280                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         5280                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         8249                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         8342                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         8420                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         8420                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           93                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        10646                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        10739                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    374430000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    302816000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    677246000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  30632454632                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  30632454632                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2763352994                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2763352994                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2438062999                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2438062999                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1505998                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1505998                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   7634474497                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   7634474497                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  17491788500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  17491788500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  25566861991                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  25566861991                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  12398047000                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  12398047000                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    374430000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    302816000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  17491788500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  33201336488                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  51370370988                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    374430000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    302816000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  17491788500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  33201336488                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  30632454632                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total  82002825620                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8104000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    550842500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    558946500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    611561500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    611561500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8104000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1162404000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1170508000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.022220                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.050500                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.028961                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000001                       # mshr miss rate for Writeback accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        16669                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        16762                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    231787500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    173284500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    405072000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  18848278545                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  18848278545                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2780289998                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2780289998                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2207149499                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2207149499                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2390499                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2390499                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   6581571997                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   6581571997                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  16087394500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  16087394500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  20254649492                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  20254649492                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   9954761500                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   9954761500                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    231787500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    173284500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  16087394500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  26836221489                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total  43328687989                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    231787500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    173284500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  16087394500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  26836221489                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  18848278545                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total  62176966534                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7998000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   1030068000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   1038066000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1163435000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1163435000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7998000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   2193503000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   2201501000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.022925                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.050459                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.029406                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.663629                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.663629                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.807763                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.807763                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.710853                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.710853                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.808226                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.808226                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.203570                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.203570                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.086224                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.086224                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.257602                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.257602                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.583331                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.583331                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.022220                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.050500                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.086224                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.245384                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.136831                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.022220                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.050500                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.086224                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.245384                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.223033                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.223033                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.081982                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.081982                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.255225                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.255225                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.600626                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.600626                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.022925                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.050459                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.081982                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.248089                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.132643                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.022925                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.050459                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.081982                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.248089                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.185012                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33000.974564                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42844.691183                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 42844.691183                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20281.638720                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20281.638720                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15343.862293                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15343.862293                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 376499.500000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 376499.500000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33349.967224                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33349.967224                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22153.141840                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22153.141840                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25787.655901                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25787.655901                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 45475.391737                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 45475.391737                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22153.141840                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27206.226770                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25299.806196                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22153.141840                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27206.226770                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42844.691183                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29868.845908                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87139.784946                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 102654.211703                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102389.906576                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 115826.041667                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 115826.041667                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87139.784946                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 109186.924667                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 108995.995903                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.176468                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 21914.295169                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 24181.481998                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22829.961111                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30634.755737                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 30634.755737                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20238.984356                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20238.984356                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15250.222823                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15250.222823                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 398416.500000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 398416.500000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29763.899302                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29763.899302                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 21893.896751                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 21893.896751                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 22795.864026                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22795.864026                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 39429.951241                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 39429.951241                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 21914.295169                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 24181.481998                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21893.896751                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24184.423623                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23267.710276                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 21914.295169                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 24181.481998                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21893.896751                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24184.423623                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30634.755737                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25097.274457                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst        86000                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 124871.863256                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 124438.503956                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 138175.178147                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 138175.178147                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst        86000                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 131591.757154                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 131338.802052                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq        927149                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp     13939785                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        38095                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         5280                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback      7136333                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict     14143122                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq      1073027                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       445884                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       351130                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       465721                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           65                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          104                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1873672                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1132302                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      9157334                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq      6348630                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq       574099                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp       467371                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     27470555                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     17217135                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       368278                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1176846                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         46232814                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    586075264                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    544882505                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1351280                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4317584                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total        1136626633                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                   12009621                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     42070384                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       1.298426                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.457567                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq        832335                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp     13281124                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        38305                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         8420                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback      6193652                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict     13562835                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq       802874                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp            2                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       426908                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       320139                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       432313                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           51                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          105                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1723284                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp       998712                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      8962853                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      5808138                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       527324                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       420340                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     26886674                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15523980                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       318688                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1026227                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         43755569                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    573628544                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    486175782                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1136136                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      3690912                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total        1064631374                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                   10738560                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     39200977                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       1.285389                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.451600                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1          29515487     70.16%     70.16% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2          12554897     29.84%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1          28013450     71.46%     71.46% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2          11187527     28.54%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      42070384                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   18619089977                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      39200977                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   17410316483                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    181245984                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    171564976                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy  13738184900                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy  13446378573                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   7905383000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   7120820957                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    199375485                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    176677986                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    637173449                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    564893937                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40322                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40322                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136608                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136608                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47696                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                40371                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40371                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136979                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136979                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47802                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2318,18 +2299,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29808                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122578                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231202                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231202                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122944                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231676                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231676                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353860                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47716                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354700                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47822                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2339,18 +2320,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17703                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155708                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338824                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7338824                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155959                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7355056                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7355056                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7496618                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36211000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7513101                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36314000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -2370,7 +2351,7 @@ system.iobus.reqLayer16.occupancy               12000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            22142000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
@@ -2378,71 +2359,71 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           569805082                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           570865133                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92701000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92952000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147898000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           148116000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115582                       # number of replacements
-system.iocache.tags.tagsinuse               11.293791                       # Cycle average of tags in use
+system.iocache.tags.replacements               115819                       # number of replacements
+system.iocache.tags.tagsinuse               11.287255                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115598                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115835                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9174209621000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.830929                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     7.462862                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.239433                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.466429                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.705862                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         9174218723000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.836610                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     7.450645                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.239788                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.465665                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.705453                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1040766                       # Number of tag accesses
-system.iocache.tags.data_accesses             1040766                       # Number of data accesses
+system.iocache.tags.tag_accesses              1042899                       # Number of tag accesses
+system.iocache.tags.data_accesses             1042899                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8873                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8910                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8854                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8891                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::realview.ide       106984                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total       106984                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8873                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8913                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8854                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8894                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8873                       # number of overall misses
-system.iocache.overall_misses::total             8913                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8854                       # number of overall misses
+system.iocache.overall_misses::total             8894                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5195000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1631093968                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1636288968                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1658968057                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1664163057                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  12624582114                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  12624582114                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12654105076                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12654105076                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5564000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1631093968                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1636657968                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1658968057                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1664532057                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5564000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1631093968                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1636657968                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1658968057                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1664532057                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8873                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8910                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8854                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8891                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide       106984                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total       106984                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8873                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8913                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8854                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8894                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8873                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8913                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8854                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8894                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2457,54 +2438,54 @@ system.iocache.overall_miss_rate::realview.ethernet            1
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 183826.661558                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 183646.348822                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 187369.331037                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 187173.890114                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118287.442040                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118287.442040                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118280.351043                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118280.351043                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 183826.661558                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 183625.936048                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 187369.331037                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 187152.243872                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 183826.661558                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 183625.936048                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         31363                       # number of cycles access was blocked
+system.iocache.overall_avg_miss_latency::realview.ide 187369.331037                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 187152.243872                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         32802                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3550                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3449                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     8.834648                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.510583                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks          106694                       # number of writebacks
-system.iocache.writebacks::total               106694                       # number of writebacks
+system.iocache.writebacks::writebacks          106950                       # number of writebacks
+system.iocache.writebacks::total               106950                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8873                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8910                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8854                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8891                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide       106984                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total       106984                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8873                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8913                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8854                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8894                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8873                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8913                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide         8854                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8894                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3345000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1187443968                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1190788968                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1216268057                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1219613057                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7288182114                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   7288182114                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7304905076                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7304905076                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3564000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1187443968                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1191007968                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1216268057                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1219832057                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3564000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1187443968                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1191007968                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1216268057                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1219832057                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -2519,613 +2500,614 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet            1
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133826.661558                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 133646.348822                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137369.331037                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 137173.890114                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68287.442040                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68287.442040                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68280.351043                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68280.351043                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 133826.661558                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 133625.936048                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 137369.331037                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 137152.243872                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 133826.661558                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 133625.936048                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 137369.331037                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 137152.243872                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1460315                       # number of replacements
-system.l2c.tags.tagsinuse                63815.106569                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    6243583                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1520944                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     4.105071                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1146599                       # number of replacements
+system.l2c.tags.tagsinuse                63894.227459                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    5787888                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1208030                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     4.791179                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   17020.262251                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   105.114677                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   114.825043                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4617.432955                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     6910.402402                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  7514.168760                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   272.316465                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   336.862323                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3976.770964                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     9922.626808                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13024.323921                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.259709                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001604                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.001752                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.070456                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.105444                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.114657                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004155                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.005140                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.060681                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.151407                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.198735                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.973741                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022         9634                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          233                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        50762                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          214                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3          450                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4         8970                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          232                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2000                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         4985                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        43502                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.147003                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.003555                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.774567                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 74931302                       # Number of tag accesses
-system.l2c.tags.data_accesses                74931302                       # Number of data accesses
-system.l2c.Writeback_hits::writebacks         2473005                       # number of Writeback hits
-system.l2c.Writeback_hits::total              2473005                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data           29717                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data           30251                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               59968                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          5861                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          6611                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             12472                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           174264                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           168948                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               343212                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6955                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker         5054                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst       704009                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       596815                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       296922                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6236                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4142                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst       738933                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       577563                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       321187                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          3257816                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          6955                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          5054                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              704009                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              771079                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       296922                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          6236                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          4142                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              738933                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              746511                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher       321187                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 3601028                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         6955                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         5054                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             704009                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             771079                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       296922                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         6236                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         4142                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             738933                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             746511                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       321187                       # number of overall hits
-system.l2c.overall_hits::total                3601028                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data         43094                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         44585                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             87679                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data         8745                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         9538                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           18283                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         499472                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data         152688                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             652160                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1944                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1581                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        73537                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       135426                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       239395                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         2244                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker         2077                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst        50651                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data       119141                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       208595                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         834591                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         1944                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         1581                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             73537                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            634898                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       239395                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         2244                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         2077                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             50651                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            271829                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       208595                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1486751                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         1944                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         1581                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            73537                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           634898                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       239395                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         2244                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         2077                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            50651                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           271829                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       208595                       # number of overall misses
-system.l2c.overall_misses::total              1486751                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data    260324500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    277994500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    538319000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data     55253500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data     54480000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total    109733500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  46824185500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data  13176547500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  60000733000                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    176295500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    146583500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   6133823500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  12343951000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  30575603157                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    201877500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    184505000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst   4199208000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data  10504090000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  25273313307                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  89739250464                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    176295500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    146583500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   6133823500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  59168136500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  30575603157                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    201877500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    184505000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   4199208000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  23680637500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  25273313307                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    149739983464                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    176295500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    146583500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   6133823500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  59168136500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  30575603157                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    201877500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    184505000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   4199208000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  23680637500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  25273313307                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   149739983464                       # number of overall miss cycles
-system.l2c.Writeback_accesses::writebacks      2473005                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          2473005                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        72811                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        74836                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          147647                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        14606                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        16149                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         30755                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       673736                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       321636                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           995372                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         8899                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         6635                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst       777546                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       732241                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       536317                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         8480                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         6219                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst       789584                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       696704                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       529782                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      4092407                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         8899                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         6635                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          777546                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1405977                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       536317                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         8480                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         6219                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          789584                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data         1018340                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       529782                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             5087779                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         8899                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         6635                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         777546                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1405977                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       536317                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         8480                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         6219                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         789584                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data        1018340                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       529782                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            5087779                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.591861                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.595769                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.593842                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.598727                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.590625                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.594472                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.741347                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.474723                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.655192                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.218452                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.238282                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.094576                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.184947                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.446368                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.264623                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.333977                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.064149                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.171007                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.393737                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.203936                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.218452                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.238282                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.094576                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.451571                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.446368                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.264623                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.333977                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.064149                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.266933                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.393737                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.292220                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.218452                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.238282                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.094576                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.451571                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.446368                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.264623                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.333977                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.064149                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.266933                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.393737                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.292220                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6040.852555                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6235.157564                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  6139.657158                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6318.296169                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5711.889285                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  6001.941694                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 93747.368221                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 86297.204102                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 92003.086666                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 90686.985597                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 92715.686275                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83411.391544                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 91149.048189                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 127720.308097                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89963.235294                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 88832.450650                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82904.740282                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 88165.199218                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 121159.727256                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 107524.824092                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90686.985597                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 92715.686275                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 83411.391544                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 93193.137323                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 127720.308097                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89963.235294                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88832.450650                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 82904.740282                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 87115.935018                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 121159.727256                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 100716.248695                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90686.985597                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 92715.686275                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 83411.391544                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 93193.137323                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 127720.308097                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89963.235294                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88832.450650                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 82904.740282                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 87115.935018                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 121159.727256                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 100716.248695                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs               107                       # number of cycles access was blocked
+system.l2c.tags.occ_blocks::writebacks   20522.379023                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   161.905583                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   188.170352                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     7049.393840                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    11329.558347                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 10071.994886                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    91.721739                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   112.803397                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     4897.031985                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     4344.569454                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  5124.698853                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.313147                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002470                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.002871                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.107565                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.172875                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.153686                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.001400                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.001721                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.074723                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.066293                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.078197                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.974949                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        10689                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          178                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        50564                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          577                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3         2554                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4         7550                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3            6                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          172                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          271                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         1822                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3        12846                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        35586                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.163101                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.002716                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.771545                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 67839853                       # Number of tag accesses
+system.l2c.tags.data_accesses                67839853                       # Number of data accesses
+system.l2c.Writeback_hits::writebacks         2183647                       # number of Writeback hits
+system.l2c.Writeback_hits::total              2183647                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data           31153                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data           25605                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               56758                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data          6308                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data          5360                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total             11668                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           179937                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data           157833                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               337770                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6619                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4994                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst       688403                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       550904                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       317834                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         5630                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker         3645                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst       689738                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       516463                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       301818                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          3086048                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          6619                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          4994                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              688403                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              730841                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher       317834                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          5630                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          3645                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              689738                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              674296                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher       301818                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 3423818                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         6619                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         4994                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             688403                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             730841                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher       317834                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         5630                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         3645                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             689738                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             674296                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher       301818                       # number of overall hits
+system.l2c.overall_hits::total                3423818                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data         42274                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data         44615                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             86889                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data         8694                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data         8260                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total           16954                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         478873                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data         118092                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             596965                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1177                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1112                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.inst        65012                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       121116                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       167688                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.dtb.walker          801                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.itb.walker          747                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.inst        45048                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data        75565                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       121227                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         599493                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.dtb.walker         1177                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker         1112                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             65012                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            599989                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.l2cache.prefetcher       167688                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker          801                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker          747                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst             45048                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data            193657                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.l2cache.prefetcher       121227                       # number of demand (read+write) misses
+system.l2c.demand_misses::total               1196458                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker         1177                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker         1112                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            65012                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           599989                       # number of overall misses
+system.l2c.overall_misses::cpu0.l2cache.prefetcher       167688                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker          801                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker          747                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst            45048                       # number of overall misses
+system.l2c.overall_misses::cpu1.data           193657                       # number of overall misses
+system.l2c.overall_misses::cpu1.l2cache.prefetcher       121227                       # number of overall misses
+system.l2c.overall_misses::total              1196458                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data    285461500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data    257633000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    543094500                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data     50714500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data     48938500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total     99653000                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data  44986860000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   9946118500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  54932978500                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    102808500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker     98262500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.inst   5348800500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data  10715307000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  19492330795                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker     71359500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker     66724500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst   3695471500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data   6552252500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  13803765015                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  59947082310                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker    102808500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker     98262500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   5348800500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  55702167000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  19492330795                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker     71359500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker     66724500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst   3695471500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data  16498371000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  13803765015                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total    114880060810                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker    102808500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker     98262500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   5348800500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  55702167000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  19492330795                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker     71359500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker     66724500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst   3695471500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data  16498371000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  13803765015                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total   114880060810                       # number of overall miss cycles
+system.l2c.Writeback_accesses::writebacks      2183647                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          2183647                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        73427                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data        70220                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          143647                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data        15002                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data        13620                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total         28622                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       658810                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       275925                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           934735                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         7796                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         6106                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst       753415                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       672020                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       485522                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         6431                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         4392                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst       734786                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       592028                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       423045                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      3685541                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         7796                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         6106                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          753415                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1330830                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       485522                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         6431                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         4392                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          734786                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          867953                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher       423045                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             4620276                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         7796                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         6106                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         753415                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1330830                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       485522                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         6431                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         4392                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         734786                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         867953                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher       423045                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            4620276                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.575728                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.635360                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.604879                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.579523                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.606461                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.592342                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.726876                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.427986                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.638646                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.150975                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.182116                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.086290                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.180227                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.345377                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.124553                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.170082                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.061308                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.127638                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.286558                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.162661                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.150975                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.182116                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.086290                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.450838                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.345377                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.124553                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.170082                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.061308                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.223119                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.286558                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.258958                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.150975                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.182116                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.086290                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.450838                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.345377                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.124553                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.170082                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.061308                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.223119                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.286558                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.258958                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6752.649383                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5774.582540                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  6250.440217                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5833.275822                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5924.757869                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  5877.845936                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 93943.195795                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84223.474071                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 92020.434196                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 87347.918437                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 88365.557554                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 82274.049406                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88471.440602                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 116241.655903                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89088.014981                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 89323.293173                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82034.085864                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 86710.150202                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 113867.084189                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 99996.300724                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87347.918437                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88365.557554                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 82274.049406                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 92838.647042                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 116241.655903                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89088.014981                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89323.293173                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 82034.085864                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 85193.775593                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 113867.084189                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 96016.793577                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87347.918437                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88365.557554                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 82274.049406                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 92838.647042                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 116241.655903                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89088.014981                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89323.293173                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 82034.085864                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 85193.775593                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 113867.084189                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 96016.793577                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs               272                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        3                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     35.666667                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     90.666667                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1116158                       # number of writebacks
-system.l2c.writebacks::total                  1116158                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          174                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data           19                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          157                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data           10                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total          360                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst            174                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             19                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst            157                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             10                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                360                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst           174                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            19                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst           157                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            10                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               360                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks        53748                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total        53748                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        43094                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        44585                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        87679                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data         8745                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         9538                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total        18283                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       499472                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data       152688                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        652160                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1944                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1581                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        73363                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       135407                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       239395                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         2244                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         2077                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        50494                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data       119131                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       208595                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       834231                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         1944                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         1581                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        73363                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       634879                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       239395                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         2244                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker         2077                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        50494                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data       271819                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       208595                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total          1486391                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         1944                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         1581                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        73363                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       634879                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       239395                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker         2244                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker         2077                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst        50494                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data       271819                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       208595                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total         1486391                       # number of overall MSHR misses
+system.l2c.writebacks::writebacks              874415                       # number of writebacks
+system.l2c.writebacks::total                   874415                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          124                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu0.data            6                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          136                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.data           15                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total          281                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst            124                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data              6                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst            136                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data             15                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                281                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst           124                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data             6                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst           136                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.data            15                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total               281                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks        39767                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total        39767                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data        42274                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data        44615                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        86889                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data         8694                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         8260                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total        16954                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data       478873                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data       118092                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        596965                       # number of ReadExReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1177                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1112                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        64888                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data       121110                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       167688                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker          801                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker          747                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        44912                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data        75550                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       121227                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total       599212                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker         1177                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker         1112                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        64888                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       599983                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       167688                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker          801                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker          747                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst        44912                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data       193642                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       121227                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total          1196177                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker         1177                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker         1112                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        64888                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       599983                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       167688                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker          801                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker          747                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst        44912                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data       193642                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       121227                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total         1196177                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        52292                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        32882                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data        30167                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           93                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data         5364                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        90631                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        32815                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         5280                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        38095                       # number of WriteReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data         8247                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        90799                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        29885                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         8420                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        38305                       # number of WriteReq MSHR uncacheable
 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        52292                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        65697                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        60052                       # number of overall MSHR uncacheable misses
 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           93                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        10644                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total       128726                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    895608505                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    925545505                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total   1821154010                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    181952000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    198394500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total    380346500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  41829465500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  11649667500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  53479133000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    156855500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    130773500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   5387567000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  10988450500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  28181653157                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    179437500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    163735000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   3683448000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   9312099500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  23187363307                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  81371382964                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    156855500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    130773500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   5387567000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  52817916000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  28181653157                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    179437500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    163735000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst   3683448000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data  20961767000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  23187363307                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 134850515964                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    156855500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    130773500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   5387567000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  52817916000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  28181653157                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    179437500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    163735000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst   3683448000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data  20961767000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  23187363307                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 134850515964                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        16667                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total       129104                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    877451504                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    925962001                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total   1803413505                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    180795000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    171889500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total    352684500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  40198130000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   8765198500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  48963328500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker     91038500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker     87142500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   4691111500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   9503861000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  17815450795                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker     63349500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker     59254500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   3237260500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   5795509500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  12591495015                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  53935473310                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker     91038500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker     87142500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   4691111500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  49701991000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  17815450795                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     63349500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker     59254500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst   3237260500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data  14560708000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  12591495015                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 102898801810                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker     91038500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker     87142500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   4691111500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  49701991000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  17815450795                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     63349500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker     59254500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst   3237260500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data  14560708000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  12591495015                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 102898801810                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   3261312500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5056717000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6149000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    454250000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   8778428500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4878683500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    521791000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5400474500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4641716000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6042500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    881581500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   8790652500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4402307500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1020289500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   5422597000                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   3261312500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9935400500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6149000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    976041000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  14178903000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9044023500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6042500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1901871000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  14213249500                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.591861                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.595769                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.593842                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.598727                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.590625                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.594472                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.741347                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.474723                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.655192                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.218452                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.238282                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.094352                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.184921                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.446368                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.264623                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.333977                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.063950                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.170992                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.393737                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.203848                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.218452                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.238282                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.094352                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.451557                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.446368                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.264623                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.333977                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.063950                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.266924                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.393737                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.292149                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.218452                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.238282                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.094352                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.451557                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.446368                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.264623                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.333977                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.063950                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.266924                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.393737                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.292149                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20782.672878                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20759.123136                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20770.697773                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20806.403659                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20800.429860                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20803.287207                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83747.368221                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 76297.204102                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 82003.086666                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80686.985597                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82715.686275                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73437.114077                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 81151.273568                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117720.308097                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79963.235294                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78832.450650                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72948.231473                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78166.887712                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111159.727256                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 97540.588835                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80686.985597                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82715.686275                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73437.114077                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83193.673125                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117720.308097                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79963.235294                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78832.450650                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72948.231473                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 77116.636438                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111159.727256                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 90723.447575                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80686.985597                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82715.686275                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73437.114077                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83193.673125                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117720.308097                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79963.235294                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78832.450650                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72948.231473                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 77116.636438                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111159.727256                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 90723.447575                       # average overall mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.575728                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.635360                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.604879                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.579523                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.606461                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.592342                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.726876                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.427986                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.638646                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.150975                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.182116                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.086125                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.180218                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.345377                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.124553                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.170082                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.061123                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.127612                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.286558                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.162585                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.150975                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.182116                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.086125                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.450834                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.345377                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.124553                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.170082                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.061123                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.223102                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.286558                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.258897                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.150975                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.182116                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.086125                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.450834                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.345377                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.124553                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.170082                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.061123                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.223102                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.286558                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.258897                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20756.292378                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20754.499630                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20755.371854                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20795.376121                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20809.866828                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20802.436003                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83943.195795                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74223.474071                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 82020.434196                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 77347.918437                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 78365.557554                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72295.516891                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78472.966724                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106241.655903                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79088.014981                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79323.293173                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72080.078821                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 76710.913302                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103867.084189                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 90010.669529                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77347.918437                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78365.557554                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72295.516891                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82838.998772                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106241.655903                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79088.014981                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79323.293173                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72080.078821                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75193.955857                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103867.084189                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 86023.056630                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77347.918437                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78365.557554                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72295.516891                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82838.998772                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106241.655903                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79088.014981                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79323.293173                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72080.078821                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75193.955857                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103867.084189                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 86023.056630                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153783.741865                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66118.279570                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 84684.936614                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 96859.005197                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148672.360201                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 98824.053030                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141763.341646                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153867.338482                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64973.118280                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 106897.235358                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 96814.419762                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147308.265016                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 121174.524941                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141563.686203                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151230.657412                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66118.279570                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91698.703495                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 110147.934372                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 150603.202225                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64973.118280                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 114109.977800                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 110091.472766                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               90631                       # Transaction distribution
-system.membus.trans_dist::ReadResp             933772                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38095                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38095                       # Transaction distribution
-system.membus.trans_dist::Writeback           1222852                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           259291                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           429274                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         300804                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          113465                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            5                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            664837                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           644660                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        843141                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        106728                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp       106728                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122578                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq               90799                       # Transaction distribution
+system.membus.trans_dist::ReadResp             698902                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38305                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38305                       # Transaction distribution
+system.membus.trans_dist::Writeback            981364                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           209019                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           434160                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         274076                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          111283                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            609626                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           589528                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        608103                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        106984                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       106984                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122944                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           52                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        24884                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5299387                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      5446901                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342793                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       342793                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5789694                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155708                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25274                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4403229                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4551499                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       343039                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       343039                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4894538                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155959                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1324                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        49768                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    169409152                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    169615952                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7274560                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7274560                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               176890512                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           639479                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3957833                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        50548                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    135367808                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    135575639                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7275904                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7275904                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               142851543                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           619953                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3354848                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3957833    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3354848    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3957833                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           109447997                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3354848                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           109588500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               33984                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            20601500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            21072500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          8645644788                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          6982752656                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         8381282870                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         6858580357                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          229327995                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          229669194                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -3169,46 +3151,46 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq              90633                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           5042509                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38095                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38095                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          3695900                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         1651242                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          481742                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        313276                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         795018                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          104                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          104                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          1145784                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         1145784                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      4959107                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq       106728                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8783138                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7404481                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              16187619                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    270950615                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    216626041                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              487576656                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         3318184                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         13892424                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.121763                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.327012                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq              90801                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           4609563                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38305                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38305                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          3165042                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1502795                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          483481                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        285744                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         769225                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          105                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          105                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          1092976                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         1092976                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      4526002                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq       106984                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8264892                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6572319                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              14837211                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    254099969                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    185036822                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              439136791                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         2966852                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         12598332                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.109406                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.312147                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1               12200843     87.82%     87.82% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                1691581     12.18%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1               11220005     89.06%     89.06% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                1378327     10.94%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           13892424                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         8859040198                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           12598332                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         8167142441                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2520000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2478499                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        5187778836                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4888169243                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4493465928                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4052371405                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
index 8076f9ab6f50c94254e3131bd3d692d0105e376a..5e0f7ea36ec57443ad4484e91c479b52a06a5591 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.309771                       # Number of seconds simulated
-sim_ticks                                47309771277000                       # Number of ticks simulated
-final_tick                               47309771277000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.309827                       # Number of seconds simulated
+sim_ticks                                47309826639000                       # Number of ticks simulated
+final_tick                               47309826639000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 108265                       # Simulator instruction rate (inst/s)
-host_op_rate                                   127309                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5527040503                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 775928                       # Number of bytes of host memory used
-host_seconds                                  8559.69                       # Real time elapsed on the host
-sim_insts                                   926711685                       # Number of instructions simulated
-sim_ops                                    1089722710                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  99581                       # Simulator instruction rate (inst/s)
+host_op_rate                                   117105                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4980017521                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 777716                       # Number of bytes of host memory used
+host_seconds                                  9499.93                       # Real time elapsed on the host
+sim_insts                                   946011818                       # Number of instructions simulated
+sim_ops                                    1112485532                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       238272                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       235456                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          4799840                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         48757000                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     23433152                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       111936                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        80000                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2674208                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         14294352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     12912064                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        433024                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            107969304                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      4799840                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2674208                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         7474048                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     89515968                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       184448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       167936                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          5084832                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         44767048                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     19339456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       176320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       161792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2535456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         18891728                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     20722048                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        420544                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            112451608                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      5084832                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2535456                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         7620288                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     93755328                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          89536552                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         3723                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         3679                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             90950                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            761841                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       366143                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         1749                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         1250                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             41828                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            223362                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       201751                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6766                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1703042                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1398687                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          93775912                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         2882                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         2624                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             95403                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            699498                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       302179                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2755                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2528                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             39660                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            295196                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       323782                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6571                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1773078                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1464927                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1401261                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          5036                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          4977                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              101456                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1030590                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       495313                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          2366                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          1691                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               56525                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              302144                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       272926                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9153                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2282178                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         101456                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          56525                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             157981                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1892124                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1467501                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          3899                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          3550                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              107479                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              946253                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       408783                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          3727                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          3420                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               53593                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              399319                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       438007                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8889                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2376919                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         107479                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          53593                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             161072                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1981731                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                435                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1892559                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1892124                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         5036                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         4977                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             101456                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1031025                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       495313                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         2366                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         1691                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              56525                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             302144                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       272926                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            9153                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4174737                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1703042                       # Number of read requests accepted
-system.physmem.writeReqs                      1401261                       # Number of write requests accepted
-system.physmem.readBursts                     1703042                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1401261                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                108957568                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     37120                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  89535296                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 107969304                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               89536552                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      580                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total                1982166                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1981731                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         3899                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         3550                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             107479                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             946688                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       408783                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         3727                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         3420                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              53593                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             399319                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       438007                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8889                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4359084                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1773078                       # Number of read requests accepted
+system.physmem.writeReqs                      1467501                       # Number of write requests accepted
+system.physmem.readBursts                     1773078                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1467501                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                113443520                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     33472                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  93774528                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 112451608                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               93775912                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      523                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         222271                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              104244                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              111881                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              106230                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              103315                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              101355                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              106401                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              102755                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              105565                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              101297                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              131029                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             105406                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             116947                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              96908                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             102973                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             100156                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             106000                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               86649                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               91854                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               85255                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               87156                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               84624                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               89053                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               87549                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               90107                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               85432                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               90372                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              86508                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              91779                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              81073                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              87139                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              84132                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              90307                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         224875                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              113386                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              120644                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              108661                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              115173                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              103078                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              114921                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              108340                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              105879                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               98747                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              127278                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              99197                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             111650                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             107228                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             113583                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             112177                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             112613                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               94420                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               97266                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               90974                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               94616                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               87287                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               94599                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               89304                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               90590                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               84448                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               90113                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              85465                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              93225                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              88655                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              95246                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              93025                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              95994                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          40                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47309769886500                       # Total gap between requests
+system.physmem.numWrRetry                          83                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47309825190500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21333                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1681684                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1751720                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1398687                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    611880                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    417253                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    192449                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    184576                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    110779                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     65725                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     35828                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     32285                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     29054                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      9028                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     4622                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     2923                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1841                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1436                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      897                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      648                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      540                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      418                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      167                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       98                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1464927                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    608524                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    449703                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    194607                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    195607                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    116312                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                     71048                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                     40112                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     36551                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     32712                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                     10303                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     5634                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     3467                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     2280                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     1844                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     1284                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      910                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      790                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      582                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      168                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       96                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       14                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
@@ -188,168 +188,170 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    19662                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    22634                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    35927                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    42991                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    51483                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    60587                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    69980                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    79960                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    85124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    91378                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    92978                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    97068                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    98211                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   103646                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   116678                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                   108732                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                   103454                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    92841                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     7303                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     3997                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     2565                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1572                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      925                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      687                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      677                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      663                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      547                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      534                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      470                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      378                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      482                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      469                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      367                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      329                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      245                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      333                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      280                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      240                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      104                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1072258                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      185.116224                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     114.248094                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     242.173437                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         644445     60.10%     60.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       212244     19.79%     79.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        67795      6.32%     86.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        36826      3.43%     89.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        25524      2.38%     92.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        13957      1.30%     93.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        14880      1.39%     94.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         9207      0.86%     95.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        47380      4.42%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1072258                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         80097                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        21.254829                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      256.467221                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095          80095    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    20153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    23447                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    36691                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    44303                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    53186                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    62828                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    72210                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    82749                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    88726                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    95528                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    97547                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                   101638                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                   103246                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                   108748                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                   123417                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                   115282                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                   109625                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    98032                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     7953                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     4632                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     2879                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     1860                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     1227                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      995                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      815                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      720                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      612                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      525                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      410                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      440                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      406                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      425                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      375                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      314                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      311                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      242                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      316                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      313                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      264                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      268                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      296                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      228                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                      119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      281                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples      1119709                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      185.063798                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     114.156365                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     241.940793                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         674939     60.28%     60.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       219039     19.56%     79.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        70659      6.31%     86.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        37987      3.39%     89.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        28223      2.52%     92.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        14545      1.30%     93.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        15798      1.41%     94.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         9595      0.86%     95.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        48924      4.37%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1119709                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         84177                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        21.057367                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      250.150754                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095          84175    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::8192-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::69632-73727            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           80097                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         80097                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.466185                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.028138                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        6.338596                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           75079     93.74%     93.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            2441      3.05%     96.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             604      0.75%     97.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             241      0.30%     97.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             302      0.38%     98.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             483      0.60%     98.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             119      0.15%     98.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              48      0.06%     99.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              45      0.06%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              27      0.03%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              34      0.04%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              20      0.02%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             420      0.52%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              48      0.06%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              47      0.06%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              52      0.06%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              14      0.02%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               6      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               3      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             6      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             3      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            26      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             7      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           84177                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         84177                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.406501                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.998569                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        6.063432                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           78913     93.75%     93.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            2654      3.15%     96.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             594      0.71%     97.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             256      0.30%     97.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             356      0.42%     98.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             499      0.59%     98.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             111      0.13%     99.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              36      0.04%     99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              47      0.06%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              28      0.03%     99.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              36      0.04%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              26      0.03%     99.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             418      0.50%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              37      0.04%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              46      0.05%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              46      0.05%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              12      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               2      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               3      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             4      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            25      0.03%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             4      0.00%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::176-179             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::252-255             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           80097                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    88359532056                       # Total ticks spent queuing
-system.physmem.totMemAccLat              120280694556                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   8512310000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       51901.03                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::188-191             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::212-215             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-235             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           84177                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    95142418476                       # Total ticks spent queuing
+system.physmem.totMemAccLat              128377824726                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   8862775000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       53675.30                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  70651.03                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.30                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.89                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.28                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.89                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  72425.30                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.40                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.98                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.38                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.98                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.17                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.78                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1368420                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    660769                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.38                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  47.23                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15240061.90                       # Average gap between requests
-system.physmem.pageHitRate                      65.43                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 4037576760                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 2203042875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                6565556400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4550560560                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3090044124960                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1167667097760                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27361592107500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31636660066815                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.713051                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45518112024303                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1579777160000                       # Time in different power states
+system.physmem.avgWrQLen                        25.45                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1427545                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    690525                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.54                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  47.13                       # Row buffer hit rate for writes
+system.physmem.avgGap                     14599188.97                       # Average gap between requests
+system.physmem.pageHitRate                      65.42                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 4299372000                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 2345887500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                6942631800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4789082880                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3090047684880                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1174100419575                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27355981545000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31638506623635                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.751312                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45508743621503                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1579778980000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    211880830197                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    221302763997                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 4068693720                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 2220021375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                6713584800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               4514888160                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3090044124960                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1175652112905                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27354587708250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31637801134170                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.737170                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45506397156129                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1579777160000                       # Time in different power states
+system.physmem_1.actEnergy                 4165628040                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 2272912125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                6883242600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               4705588080                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3090047684880                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1168667714520                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27360747075750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31637489845995                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.729820                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45516677078545                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1579778980000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    223594850121                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    213370138955                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          384                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -383,15 +385,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              148829565                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         98586451                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          7318222                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups           104779817                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               69383898                       # Number of BTB hits
+system.cpu0.branchPred.lookups              147637418                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         98315773                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          7247820                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups           103619610                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               67413734                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            66.218762                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               20536581                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            208145                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            65.058857                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               20080737                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            195189                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -422,90 +424,84 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   633176                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               633176                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        15593                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3       103829                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore       293482                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       339694                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean  2057.107279                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 12691.149268                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-32767       334819     98.56%     98.56% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-65535         2369      0.70%     99.26% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-98303          775      0.23%     99.49% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::98304-131071         1050      0.31%     99.80% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-163839          325      0.10%     99.90% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::163840-196607          166      0.05%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-229375           47      0.01%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::229376-262143           24      0.01%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-294911           28      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::294912-327679           54      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::327680-360447           18      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::360448-393215           11      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::425984-458751            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::458752-491519            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::491520-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       339694                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       334006                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 19047.289570                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 15950.264710                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 18217.957975                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       329273     98.58%     98.58% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071         3345      1.00%     99.58% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607          501      0.15%     99.73% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143          607      0.18%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679          176      0.05%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215           53      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751           23      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287           15      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823           10      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       334006                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 554756829244                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.612373                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.535164                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1 553440790244     99.76%     99.76% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3    774310500      0.14%     99.90% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5    264675000      0.05%     99.95% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7    116251500      0.02%     99.97% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9     83135500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11     43553500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13     14917000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15     18677500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17       518500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 554756829244                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K       103830     86.94%     86.94% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        15593     13.06%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       119423                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       633176                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                   596316                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               596316                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        13005                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        90766                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore       267964                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       328352                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean  1967.306427                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 12140.663837                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-65535       326191     99.34%     99.34% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-131071         1511      0.46%     99.80% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-196607          485      0.15%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-262143           70      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-327679           71      0.02%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::327680-393215           17      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::393216-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::458752-524287            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       328352                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       293288                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 18414.921511                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 15494.626324                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 16461.439983                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535       290000     98.88%     98.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071         2364      0.81%     99.68% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607          368      0.13%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143          346      0.12%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679          119      0.04%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215           72      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751           12      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total       293288                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 554812439744                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.594659                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.537153                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1 553701545244     99.80%     99.80% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3    589103000      0.11%     99.91% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5    238633000      0.04%     99.95% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7    116174000      0.02%     99.97% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9     85227000      0.02%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11     46829500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13     15433000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15     19112000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17       363500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::18-19        19500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 554812439744                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        90767     87.47%     87.47% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        13005     12.53%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       103772                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       596316                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       633176                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       119423                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       596316                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       103772                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       119423                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       752599                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       103772                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       700088                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                   108615139                       # DTB read hits
-system.cpu0.dtb.read_misses                    465587                       # DTB read misses
-system.cpu0.dtb.write_hits                   88878639                       # DTB write hits
-system.cpu0.dtb.write_misses                   167589                       # DTB write misses
-system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                   107674804                       # DTB read hits
+system.cpu0.dtb.read_misses                    416109                       # DTB read misses
+system.cpu0.dtb.write_hits                   89240851                       # DTB write hits
+system.cpu0.dtb.write_misses                   180207                       # DTB write misses
+system.cpu0.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              45077                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1071                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   45162                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      301                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  7481                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              46383                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1087                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   37572                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      168                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  7516                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    44285                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses               109080726                       # DTB read accesses
-system.cpu0.dtb.write_accesses               89046228                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    38101                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses               108090913                       # DTB read accesses
+system.cpu0.dtb.write_accesses               89421058                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        197493778                       # DTB hits
-system.cpu0.dtb.misses                         633176                       # DTB misses
-system.cpu0.dtb.accesses                    198126954                       # DTB accesses
+system.cpu0.dtb.hits                        196915655                       # DTB hits
+system.cpu0.dtb.misses                         596316                       # DTB misses
+system.cpu0.dtb.accesses                    197511971                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -535,1164 +531,1160 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    92658                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                92658                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2         1215                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        67279                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore        10404                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples        82254                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1278.472779                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  8944.038924                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-32767        81396     98.96%     98.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-65535          425      0.52%     99.47% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-98303          229      0.28%     99.75% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-131071          180      0.22%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-163839            8      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::163840-196607            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-229375            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::229376-262143            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::294912-327679            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        82254                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        78898                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 24333.924814                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 20592.654972                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 23297.887242                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        76185     96.56%     96.56% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071         2219      2.81%     99.37% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607          249      0.32%     99.69% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143          140      0.18%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679           58      0.07%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           30      0.04%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        78898                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 417288840772                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.850626                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.356648                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0    62357623096     14.94%     14.94% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   354908424176     85.05%     99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2       20580000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3        1826000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4         387500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 417288840772                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        67279     98.23%     98.23% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         1215      1.77%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        68494                       # Table walker page sizes translated
+system.cpu0.itb.walker.walks                    85428                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                85428                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2          771                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        61190                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore        10178                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        75250                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1283.993355                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  9203.446829                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-32767        74460     98.95%     98.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-65535          428      0.57%     99.52% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-98303          166      0.22%     99.74% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-131071          158      0.21%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-163839           10      0.01%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::163840-196607            5      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-229375            9      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::229376-262143            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::262144-294911            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::294912-327679            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::327680-360447            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        75250                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        72139                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 23671.051720                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 20466.529400                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 20605.197168                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        70248     97.38%     97.38% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071         1514      2.10%     99.48% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607          196      0.27%     99.75% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143          111      0.15%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679           47      0.07%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           15      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        72139                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 421639244068                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.834946                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.371382                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0    69614918048     16.51%     16.51% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   352004823020     83.48%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2       17379000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3        2056500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4          67500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 421639244068                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        61190     98.76%     98.76% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M          771      1.24%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        61961                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        92658                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        92658                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        85428                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        85428                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        68494                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        68494                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       161152                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   234838704                       # ITB inst hits
-system.cpu0.itb.inst_misses                     92658                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        61961                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        61961                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       147389                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   231535487                       # ITB inst hits
+system.cpu0.itb.inst_misses                     85428                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              45077                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1071                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   33056                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              46383                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1087                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   26943                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   232539                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   216195                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               234931362                       # ITB inst accesses
-system.cpu0.itb.hits                        234838704                       # DTB hits
-system.cpu0.itb.misses                          92658                       # DTB misses
-system.cpu0.itb.accesses                    234931362                       # DTB accesses
-system.cpu0.numCycles                       826354541                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               231620915                       # ITB inst accesses
+system.cpu0.itb.hits                        231535487                       # DTB hits
+system.cpu0.itb.misses                          85428                       # DTB misses
+system.cpu0.itb.accesses                    231620915                       # DTB accesses
+system.cpu0.numCycles                       805724204                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          96417195                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     658349874                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                  148829565                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          89920479                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    686511551                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles               15731276                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                   2082372                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles              301509                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles      6642770                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       777478                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles       876995                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                234604466                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes              1859928                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                  30773                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         801475508                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.962394                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.215680                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          95731684                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     652075833                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                  147637418                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          87494471                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    667504198                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles               15546378                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                   1866411                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles              305738                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles      6228904                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       744813                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles       860245                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                231319013                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes              1833472                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                  28917                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         781015182                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.979576                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.220669                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               432057914     53.91%     53.91% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1               143320091     17.88%     71.79% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                50277190      6.27%     78.06% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3               175820313     21.94%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               414945915     53.13%     53.13% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1               142136658     18.20%     71.33% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                48870776      6.26%     77.59% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3               175061833     22.41%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           801475508                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.180104                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.796692                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles               115405888                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            393574581                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                246061591                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles             40857295                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               5576153                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved            21574429                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred              2334934                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             682682220                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts             25205347                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               5576153                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles               153705251                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               60022582                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles     253017805                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                248013590                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             81140127                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             664288996                       # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts              6473093                       # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents             10525488                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                404111                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                973821                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents              42702914                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents           12474                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands          634198397                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups           1026536806                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       783997445                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           728382                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            571881769                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                62316623                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts          17028830                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts      14786866                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 82376276                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads           108687128                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           92520441                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          9956675                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         8516242                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 640223835                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded           17051325                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                645202743                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued          2940745                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       58459841                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     38213470                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        295844                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    801475508                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.805019                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.062618                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           781015182                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.183236                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.809304                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles               113248081                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            377378437                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                245811555                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles             39067395                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               5509714                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved            21219272                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred              2308032                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             677494422                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts             25172258                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               5509714                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles               150635102                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               57564950                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles     243777898                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                246916319                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             76611199                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             659282826                       # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts              6463914                       # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents             10193503                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                302591                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                345572                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents              40114273                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents           11761                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands          627680154                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups           1013922393                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       779757811                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           794183                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            565536193                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                62143943                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts          16063927                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts      14023847                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 79290060                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads           107984972                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           92881396                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          9789553                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         8248701                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 636103677                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded           16216212                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                639991449                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued          2906968                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       58559234                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     38038909                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        288402                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    781015182                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.819435                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.071222                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          449210773     56.05%     56.05% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1          147559174     18.41%     74.46% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2          124891919     15.58%     90.04% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           71400363      8.91%     98.95% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            8407753      1.05%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5               5526      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          434056489     55.58%     55.58% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1          142602713     18.26%     73.83% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2          124298977     15.92%     89.75% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           71442121      9.15%     98.90% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            8609991      1.10%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5               4891      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      801475508                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      781015182                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu               66711662     45.46%     45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                 70956      0.05%     45.50% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                  22678      0.02%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc              31      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead              38740309     26.40%     71.92% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite             41215825     28.08%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu               67040735     45.54%     45.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                 53703      0.04%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                  26002      0.02%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc              14      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead              38206404     25.96%     71.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite             41875543     28.45%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu            441248281     68.39%     68.39% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult             1607382      0.25%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                84016      0.01%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                 12      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc         46433      0.01%     68.66% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.66% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.66% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.66% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead           111952136     17.35%     86.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           90264483     13.99%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass                1      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu            436779538     68.25%     68.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult             1517289      0.24%     68.48% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                81855      0.01%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  5      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt             23      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc         47604      0.01%     68.51% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.51% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.51% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.51% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead           110932479     17.33%     85.84% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           90632632     14.16%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             645202743                       # Type of FU issued
-system.cpu0.iq.rate                          0.780782                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                  146761461                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.227466                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads        2240404538                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        715416173                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    626754280                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads            1178660                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            474470                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       433754                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             791232333                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 731871                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads         3009936                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             639991449                       # Type of FU issued
+system.cpu0.iq.rate                          0.794306                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                  147202401                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.230007                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads        2209837146                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        710527601                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    621905864                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads            1270303                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            504170                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       467307                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             786402566                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 791283                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads         2962367                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads     13422485                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses        18059                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation       156652                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      6220264                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads     13371443                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses        16751                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation       153989                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      6295959                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      2933130                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked      5035754                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      2934112                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked      4671160                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               5576153                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                8424043                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              6068776                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          657405938                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles               5509714                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                7058035                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              5778589                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          652441938                       # Number of instructions dispatched to IQ
 system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts            108687128                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            92520441                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts          14528017                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 62220                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              5930416                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents        156652                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect       2211475                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect      3142674                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts             5354149                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            636790575                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts            108609704                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          7786358                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts            107984972                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            92881396                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts          13772451                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 68630                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              5639093                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents        153989                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect       2201982                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect      3098287                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts             5300269                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            631633854                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts            107665614                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          7773689                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       130778                       # number of nop insts executed
-system.cpu0.iew.exec_refs                   197486892                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches               120113448                       # Number of branches executed
-system.cpu0.iew.exec_stores                  88877188                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.770602                       # Inst execution rate
-system.cpu0.iew.wb_sent                     628006707                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    627188034                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                305309945                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                500537218                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       122049                       # number of nop insts executed
+system.cpu0.iew.exec_refs                   196907522                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches               119104624                       # Number of branches executed
+system.cpu0.iew.exec_stores                  89241908                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.783933                       # Inst execution rate
+system.cpu0.iew.wb_sent                     623170550                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    622373171                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                301982038                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                495557723                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.758982                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.609965                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.772439                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.609378                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts       51032011                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls       16755481                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts          5028737                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    791775198                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.756295                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.558039                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts       51133197                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls       15927810                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts          4984345                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    771348242                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.769770                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.572751                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    529474510     66.87%     66.87% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1    135713871     17.14%     84.01% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     58480062      7.39%     91.40% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3     19506672      2.46%     93.86% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4     13859320      1.75%     95.61% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      9636766      1.22%     96.83% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      6431343      0.81%     97.64% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7      3969096      0.50%     98.14% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8     14703558      1.86%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    513096769     66.52%     66.52% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1    132148168     17.13%     83.65% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     58179832      7.54%     91.19% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3     19360594      2.51%     93.70% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4     14004722      1.82%     95.52% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      9477117      1.23%     96.75% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      6473381      0.84%     97.59% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7      3935015      0.51%     98.10% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8     14672644      1.90%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    791775198                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           510225692                       # Number of instructions committed
-system.cpu0.commit.committedOps             598815315                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    771348242                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           504955538                       # Number of instructions committed
+system.cpu0.commit.committedOps             593760630                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                     181564818                       # Number of memory references committed
-system.cpu0.commit.loads                     95264643                       # Number of loads committed
-system.cpu0.commit.membars                    4026241                       # Number of memory barriers committed
-system.cpu0.commit.branches                 114090927                       # Number of branches committed
-system.cpu0.commit.fp_insts                    424114                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                549390032                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls            15322892                       # Number of function calls committed.
+system.cpu0.commit.refs                     181198957                       # Number of memory references committed
+system.cpu0.commit.loads                     94613526                       # Number of loads committed
+system.cpu0.commit.membars                    4060839                       # Number of memory barriers committed
+system.cpu0.commit.branches                 113014510                       # Number of branches committed
+system.cpu0.commit.fp_insts                    458000                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                545152087                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls            14971844                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu       415791168     69.44%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult        1352857      0.23%     69.66% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv           66520      0.01%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc        39952      0.01%     69.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       95264643     15.91%     85.59% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      86300175     14.41%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu       411193864     69.25%     69.25% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult        1260833      0.21%     69.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv           65173      0.01%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            8      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp           13      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt           21      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc        41761      0.01%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       94613526     15.93%     85.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      86585431     14.58%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        598815315                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events             14703558                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                  1422522153                       # The number of ROB reads
-system.cpu0.rob.rob_writes                 1309355495                       # The number of ROB writes
-system.cpu0.timesIdled                        1107002                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       24879033                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                 93793188049                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  510225692                       # Number of Instructions Simulated
-system.cpu0.committedOps                    598815315                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.619586                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.619586                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.617442                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.617442                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               751256572                       # number of integer regfile reads
-system.cpu0.int_regfile_writes              446675945                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   709287                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  346140                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                138932349                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes               139558794                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads             1422736351                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes              16846265                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements          6557508                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          508.746857                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          168230159                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          6558019                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            25.652588                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       1887096000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   508.746857                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.993646                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.993646                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          174                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          302                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           35                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        376736198                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       376736198                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     88222232                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       88222232                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     74841943                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      74841943                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       232729                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       232729                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       258353                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       258353                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1906592                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1906592                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1977838                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1977838                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    163064175                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       163064175                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    163296904                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      163296904                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      7298679                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      7298679                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      8186484                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      8186484                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       785305                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       785305                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       832077                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total       832077                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       303324                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       303324                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       192936                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       192936                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data     15485163                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      15485163                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data     16270468                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     16270468                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 111692276000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 111692276000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 148685242611                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 148685242611                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  79029404267                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  79029404267                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4531612500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   4531612500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4045324000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   4045324000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      3600000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      3600000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 260377518611                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 260377518611                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 260377518611                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 260377518611                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     95520911                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     95520911                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     83028427                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     83028427                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data      1018034                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1018034                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1090430                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1090430                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2209916                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      2209916                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2170774                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      2170774                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    178549338                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    178549338                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    179567372                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    179567372                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.076409                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.076409                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.098599                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.098599                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.771394                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.771394                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.763072                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.763072                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.137256                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.137256                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.088879                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.088879                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.086728                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.086728                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.090609                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.090609                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15303.081010                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15303.081010                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18162.283419                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 18162.283419                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 94978.474669                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 94978.474669                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14939.841556                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14939.841556                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20967.180827                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20967.180827                       # average StoreCondReq miss latency
+system.cpu0.commit.op_class_0::total        593760630                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events             14672644                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                  1397369391                       # The number of ROB reads
+system.cpu0.rob.rob_writes                 1299419087                       # The number of ROB writes
+system.cpu0.timesIdled                        1071653                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       24709022                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                 93813929115                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  504955538                       # Number of Instructions Simulated
+system.cpu0.committedOps                    593760630                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.595634                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.595634                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.626710                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.626710                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               746722296                       # number of integer regfile reads
+system.cpu0.int_regfile_writes              443322911                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   778801                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  335108                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                136612374                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes               137527114                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads             1389482326                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes              16167899                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements          6374252                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          504.525126                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          168612051                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          6374762                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            26.449937                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       1887138000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   504.525126                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.985401                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.985401                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          163                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          286                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           61                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses        375986188                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       375986188                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     87724319                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       87724319                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     75477797                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      75477797                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       231729                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       231729                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       266468                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       266468                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      2022541                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      2022541                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2052696                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      2052696                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    163202116                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       163202116                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    163433845                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      163433845                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      7197565                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      7197565                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      7724152                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      7724152                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       724383                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       724383                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       844788                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       844788                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       278463                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       278463                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       208196                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       208196                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data     14921717                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      14921717                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data     15646100                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     15646100                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 108620779500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 108620779500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 138974834179                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 138974834179                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  74732911806                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  74732911806                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4099802000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   4099802000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4408839000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   4408839000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      3050500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      3050500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 247595613679                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 247595613679                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 247595613679                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 247595613679                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     94921884                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     94921884                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     83201949                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     83201949                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       956112                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       956112                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1111256                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1111256                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2301004                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      2301004                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2260892                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      2260892                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    178123833                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    178123833                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    179079945                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    179079945                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.075826                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.075826                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.092836                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.092836                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.757634                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.757634                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.760210                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.760210                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.121018                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.121018                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.092086                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.092086                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.083772                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.083772                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.087369                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.087369                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15091.323177                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15091.323177                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17992.244868                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 17992.244868                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 88463.510142                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 88463.510142                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14722.968581                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14722.968581                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21176.386674                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21176.386674                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16814.645000                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 16814.645000                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16003.074934                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 16003.074934                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     24592023                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets     22766928                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           764014                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets         809850                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    32.187922                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    28.112525                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16592.970747                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 16592.970747                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15824.749534                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 15824.749534                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     23148520                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets     20510394                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           766944                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets         746852                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    30.182803                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    27.462461                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      4422416                       # number of writebacks
-system.cpu0.dcache.writebacks::total          4422416                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3749707                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      3749707                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      6590276                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      6590276                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         4547                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total         4547                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       153940                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       153940                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data     10339983                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total     10339983                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data     10339983                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total     10339983                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3548972                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3548972                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1596208                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1596208                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       778051                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       778051                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       827530                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       827530                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       149384                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       149384                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       192928                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       192928                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      5145180                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      5145180                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      5923231                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      5923231                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        20289                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20289                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        22269                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        22269                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        42558                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        42558                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  52135719000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  52135719000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  31476098425                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  31476098425                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  17784168000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  17784168000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  78021331267                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  78021331267                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   2035314000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   2035314000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3852473000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3852473000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      3523000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      3523000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  83611817425                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  83611817425                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 101395985425                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 101395985425                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3695888000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3695888000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3839366000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3839366000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7535254000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7535254000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.037154                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.037154                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019225                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019225                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.764268                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.764268                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.758902                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.758902                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.067597                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.067597                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.088875                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.088875                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028817                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.028817                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032986                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032986                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14690.372029                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14690.372029                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19719.296248                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19719.296248                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22857.329404                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22857.329404                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 94282.178612                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 94282.178612                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13624.712151                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13624.712151                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19968.449370                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19968.449370                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      4317679                       # number of writebacks
+system.cpu0.dcache.writebacks::total          4317679                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3700903                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      3700903                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      6185217                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      6185217                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         5102                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total         5102                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       141775                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       141775                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      9886120                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      9886120                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      9886120                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      9886120                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3496662                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3496662                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1538935                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1538935                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       717217                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       717217                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       839686                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       839686                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       136688                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       136688                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       208181                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       208181                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      5035597                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      5035597                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      5752814                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      5752814                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        21352                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        21352                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        23308                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        23308                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        44660                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        44660                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  50025996500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  50025996500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  29968345030                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  29968345030                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  17752964500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  17752964500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  73677446306                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  73677446306                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1889285500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1889285500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4200723000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4200723000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2985500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2985500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  79994341530                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  79994341530                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  97747306030                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  97747306030                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3896297500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3896297500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   4053651000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4053651000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7949948500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7949948500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036837                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036837                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018496                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018496                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.750139                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.750139                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.755619                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.755619                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059404                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059404                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.092079                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.092079                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028270                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.028270                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032124                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.032124                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14306.786444                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14306.786444                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19473.431321                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19473.431321                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24752.570700                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24752.570700                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 87744.045162                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 87744.045162                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13821.882682                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13821.882682                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20178.224718                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20178.224718                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16250.513573                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16250.513573                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17118.357434                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17118.357434                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182162.156834                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182162.156834                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172408.550002                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172408.550002                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177058.461394                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177058.461394                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15885.771147                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15885.771147                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16991.216130                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16991.216130                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182479.275946                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182479.275946                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173916.723872                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173916.723872                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 178010.490372                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 178010.490372                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          6585231                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.955630                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          227602766                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          6585743                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            34.559922                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      17287340000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.955630                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.replacements          6538162                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.955601                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          224372588                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          6538674                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            34.314693                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      17322639000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.955601                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999913                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999913                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          310                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          110                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          309                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           99                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        475737897                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       475737897                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    227602766                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      227602766                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    227602766                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       227602766                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    227602766                       # number of overall hits
-system.cpu0.icache.overall_hits::total      227602766                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      6973294                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      6973294                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      6973294                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       6973294                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      6973294                       # number of overall misses
-system.cpu0.icache.overall_misses::total      6973294                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  74030582287                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  74030582287                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  74030582287                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  74030582287                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  74030582287                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  74030582287                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    234576060                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    234576060                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    234576060                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    234576060                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    234576060                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    234576060                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.029727                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.029727                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.029727                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.029727                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.029727                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.029727                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10616.300171                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10616.300171                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10616.300171                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10616.300171                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10616.300171                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10616.300171                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs     10890869                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets          530                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs           815898                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        469120906                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       469120906                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    224372588                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      224372588                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    224372588                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       224372588                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    224372588                       # number of overall hits
+system.cpu0.icache.overall_hits::total      224372588                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      6918516                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      6918516                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      6918516                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       6918516                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      6918516                       # number of overall misses
+system.cpu0.icache.overall_misses::total      6918516                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  73530599413                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  73530599413                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  73530599413                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  73530599413                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  73530599413                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  73530599413                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    231291104                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    231291104                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    231291104                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    231291104                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    231291104                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    231291104                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.029913                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.029913                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.029913                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.029913                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.029913                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.029913                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10628.088366                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10628.088366                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10628.088366                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10628.088366                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10628.088366                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10628.088366                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs     10842770                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets          750                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs           802318                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets             10                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.348322                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets           53                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.514305                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets           75                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       387516                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       387516                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst       387516                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       387516                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst       387516                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       387516                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6585778                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      6585778                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      6585778                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      6585778                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      6585778                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      6585778                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       379817                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       379817                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst       379817                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       379817                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst       379817                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       379817                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6538699                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      6538699                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      6538699                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      6538699                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      6538699                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      6538699                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        21294                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        21294                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        21294                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        21294                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  67014306188                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  67014306188                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  67014306188                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  67014306188                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  67014306188                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  67014306188                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  66562536735                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  66562536735                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  66562536735                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  66562536735                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  66562536735                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  66562536735                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1863746498                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1863746498                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1863746498                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   1863746498                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028075                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028075                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028075                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.028075                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028075                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.028075                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10175.609653                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10175.609653                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10175.609653                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10175.609653                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10175.609653                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10175.609653                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028270                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028270                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028270                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.028270                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028270                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.028270                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10179.782971                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10179.782971                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10179.782971                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10179.782971                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10179.782971                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10179.782971                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87524.490373                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87524.490373                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      8598962                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      8934370                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit       290328                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      8420678                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      8427841                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit         6477                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage      1159342                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements         3030105                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16246.172494                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          22237347                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         3045780                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            7.301035                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle     15974403000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  7087.125273                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    75.689704                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker   100.487660                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4186.697540                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3865.106436                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   931.065881                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.432564                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.004620                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.006133                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.255536                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.235907                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.056828                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.991588                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1420                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023          100                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14155                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           86                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          252                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          649                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          433                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            3                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           77                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           11                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            9                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          206                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          782                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4799                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4726                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3642                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.086670                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.006104                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.863953                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       448543088                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      448543088                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       611768                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       192592                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total        804360                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks      4422408                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total      4422408                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       116889                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total       116889                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        39729                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total        39729                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data      1062033                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total      1062033                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5870980                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      5870980                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      3339122                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total      3339122                       # number of ReadSharedReq hits
-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       194533                       # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total       194533                       # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       611768                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       192592                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      5870980                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      4401155                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total       11076495                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       611768                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       192592                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      5870980                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      4401155                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total      11076495                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        14162                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker        11237                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        25399                       # number of ReadReq misses
-system.cpu0.l2cache.Writeback_misses::writebacks            6                       # number of Writeback misses
-system.cpu0.l2cache.Writeback_misses::total            6                       # number of Writeback misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       131236                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       131236                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       153191                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       153191                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.prefetcher.pfSpanPage      1085415                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements         2879166                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16210.435264                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          21867253                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2894850                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            7.553847                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle     16000650500                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks  7399.715112                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    85.098490                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    94.687899                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4348.179928                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3389.288950                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   893.464886                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.451643                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.005194                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.005779                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.265392                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.206866                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.054533                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.989406                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1404                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           92                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14188                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          100                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          251                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          619                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          434                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            4                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           68                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           15                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          213                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          757                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4744                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4803                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3671                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.085693                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005615                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.865967                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       440722520                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      440722520                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       580486                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       180915                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total        761401                       # number of ReadReq hits
+system.cpu0.l2cache.Writeback_hits::writebacks      4317669                       # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total      4317669                       # number of Writeback hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       115526                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total       115526                       # number of UpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        36643                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::total        36643                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       998559                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       998559                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5850201                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      5850201                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      3218899                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total      3218899                       # number of ReadSharedReq hits
+system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       227084                       # number of InvalidateReq hits
+system.cpu0.l2cache.InvalidateReq_hits::total       227084                       # number of InvalidateReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       580486                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker       180915                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      5850201                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data      4217458                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total       10829060                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       580486                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker       180915                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      5850201                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data      4217458                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total      10829060                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        13187                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         9856                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total        23043                       # number of ReadReq misses
+system.cpu0.l2cache.Writeback_misses::writebacks            5                       # number of Writeback misses
+system.cpu0.l2cache.Writeback_misses::total            5                       # number of Writeback misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       140809                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total       140809                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       171530                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total       171530                       # number of SCUpgradeReq misses
 system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            8                       # number of SCUpgradeFailReq misses
 system.cpu0.l2cache.SCUpgradeFailReq_misses::total            8                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       296814                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       296814                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       714775                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total       714775                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1134930                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total      1134930                       # number of ReadSharedReq misses
-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       631728                       # number of InvalidateReq misses
-system.cpu0.l2cache.InvalidateReq_misses::total       631728                       # number of InvalidateReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        14162                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker        11237                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       714775                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1431744                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total      2171918                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        14162                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker        11237                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       714775                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1431744                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      2171918                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    627635500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    557924000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total   1185559500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2881179498                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total   2881179498                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3211389999                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3211389999                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      3406498                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      3406498                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  17257972999                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total  17257972999                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  22144079998                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total  22144079998                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  43103483484                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total  43103483484                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  74596156500                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::total  74596156500                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    627635500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    557924000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst  22144079998                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data  60361456483                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total  83691095981                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    627635500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    557924000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst  22144079998                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data  60361456483                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  83691095981                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       625930                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       203829                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total       829759                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks      4422414                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total      4422414                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       248125                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       248125                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       192920                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       192920                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data       296756                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total       296756                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       688482                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total       688482                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1127441                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total      1127441                       # number of ReadSharedReq misses
+system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       611195                       # number of InvalidateReq misses
+system.cpu0.l2cache.InvalidateReq_misses::total       611195                       # number of InvalidateReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        13187                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker         9856                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst       688482                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data      1424197                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total      2135722                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        13187                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker         9856                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst       688482                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data      1424197                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total      2135722                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    534558500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    449764500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total    984323000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   3072018500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total   3072018500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3550746499                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3550746499                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2885498                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2885498                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  16106273500                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total  16106273500                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  21873259998                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total  21873259998                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  41772472980                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total  41772472980                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  70023878999                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::total  70023878999                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    534558500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    449764500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst  21873259998                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data  57878746480                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total  80736329478                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    534558500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    449764500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  21873259998                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data  57878746480                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  80736329478                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       593673                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       190771                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total       784444                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::writebacks      4317674                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total      4317674                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       256335                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total       256335                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       208173                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total       208173                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            8                       # number of SCUpgradeFailReq accesses(hits+misses)
 system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            8                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1358847                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total      1358847                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      6585755                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      6585755                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4474052                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total      4474052                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       826261                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::total       826261                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       625930                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       203829                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      6585755                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data      5832899                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total     13248413                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       625930                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       203829                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      6585755                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data      5832899                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     13248413                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.022626                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.055130                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.030610                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1295315                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total      1295315                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      6538683                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      6538683                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4346340                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total      4346340                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       838279                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::total       838279                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       593673                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       190771                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      6538683                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data      5641655                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total     12964782                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       593673                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       190771                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      6538683                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data      5641655                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total     12964782                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.022213                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.051664                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.029375                       # miss rate for ReadReq accesses
 system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000001                       # miss rate for Writeback accesses
 system.cpu0.l2cache.Writeback_miss_rate::total     0.000001                       # miss rate for Writeback accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.528911                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.528911                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.794065                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.794065                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.549316                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.549316                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.823978                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.823978                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.218431                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.218431                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.108533                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.108533                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.253669                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.253669                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.764562                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.764562                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.022626                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.055130                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.108533                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.245460                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.163938                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.022626                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.055130                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.108533                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.245460                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.163938                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 44318.281316                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 49650.618492                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 46677.408559                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21954.185574                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21954.185574                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20963.307237                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20963.307237                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 425812.250000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 425812.250000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 58144.066651                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 58144.066651                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 30980.490361                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 30980.490361                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37978.979747                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37978.979747                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 118082.713605                       # average InvalidateReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 118082.713605                       # average InvalidateReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 44318.281316                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 49650.618492                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30980.490361                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42159.391960                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 38533.266901                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 44318.281316                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 49650.618492                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30980.490361                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42159.391960                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 38533.266901                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs          232                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.229099                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.229099                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.105294                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.105294                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.259400                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.259400                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.729107                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.729107                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.022213                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.051664                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.105294                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.252443                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.164733                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.022213                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.051664                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.105294                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.252443                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.164733                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 40536.778646                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 45633.573458                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 42716.790348                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21816.918663                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21816.918663                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20700.440150                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20700.440150                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 360687.250000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 360687.250000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54274.466228                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54274.466228                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 31770.271406                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 31770.271406                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37050.695318                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37050.695318                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 114568.802099                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 114568.802099                       # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 40536.778646                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 45633.573458                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31770.271406                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 40639.564948                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 37802.827090                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 40536.778646                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 45633.573458                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31770.271406                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 40639.564948                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 37802.827090                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs         1651                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               3                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               6                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    77.333333                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs   275.166667                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1656758                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1656758                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            4                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker          144                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total          148                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        25414                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total        25414                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            4                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            4                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         5426                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         5426                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data           23                       # number of InvalidateReq MSHR hits
-system.cpu0.l2cache.InvalidateReq_mshr_hits::total           23                       # number of InvalidateReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            4                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker          144                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            4                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data        30840                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total        30992                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            4                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker          144                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            4                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data        30840                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total        30992                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        14158                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker        11093                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        25251                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.Writeback_mshr_misses::writebacks            6                       # number of Writeback MSHR misses
-system.cpu0.l2cache.Writeback_mshr_misses::total            6                       # number of Writeback MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks       124422                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::total       124422                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       859401                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       859401                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       131236                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       131236                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       153191                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       153191                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.writebacks::writebacks      1533538                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1533538                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            3                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker          198                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::total          201                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        18639                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total        18639                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            9                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            9                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         6125                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         6125                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            3                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker          198                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            9                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data        24764                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total        24974                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            3                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker          198                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            9                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data        24764                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total        24974                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        13184                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         9658                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total        22842                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.Writeback_mshr_misses::writebacks            5                       # number of Writeback MSHR misses
+system.cpu0.l2cache.Writeback_mshr_misses::total            5                       # number of Writeback MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks       117912                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::total       117912                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       787872                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       787872                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       140809                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total       140809                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       171530                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       171530                       # number of SCUpgradeReq MSHR misses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            8                       # number of SCUpgradeFailReq MSHR misses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            8                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       271400                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       271400                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       714771                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       714771                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1129504                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1129504                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       631705                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::total       631705                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        14158                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker        11093                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       714771                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1400904                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total      2140926                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        14158                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker        11093                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       714771                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1400904                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       859401                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total      3000327                       # number of overall MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       278117                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total       278117                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       688473                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       688473                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1121316                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1121316                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       611195                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::total       611195                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        13184                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         9658                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       688473                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1399433                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total      2110748                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        13184                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         9658                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       688473                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1399433                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       787872                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total      2898620                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        21294                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        20289                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        41583                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        22269                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        22269                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        21352                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        42646                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        23308                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        23308                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        21294                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        42558                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        63852                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    542595500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    483807000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   1026402500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  56082760333                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  56082760333                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2730207494                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2730207494                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2385366995                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2385366995                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2944498                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2944498                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  12497558999                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  12497558999                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  17855117998                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  17855117998                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  35928472484                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  35928472484                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  70805243000                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  70805243000                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    542595500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    483807000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  17855117998                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  48426031483                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total  67307551981                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    542595500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    483807000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  17855117998                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  48426031483                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  56082760333                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total 123390312314                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        44660                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        65954                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    455402500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    383158000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    838560500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  47401942947                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  47401942947                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2887874997                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2887874997                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2620767495                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2620767495                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2495498                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2495498                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  11968940000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  11968940000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  17742237498                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  17742237498                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  34600470980                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  34600470980                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  66356708999                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  66356708999                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    455402500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    383158000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  17742237498                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  46569410980                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total  65150208978                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    455402500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    383158000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  17742237498                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  46569410980                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  47401942947                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total 112552151925                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1704040500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3533504500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   5237545000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3666920967                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3666920967                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3725362000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   5429402500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3873404967                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3873404967                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   1704040500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   7200425467                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   8904465967                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.022619                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.054423                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.030432                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   7598766967                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   9302807467                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.022208                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.050626                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.029119                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for Writeback accesses
 system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000001                       # mshr miss rate for Writeback accesses
 system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.528911                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.528911                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.794065                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.794065                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.549316                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.549316                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.823978                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.823978                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.199728                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.199728                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.108533                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.108533                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.252457                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.252457                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.764534                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.764534                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.022619                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.054423                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.108533                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.240173                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.161599                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.022619                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.054423                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.108533                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.240173                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.214710                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.214710                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.105292                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.105292                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.257991                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.257991                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.729107                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.729107                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.022208                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.050626                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.105292                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.248054                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.162806                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.022208                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.050626                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.105292                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.248054                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.226467                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 38324.304280                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 43613.720364                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 40647.994139                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65257.964947                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65257.964947                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20803.799979                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20803.799979                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15571.195403                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15571.195403                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 368062.250000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 368062.250000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 46048.485626                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 46048.485626                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 24980.193654                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 24980.193654                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31809.070604                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31809.070604                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 112085.930933                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 112085.930933                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 38324.304280                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43613.720364                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24980.193654                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34567.701629                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31438.523322                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 38324.304280                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43613.720364                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24980.193654                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34567.701629                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65257.964947                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41125.621412                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.223576                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34542.058556                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 39672.603023                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 36711.343140                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60164.522850                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60164.522850                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20509.164876                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20509.164876                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15278.770448                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15278.770448                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 311937.250000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 311937.250000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43035.628890                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43035.628890                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 25770.418735                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 25770.418735                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30857.020661                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30857.020661                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 108568.802099                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 108568.802099                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34542.058556                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 39672.603023                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25770.418735                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33277.342309                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30865.934246                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34542.058556                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 39672.603023                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25770.418735                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33277.342309                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60164.522850                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38829.564388                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174158.632757                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 125953.995623                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164664.824060                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164664.824060                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174473.679281                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 127313.288468                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 166183.497812                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166183.497812                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 169190.879905                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 139454.769890                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 170147.043596                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 141049.935819                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq       1048889                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     12194005                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadReq        984567                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     11961948                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        38264                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        22269                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback      8425423                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict     11622390                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq      1249461                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       495211                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       344893                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       512947                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        38204                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        23308                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback      8463420                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict     11561533                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq      1016095                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp            5                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       502894                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       380729                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       540434                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           79                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          148                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1710859                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1368930                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      6585778                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq      6660291                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq       932989                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp       826261                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     19798041                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     21027852                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       446745                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1372185                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         42644823                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    421828960                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    663719558                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1630632                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      5007440                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1092186590                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                   11579815                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     39116658                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       1.312501                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.463513                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          136                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1691199                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1306018                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      6538699                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      6804200                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       945007                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       838279                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     19656927                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     20547872                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       414026                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1295337                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         41914162                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    418816352                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    645201790                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1526168                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4749384                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1070293694                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                   11878703                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     38928585                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       1.320254                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.466574                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1          26892655     68.75%     68.75% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2          12224003     31.25%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1          26461563     67.97%     67.97% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2          12467022     32.03%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      39116658                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   18374497429                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      38928585                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   18022605428                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    206346476                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    218178978                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   9904865164                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   9834328997                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   9419389746                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   9151913574                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    243194937                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    223594319                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    746720066                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    702320680                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups              121710225                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         81714662                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          5979961                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            85476181                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               55576245                       # Number of BTB hits
+system.cpu1.branchPred.lookups              127974219                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         85721226                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          6122377                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            91131353                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               60172902                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            65.019570                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               16076930                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            165894                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            66.028760                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               17085083                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            181731                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1722,83 +1714,89 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   527361                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               527361                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        10839                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        84415                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore       237711                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       289650                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean  2083.972035                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 12311.346834                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-65535       287768     99.35%     99.35% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-131071         1260      0.44%     99.79% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-196607          464      0.16%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::196608-262143           78      0.03%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-327679           55      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::327680-393215           21      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::393216-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::458752-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       289650                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       263786                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 17712.334999                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 15356.267972                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 12186.421874                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535       262356     99.46%     99.46% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1127      0.43%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607          155      0.06%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143           73      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679           35      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215           26      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       263786                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 425904638364                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.594204                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.544845                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1 424921434364     99.77%     99.77% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3    524417000      0.12%     99.89% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5    206354500      0.05%     99.94% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7    102255000      0.02%     99.96% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9     73118500      0.02%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11     43959500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13     13868000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15     18884000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17       347500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 425904638364                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        84415     88.62%     88.62% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        10839     11.38%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total        95254                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       527361                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks                   610901                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               610901                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        15580                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3       103695                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore       293448                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       317453                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean  2113.928676                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 12461.929670                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-32767       312797     98.53%     98.53% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-65535         2424      0.76%     99.30% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-98303          700      0.22%     99.52% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::98304-131071          857      0.27%     99.79% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-163839          351      0.11%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::163840-196607          153      0.05%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-229375           53      0.02%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::229376-262143           19      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-294911           21      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::294912-327679           57      0.02%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::327680-360447           14      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::360448-393215            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::425984-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::458752-491519            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       317453                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       338102                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 18568.539967                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 16066.889111                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 14911.003076                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535       335377     99.19%     99.19% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1909      0.56%     99.76% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607          302      0.09%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143          312      0.09%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679          121      0.04%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215           38      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751           24      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       338102                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 438848021252                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.580073                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.553130                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1 437543459752     99.70%     99.70% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3    782991500      0.18%     99.88% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5    243923500      0.06%     99.94% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7    110155500      0.03%     99.96% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9     88476500      0.02%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11     41634500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13     16681500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15     20049000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17       649500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 438848021252                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K       103695     86.94%     86.94% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        15580     13.06%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       119275                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       610901                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       527361                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        95254                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       610901                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       119275                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        95254                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       622615                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       119275                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       730176                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    90076123                       # DTB read hits
-system.cpu1.dtb.read_misses                    364024                       # DTB read misses
-system.cpu1.dtb.write_hits                   74326349                       # DTB write hits
-system.cpu1.dtb.write_misses                   163337                       # DTB write misses
-system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                    94901630                       # DTB read hits
+system.cpu1.dtb.read_misses                    438242                       # DTB read misses
+system.cpu1.dtb.write_hits                   77470080                       # DTB write hits
+system.cpu1.dtb.write_misses                   172659                       # DTB write misses
+system.cpu1.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              45077                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1071                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   33241                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      185                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  5418                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              46383                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1087                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   42323                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      163                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  7630                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    36861                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                90440147                       # DTB read accesses
-system.cpu1.dtb.write_accesses               74489686                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    42941                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                95339872                       # DTB read accesses
+system.cpu1.dtb.write_accesses               77642739                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        164402472                       # DTB hits
-system.cpu1.dtb.misses                         527361                       # DTB misses
-system.cpu1.dtb.accesses                    164929833                       # DTB accesses
+system.cpu1.dtb.hits                        172371710                       # DTB hits
+system.cpu1.dtb.misses                         610901                       # DTB misses
+system.cpu1.dtb.accesses                    172982611                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1828,1155 +1826,1161 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    77446                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                77446                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          594                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        55102                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore         9325                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples        68121                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean  1127.809339                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  8184.124599                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-65535        67907     99.69%     99.69% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-131071          190      0.28%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-196607            8      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::196608-262143           12      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-327679            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        68121                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        65021                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 21947.540026                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 19801.580238                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 14876.528667                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        64283     98.86%     98.86% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071          594      0.91%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607           78      0.12%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143           35      0.05%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679           16      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                    86285                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                86285                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2         1166                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        62692                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore         9855                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples        76430                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1337.426403                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev 10105.936208                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-32767        75617     98.94%     98.94% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-65535          383      0.50%     99.44% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-98303          204      0.27%     99.70% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::98304-131071          174      0.23%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::131072-163839            8      0.01%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::163840-196607           13      0.02%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::196608-229375            9      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::229376-262143            9      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-294911            1      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::294912-327679            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::327680-360447            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::360448-393215            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        76430                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        73713                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 23336.867310                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 20402.005732                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 19525.264050                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        72001     97.68%     97.68% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071         1393      1.89%     99.57% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607          144      0.20%     99.76% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143          112      0.15%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679           36      0.05%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215           17      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751            7      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        65021                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 387249857200                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.854665                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.352569                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    56297043096     14.54%     14.54% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1   330938122104     85.46%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2       13360500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3        1244000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4          37500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::5          50000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 387249857200                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        55102     98.93%     98.93% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          594      1.07%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        55696                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkCompletionTime::total        73713                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 417370190772                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.853526                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.353735                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    61155433348     14.65%     14.65% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1   356194673424     85.34%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2       18786000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3        1262500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4          35500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 417370190772                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        62692     98.17%     98.17% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M         1166      1.83%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        63858                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        77446                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        77446                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        86285                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        86285                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        55696                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        55696                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       133142                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   191622824                       # ITB inst hits
-system.cpu1.itb.inst_misses                     77446                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        63858                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        63858                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       150143                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   203133106                       # ITB inst hits
+system.cpu1.itb.inst_misses                     86285                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              45077                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1071                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   23450                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              46383                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1087                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   30560                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   204512                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   224551                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               191700270                       # ITB inst accesses
-system.cpu1.itb.hits                        191622824                       # DTB hits
-system.cpu1.itb.misses                          77446                       # DTB misses
-system.cpu1.itb.accesses                    191700270                       # DTB accesses
-system.cpu1.numCycles                       652098782                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               203219391                       # ITB inst accesses
+system.cpu1.itb.hits                        203133106                       # DTB hits
+system.cpu1.itb.misses                          86285                       # DTB misses
+system.cpu1.itb.accesses                    203219391                       # DTB accesses
+system.cpu1.numCycles                       708901373                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          77581821                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     539946872                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                  121710225                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          71653175                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                    543040637                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles               12931684                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                   1632229                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles              244335                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles      5898534                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       685251                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles       721414                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                191398691                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes              1512045                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                  26398                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         636270063                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.997205                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.224602                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          79210227                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     569056404                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                  127974219                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          77257985                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                    596249525                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles               13297978                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                   1936888                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles              233747                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles      6483042                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       760521                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles       721953                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                202886748                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes              1527721                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                  28660                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         692244892                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.964370                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.215604                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               332513921     52.26%     52.26% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1               118489139     18.62%     70.88% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                39798398      6.25%     77.14% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3               145468605     22.86%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               371999522     53.74%     53.74% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1               125145403     18.08%     71.82% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                42864856      6.19%     78.01% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3               152235111     21.99%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           636270063                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.186644                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.828014                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                93717841                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles            303303779                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                200797968                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles             33854734                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               4595741                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved            17115460                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred              1907562                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts             560589350                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts             20699594                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               4595741                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles               125431952                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               39494252                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles     209485809                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                202527049                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             54735260                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts             545352444                       # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts              5255771                       # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents              8923159                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                236326                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                251378                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents              23064401                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents           10277                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands          518904030                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            842346329                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       645518990                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           772636                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps            467533188                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                51370836                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts          14457491                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts      12765800                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 68374020                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            90157460                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           77360116                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          8411660                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         7288721                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                 524903956                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded           14739695                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                529653671                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued          2395600                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       48736249                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     31414673                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        252865                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    636270063                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.832435                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.069985                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           692244892                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.180525                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.802730                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                98103528                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles            343550458                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                207545620                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles             38285921                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               4759365                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved            18045337                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred              1925812                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts             590182189                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts             20993149                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               4759365                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles               132299037                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               44198902                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles     235238981                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                211136719                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles             64611888                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts             574391592                       # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts              5359861                       # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents              9789729                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                401271                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                868513                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents              28581746                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents           10968                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands          549201958                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            896745625                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       678703153                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           702078                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps            496570478                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                52631474                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts          16637084                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts      14688391                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 76542594                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            94434816                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           80595349                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          8923483                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         7689116                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                 551758554                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded           16802636                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                558923093                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued          2479703                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       49836281                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     32327580                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        272404                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    692244892                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.807407                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.056587                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0          346386206     54.44%     54.44% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1          123009687     19.33%     73.77% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2          101156259     15.90%     89.67% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3           58544050      9.20%     98.87% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            7169989      1.13%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5               3872      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0          382813800     55.30%     55.30% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1          135617529     19.59%     74.89% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2          105540069     15.25%     90.14% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3           60873310      8.79%     98.93% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            7395424      1.07%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5               4760      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      636270063                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      692244892                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu               53039712     43.72%     43.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                 43863      0.04%     43.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                  10928      0.01%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc              13      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead              32632716     26.90%     70.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite             35589452     29.34%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu               54751854     43.35%     43.35% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                 59874      0.05%     43.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                   7206      0.01%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc              22      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     43.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead              34635726     27.43%     70.83% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite             36835867     29.17%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass                2      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu            360085884     67.99%     67.99% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult             1163863      0.22%     68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                64768      0.01%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt             25      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc         79405      0.01%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            92781248     17.52%     85.75% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           75478453     14.25%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass               22      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu            381080184     68.18%     68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult             1279374      0.23%     68.41% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                67457      0.01%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc         77518      0.01%     68.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            97747450     17.49%     85.92% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           78671088     14.08%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total             529653671                       # Type of FU issued
-system.cpu1.iq.rate                          0.812229                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                  121316684                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.229049                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads        1818002123                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes        587994704                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses    514426397                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads            1287564                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            520666                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       480327                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses             650175074                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 795279                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads         2341712                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total             558923093                       # Type of FU issued
+system.cpu1.iq.rate                          0.788436                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                  126290549                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.225953                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads        1937670345                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes        618057050                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses    542680096                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads            1190983                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            486822                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       443064                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses             684478646                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 734974                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads         2497447                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads     11071583                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses        15258                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation       136605                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      5366212                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads     11391566                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses        16442                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation       147287                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      5480411                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads      2403910                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      3823950                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads      2518337                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      4561530                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               4595741                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                5738657                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              1529256                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts          539757610                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles               4759365                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                7377288                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles              1779487                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts          568686865                       # Number of instructions dispatched to IQ
 system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             90157460                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            77360116                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts          12526602                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 63879                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents              1404906                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents        136605                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect       1813433                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect      2553447                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts             4366880                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts            522753556                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             90069669                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          6385743                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts             94434816                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            80595349                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts          14436432                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 67561                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents              1633321                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents        147287                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect       1861843                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect      2641662                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts             4503505                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts            551808656                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             94901612                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          6513481                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       113959                       # number of nop insts executed
-system.cpu1.iew.exec_refs                   164397082                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                97927466                       # Number of branches executed
-system.cpu1.iew.exec_stores                  74327413                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.801648                       # Inst execution rate
-system.cpu1.iew.wb_sent                     515591253                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                    514906724                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                248837648                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                408235008                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       125675                       # number of nop insts executed
+system.cpu1.iew.exec_refs                   172371354                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches               103407043                       # Number of branches executed
+system.cpu1.iew.exec_stores                  77469742                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.778400                       # Inst execution rate
+system.cpu1.iew.wb_sent                     543849746                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                    543123160                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                263131919                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                431737287                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.789615                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.609545                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.766148                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.609472                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts       42654937                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls       14486830                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts          4109860                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    628197112                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.781454                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.577369                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts       43653536                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls       16530232                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts          4232753                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    683948716                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.758427                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.554925                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0    412381395     65.65%     65.65% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1    112703002     17.94%     83.59% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2     47448288      7.55%     91.14% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3     15899123      2.53%     93.67% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4     11433065      1.82%     95.49% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      7648889      1.22%     96.71% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      5327937      0.85%     97.56% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7      3177183      0.51%     98.06% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8     12178230      1.94%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    453202569     66.26%     66.26% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1    123078137     18.00%     84.26% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2     49564580      7.25%     91.50% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3     16593049      2.43%     93.93% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4     11718092      1.71%     95.64% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      8048900      1.18%     96.82% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      5489767      0.80%     97.62% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7      3345988      0.49%     98.11% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8     12907634      1.89%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    628197112                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts           416485993                       # Number of instructions committed
-system.cpu1.commit.committedOps             490907395                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    683948716                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts           441056280                       # Number of instructions committed
+system.cpu1.commit.committedOps             518724902                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                     151079780                       # Number of memory references committed
-system.cpu1.commit.loads                     79085876                       # Number of loads committed
-system.cpu1.commit.membars                    3553216                       # Number of memory barriers committed
-system.cpu1.commit.branches                  92889165                       # Number of branches committed
-system.cpu1.commit.fp_insts                    468052                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                450541794                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls            11963242                       # Number of function calls committed.
+system.cpu1.commit.refs                     158158187                       # Number of memory references committed
+system.cpu1.commit.loads                     83043249                       # Number of loads committed
+system.cpu1.commit.membars                    3695786                       # Number of memory barriers committed
+system.cpu1.commit.branches                  98284315                       # Number of branches committed
+system.cpu1.commit.fp_insts                    431344                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                475340146                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls            12767541                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu       338771351     69.01%     69.01% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult         933774      0.19%     69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv           51484      0.01%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc        70964      0.01%     69.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       79085876     16.11%     85.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      71993904     14.67%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu       359393863     69.28%     69.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult        1051243      0.20%     69.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv           53001      0.01%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc        68608      0.01%     69.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       83043249     16.01%     85.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      75114938     14.48%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total        490907395                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events             12178230                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                  1145716069                       # The number of ROB reads
-system.cpu1.rob.rob_writes                 1075160501                       # The number of ROB writes
-system.cpu1.timesIdled                         888623                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                       15828719                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                 93967443806                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                  416485993                       # Number of Instructions Simulated
-system.cpu1.committedOps                    490907395                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.565716                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.565716                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.638685                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.638685                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               618570567                       # number of integer regfile reads
-system.cpu1.int_regfile_writes              365658107                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                   762313                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                  433520                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                112664520                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes               113502103                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads             1139246007                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes              14605610                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements          5006870                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          430.966811                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          140806906                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5007379                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            28.119882                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8489665359000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   430.966811                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.841732                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.841732                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          370                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           39                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        313329932                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       313329932                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     73478112                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       73478112                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     62922278                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      62922278                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       161792                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       161792                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data        60224                       # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total        60224                       # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1740937                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1740937                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1748633                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1748633                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    136400390                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       136400390                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    136562182                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      136562182                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      5886586                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      5886586                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      6650181                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      6650181                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       625497                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       625497                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data       420972                       # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total       420972                       # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       235563                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       235563                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       185045                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       185045                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data     12536767                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total      12536767                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data     13162264                       # number of overall misses
-system.cpu1.dcache.overall_misses::total     13162264                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  84434005000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  84434005000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 115550287907                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 115550287907                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  14693527706                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total  14693527706                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   3280765000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   3280765000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   3888950500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   3888950500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3327000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3327000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 199984292907                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 199984292907                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 199984292907                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 199984292907                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     79364698                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     79364698                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     69572459                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     69572459                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       787289                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       787289                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       481196                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total       481196                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1976500                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      1976500                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1933678                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      1933678                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    148937157                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    148937157                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    149724446                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    149724446                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.074171                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.074171                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.095586                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.095586                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.794495                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.794495                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.874845                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total     0.874845                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.119182                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.119182                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.095696                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.095696                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.084175                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.084175                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.087910                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.087910                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14343.459010                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14343.459010                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17375.510216                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 17375.510216                       # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 34903.812382                       # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 34903.812382                       # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13927.335787                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13927.335787                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21016.241995                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21016.241995                       # average StoreCondReq miss latency
+system.cpu1.commit.op_class_0::total        518724902                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events             12907634                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                  1229236643                       # The number of ROB reads
+system.cpu1.rob.rob_writes                 1133012460                       # The number of ROB writes
+system.cpu1.timesIdled                         937113                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                       16656481                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                 93910751930                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                  441056280                       # Number of Instructions Simulated
+system.cpu1.committedOps                    518724902                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.607281                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.607281                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.622169                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.622169                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               651831389                       # number of integer regfile reads
+system.cpu1.int_regfile_writes              384949596                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                   687947                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                  437000                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                121245693                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes               121813302                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads             1231894475                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes              16565900                       # number of misc regfile writes
+system.cpu1.dcache.tags.replacements          5500590                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          430.004525                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          146156295                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          5501102                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            26.568548                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8485200468500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   430.004525                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.839853                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.839853                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          388                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses        327866519                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       327866519                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     76697860                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       76697860                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     64975008                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      64975008                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       170492                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       170492                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data        54492                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total        54492                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1753772                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1753772                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1761808                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1761808                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    141672868                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       141672868                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    141843360                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      141843360                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      6400758                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      6400758                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      7699637                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      7699637                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       744836                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       744836                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       409878                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       409878                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       258549                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       258549                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       208576                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       208576                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data     14100395                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total      14100395                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data     14845231                       # number of overall misses
+system.cpu1.dcache.overall_misses::total     14845231                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  92687894000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  92687894000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 138325220262                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 138325220262                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  20294196326                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  20294196326                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   4013433500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   4013433500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4392601500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   4392601500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3408500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3408500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 231013114262                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 231013114262                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 231013114262                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 231013114262                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     83098618                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     83098618                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     72674645                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     72674645                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       915328                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       915328                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       464370                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       464370                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2012321                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      2012321                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1970384                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      1970384                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    155773263                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    155773263                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    156688591                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    156688591                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.077026                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.077026                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.105947                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.105947                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.813737                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.813737                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.882654                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.882654                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.128483                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.128483                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.105856                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.105856                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.090519                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.090519                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.094744                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.094744                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14480.768371                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14480.768371                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17965.161249                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 17965.161249                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 49512.772889                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 49512.772889                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15522.912485                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15522.912485                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21059.956563                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21059.956563                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15951.823377                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 15951.823377                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15193.760960                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 15193.760960                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs      3842918                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets     18319630                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs           344375                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets         666302                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    11.159109                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    27.494484                       # average number of cycles each access was blocked
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16383.449844                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 16383.449844                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15561.436145                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 15561.436145                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs      5682783                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets     23004045                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs           345925                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets         792691                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    16.427789                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    29.020192                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      3252895                       # number of writebacks
-system.cpu1.dcache.writebacks::total          3252895                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3007786                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total      3007786                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      5379273                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total      5379273                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         3474                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::total         3474                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       121870                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total       121870                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      8387059                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      8387059                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      8387059                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      8387059                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2878800                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      2878800                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1270908                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1270908                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       625447                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       625447                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       417498                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total       417498                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       113693                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       113693                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       185035                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       185035                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4149708                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4149708                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      4775155                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      4775155                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        18068                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        18068                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        15995                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        15995                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        34063                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        34063                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  38840223500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  38840223500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  22606708667                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  22606708667                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13883914500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13883914500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  14151578206                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  14151578206                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1521353000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1521353000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3703986500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3703986500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3256000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3256000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  61446932167                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  61446932167                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  75330846667                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  75330846667                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2814873000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2814873000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2522981000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   2522981000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   5337854000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   5337854000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036273                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036273                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018267                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018267                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.794431                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.794431                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.867626                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.867626                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.057522                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.057522                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.095691                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.095691                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027862                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.027862                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031893                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.031893                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13491.810303                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13491.810303                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17787.840400                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17787.840400                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22198.386914                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22198.386914                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 33896.158080                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 33896.158080                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13381.237191                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13381.237191                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20017.761505                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20017.761505                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      3566261                       # number of writebacks
+system.cpu1.dcache.writebacks::total          3566261                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3293272                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total      3293272                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      6267237                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total      6267237                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         2938                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::total         2938                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       130878                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total       130878                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      9560509                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      9560509                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      9560509                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      9560509                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3107486                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      3107486                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1432400                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1432400                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       744751                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       744751                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       406940                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       406940                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       127671                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       127671                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       208566                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       208566                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4539886                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4539886                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      5284637                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      5284637                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        16935                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total        16935                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        14896                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total        14896                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        31831                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        31831                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  43040497000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  43040497000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  26400232128                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  26400232128                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  15655161500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  15655161500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  19798456326                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  19798456326                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1838541000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1838541000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4184106500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4184106500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3337500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3337500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  69440729128                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  69440729128                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  85095890628                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  85095890628                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2604403500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2604403500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2300537000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   2300537000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   4904940500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   4904940500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.037395                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.037395                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.019710                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.019710                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.813644                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.813644                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.876327                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.876327                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.063445                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.063445                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.105850                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.105850                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.029144                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.029144                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033727                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.033727                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13850.584363                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13850.584363                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18430.768031                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18430.768031                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21020.665296                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21020.665296                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 48652.028127                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 48652.028127                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14400.615645                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14400.615645                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20061.306733                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20061.306733                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14807.531558                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14807.531558                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15775.581456                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15775.581456                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 155793.280939                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 155793.280939                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157735.604877                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 157735.604877                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 156705.340105                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 156705.340105                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15295.698863                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15295.698863                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16102.504416                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16102.504416                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 153788.219663                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 153788.219663                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154439.916756                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154439.916756                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 154093.195313                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 154093.195313                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          5324088                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          501.812989                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          185755475                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          5324600                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            34.886278                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8495816906000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.812989                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.980103                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.980103                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements          5403947                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          501.811782                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          197154720                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          5404459                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            36.480010                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8495886874000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.811782                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.980101                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.980101                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          344                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           57                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0          112                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          334                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           66                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        388109731                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       388109731                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    185755475                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      185755475                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    185755475                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       185755475                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    185755475                       # number of overall hits
-system.cpu1.icache.overall_hits::total      185755475                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      5637082                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      5637082                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      5637082                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       5637082                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      5637082                       # number of overall misses
-system.cpu1.icache.overall_misses::total      5637082                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  58647080384                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  58647080384                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  58647080384                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  58647080384                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  58647080384                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  58647080384                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    191392557                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    191392557                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    191392557                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    191392557                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    191392557                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    191392557                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.029453                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.029453                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.029453                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.029453                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.029453                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.029453                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10403.801184                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 10403.801184                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10403.801184                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 10403.801184                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10403.801184                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 10403.801184                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs      8439613                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets           34                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs           658051                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              1                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.825166                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets           34                       # average number of cycles each access was blocked
+system.cpu1.icache.tags.tag_accesses        411165528                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       411165528                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    197154720                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      197154720                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    197154720                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       197154720                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    197154720                       # number of overall hits
+system.cpu1.icache.overall_hits::total      197154720                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      5725810                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      5725810                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      5725810                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       5725810                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      5725810                       # number of overall misses
+system.cpu1.icache.overall_misses::total      5725810                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  59819230732                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  59819230732                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  59819230732                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  59819230732                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  59819230732                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  59819230732                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    202880530                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    202880530                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    202880530                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    202880530                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    202880530                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    202880530                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.028223                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.028223                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.028223                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.028223                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.028223                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.028223                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10447.295794                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 10447.295794                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10447.295794                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 10447.295794                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10447.295794                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 10447.295794                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs      8523796                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets          288                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs           664103                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              3                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.835051                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets           96                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       312465                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total       312465                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst       312465                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total       312465                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst       312465                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total       312465                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5324617                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      5324617                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      5324617                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      5324617                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      5324617                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      5324617                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       321342                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total       321342                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst       321342                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total       321342                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst       321342                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total       321342                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5404468                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      5404468                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      5404468                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      5404468                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      5404468                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      5404468                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total           67                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total           67                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  53161463126                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  53161463126                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  53161463126                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  53161463126                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  53161463126                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  53161463126                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6100998                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      6100998                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      6100998                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      6100998                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.027820                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.027820                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.027820                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.027820                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.027820                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.027820                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9984.091462                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9984.091462                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9984.091462                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  9984.091462                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9984.091462                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  9984.091462                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91059.671642                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 91059.671642                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91059.671642                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 91059.671642                       # average overall mshr uncacheable latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  54260492010                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  54260492010                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  54260492010                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  54260492010                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  54260492010                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  54260492010                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5791998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      5791998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      5791998                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      5791998                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.026639                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.026639                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.026639                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.026639                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.026639                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.026639                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10039.932147                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10039.932147                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10039.932147                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 10039.932147                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10039.932147                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 10039.932147                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86447.731343                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86447.731343                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86447.731343                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86447.731343                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      6690086                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      6848412                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit       136895                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      7840068                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      7844426                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit         3981                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       833652                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements         2101281                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13129.737314                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          17962799                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2117240                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            8.484064                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    10109948263500                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  3719.638298                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    30.194019                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    18.354708                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  4841.731410                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3496.437967                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1023.380912                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.227029                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001843                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.001120                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.295516                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.213406                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.062462                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.801376                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1215                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           80                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14664                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::0            4                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           26                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          222                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          606                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          357                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           40                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           15                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           24                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          138                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1327                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5436                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4651                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3112                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.074158                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004883                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.895020                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       353923766                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      353923766                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       516145                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       163709                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        679854                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks      3252875                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total      3252875                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        76096                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total        76096                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        32991                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total        32991                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       823499                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       823499                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4739467                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      4739467                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2648300                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total      2648300                       # number of ReadSharedReq hits
-system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       186015                       # number of InvalidateReq hits
-system.cpu1.l2cache.InvalidateReq_hits::total       186015                       # number of InvalidateReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       516145                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       163709                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      4739467                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3471799                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        8891120                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       516145                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       163709                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      4739467                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3471799                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       8891120                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        10986                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         7768                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        18754                       # number of ReadReq misses
-system.cpu1.l2cache.Writeback_misses::writebacks           19                       # number of Writeback misses
-system.cpu1.l2cache.Writeback_misses::total           19                       # number of Writeback misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       135316                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       135316                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       152038                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       152038                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            6                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total            6                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       244643                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       244643                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       585139                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total       585139                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       965514                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total       965514                       # number of ReadSharedReq misses
-system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       230258                       # number of InvalidateReq misses
-system.cpu1.l2cache.InvalidateReq_misses::total       230258                       # number of InvalidateReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        10986                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         7768                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       585139                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1210157                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      1814050                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        10986                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         7768                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       585139                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1210157                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      1814050                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    393593000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    283804000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total    677397000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2923492500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total   2923492500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3131932000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3131932000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      3149000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      3149000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  10851172997                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total  10851172997                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  16931159000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total  16931159000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  31232900488                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total  31232900488                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  11958390500                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::total  11958390500                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    393593000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    283804000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  16931159000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data  42084073485                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  59692629485                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    393593000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    283804000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  16931159000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  42084073485                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  59692629485                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       527131                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       171477                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       698608                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks      3252894                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total      3252894                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       211412                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       211412                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       185029                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       185029                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            6                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            6                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1068142                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1068142                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      5324606                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total      5324606                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3613814                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total      3613814                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       416273                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::total       416273                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       527131                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       171477                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      5324606                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data      4681956                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total     10705170                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       527131                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       171477                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      5324606                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data      4681956                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     10705170                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.020841                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.045301                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.026845                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000006                       # miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_miss_rate::total     0.000006                       # miss rate for Writeback accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.640058                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.640058                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.821698                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.821698                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.prefetcher.pfSpanPage       944222                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements         2377748                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13486.772220                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          18876475                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         2393818                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            7.885510                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    10140216096000                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks  5055.984886                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    70.053821                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    84.713714                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3027.541847                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  4406.199695                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   842.278257                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.308593                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004276                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.005171                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.184786                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.268933                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.051409                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.823167                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1281                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           69                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14720                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::0            8                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           30                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          223                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          628                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          392                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           34                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           14                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           19                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          131                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1431                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5385                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4653                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3120                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.078186                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004211                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.898438                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       375099508                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      375099508                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       592978                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       185889                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        778867                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks      3566243                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total      3566243                       # number of Writeback hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        83253                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total        83253                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        35939                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total        35939                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       957303                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total       957303                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4781175                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      4781175                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2910784                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total      2910784                       # number of ReadSharedReq hits
+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       147109                       # number of InvalidateReq hits
+system.cpu1.l2cache.InvalidateReq_hits::total       147109                       # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       592978                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       185889                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      4781175                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data      3868087                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total        9428129                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       592978                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker       185889                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      4781175                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data      3868087                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total       9428129                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12789                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9475                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total        22264                       # number of ReadReq misses
+system.cpu1.l2cache.Writeback_misses::writebacks           18                       # number of Writeback misses
+system.cpu1.l2cache.Writeback_misses::total           18                       # number of Writeback misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       144289                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total       144289                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       172622                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total       172622                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            5                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data       255780                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total       255780                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       623287                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total       623287                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data      1065341                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total      1065341                       # number of ReadSharedReq misses
+system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       258817                       # number of InvalidateReq misses
+system.cpu1.l2cache.InvalidateReq_misses::total       258817                       # number of InvalidateReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12789                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9475                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst       623287                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data      1321121                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total      1966672                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        12789                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9475                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst       623287                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data      1321121                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total      1966672                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    512874500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    430496500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total    943371000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   3103492000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total   3103492000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3553775999                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3553775999                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      3230499                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      3230499                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  13173602496                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total  13173602496                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  17677681000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total  17677681000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  35240864484                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total  35240864484                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  17868215998                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::total  17868215998                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    512874500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    430496500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst  17677681000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data  48414466980                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total  67035518980                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    512874500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    430496500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst  17677681000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data  48414466980                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total  67035518980                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       605767                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       195364                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total       801131                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks      3566261                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total      3566261                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       227542                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       227542                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       208561                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       208561                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1213083                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total      1213083                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      5404462                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total      5404462                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3976125                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total      3976125                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       405926                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::total       405926                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       605767                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       195364                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst      5404462                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data      5189208                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total     11394801                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       605767                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       195364                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      5404462                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data      5189208                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total     11394801                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.021112                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.048499                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.027791                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000005                       # miss rate for Writeback accesses
+system.cpu1.l2cache.Writeback_miss_rate::total     0.000005                       # miss rate for Writeback accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.634120                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.634120                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.827681                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.827681                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.229036                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.229036                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.109893                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.109893                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.267173                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.267173                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.553142                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.553142                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.020841                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.045301                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.109893                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.258473                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.169456                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.020841                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.045301                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.109893                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.258473                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.169456                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 35826.779538                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36535.015448                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36120.134371                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21604.928464                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21604.928464                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20599.665873                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20599.665873                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 524833.333333                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 524833.333333                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44355.133795                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44355.133795                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 28935.276917                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 28935.276917                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 32348.469818                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 32348.469818                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 51934.744938                       # average InvalidateReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 51934.744938                       # average InvalidateReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 35826.779538                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 36535.015448                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28935.276917                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34775.713800                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 32905.724476                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 35826.779538                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 36535.015448                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28935.276917                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34775.713800                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 32905.724476                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.210851                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.210851                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.115328                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.115328                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.267934                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.267934                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.637597                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.637597                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.021112                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.048499                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.115328                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.254590                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.172594                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.021112                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.048499                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.115328                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.254590                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.172594                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 40102.783642                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 45434.986807                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 42372.035573                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21508.860689                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21508.860689                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20587.039885                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20587.039885                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 646099.800000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 646099.800000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51503.645696                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51503.645696                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 28362.024236                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 28362.024236                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 33079.421973                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 33079.421973                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 69038.030724                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 69038.030724                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 40102.783642                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 45434.986807                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28362.024236                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36646.504733                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 34085.764673                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 40102.783642                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 45434.986807                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28362.024236                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36646.504733                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 34085.764673                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs         3889                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs              13                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs   299.153846                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks       947503                       # number of writebacks
-system.cpu1.l2cache.writebacks::total          947503                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            7                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker          197                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total          204                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data        11124                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total        11124                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.writebacks::writebacks      1147174                       # number of writebacks
+system.cpu1.l2cache.writebacks::total         1147174                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            3                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker          177                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::total          180                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data        16460                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total        16460                       # number of ReadExReq MSHR hits
 system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            1                       # number of ReadCleanReq MSHR hits
 system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         2294                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         2294                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data           25                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::total           25                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            7                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker          197                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         3382                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         3382                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            3                       # number of InvalidateReq MSHR hits
+system.cpu1.l2cache.InvalidateReq_mshr_hits::total            3                       # number of InvalidateReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            3                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker          177                       # number of demand (read+write) MSHR hits
 system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data        13418                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total        13623                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            7                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker          197                       # number of overall MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data        19842                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total        20023                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            3                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker          177                       # number of overall MSHR hits
 system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            1                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data        13418                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total        13623                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        10979                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         7571                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        18550                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.Writeback_mshr_misses::writebacks           19                       # number of Writeback MSHR misses
-system.cpu1.l2cache.Writeback_mshr_misses::total           19                       # number of Writeback MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks        99449                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::total        99449                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       669869                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       669869                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       135316                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       135316                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       152038                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       152038                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            6                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            6                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       233519                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total       233519                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       585138                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       585138                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       963220                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       963220                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       230233                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::total       230233                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        10979                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         7571                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       585138                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1196739                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total      1800427                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        10979                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         7571                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       585138                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1196739                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       669869                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total      2470296                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data        19842                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total        20023                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        12786                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         9298                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total        22084                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.Writeback_mshr_misses::writebacks           18                       # number of Writeback MSHR misses
+system.cpu1.l2cache.Writeback_mshr_misses::total           18                       # number of Writeback MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks       111700                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::total       111700                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       804888                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total       804888                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       144289                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total       144289                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       172622                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       172622                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            5                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       239320                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total       239320                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       623286                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       623286                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data      1061959                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total      1061959                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       258814                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::total       258814                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        12786                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         9298                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       623286                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1301279                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total      1946649                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        12786                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         9298                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       623286                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1301279                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       804888                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total      2751537                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        18068                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        18135                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        15995                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        15995                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        16935                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        17002                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        14896                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        14896                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        34063                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        34130                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    327529500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    230470000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    557999500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  32826022044                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  32826022044                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2716564991                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2716564991                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2299520000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2299520000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2723000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2723000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   8060381997                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   8060381997                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  13420310000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  13420310000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  25345446988                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  25345446988                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  10575798500                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  10575798500                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    327529500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    230470000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  13420310000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  33405828985                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  47384138485                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    327529500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    230470000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  13420310000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  33405828985                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  32826022044                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total  80210160529                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5597500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2670265000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2675862500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   2403001000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   2403001000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      5597500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   5073266000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   5078863500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.020828                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.044152                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.026553                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000006                       # mshr miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000006                       # mshr miss rate for Writeback accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        31831                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        31898                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    436116500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    365754500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    801871000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  50468745441                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  50468745441                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2875133996                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2875133996                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2601766497                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2601766497                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2804499                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2804499                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   9250303496                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   9250303496                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  13937951500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  13937951500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  28711604984                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  28711604984                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  16314942498                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  16314942498                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    436116500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    365754500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  13937951500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  37961908480                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total  52701730980                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    436116500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    365754500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  13937951500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  37961908480                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  50468745441                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total 103170476421                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5288500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2468909500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2474198000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   2188801500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   2188801500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      5288500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   4657711000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   4662999500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.021107                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.047593                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.027566                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000005                       # mshr miss rate for Writeback accesses
+system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000005                       # mshr miss rate for Writeback accesses
 system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.640058                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.640058                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.821698                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.821698                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.634120                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.634120                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.827681                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.827681                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.218622                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.218622                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.109893                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.109893                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.266538                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.266538                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.553082                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.553082                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.020828                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.044152                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.109893                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.255607                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.168183                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.020828                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.044152                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.109893                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.255607                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.197282                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.197282                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.115328                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.115328                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.267084                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.267084                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.637589                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.637589                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.021107                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.047593                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.115328                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.250766                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.170837                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.021107                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.047593                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.115328                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.250766                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.230757                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 29832.361782                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30441.157047                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30080.835580                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 49003.644062                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 49003.644062                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20075.711601                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20075.711601                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15124.639893                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15124.639893                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 453833.333333                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 453833.333333                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34517.028580                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34517.028580                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22935.290478                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22935.290478                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26313.248259                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26313.248259                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 45935.198256                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 45935.198256                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 29832.361782                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30441.157047                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22935.290478                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27914.047244                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26318.278100                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 29832.361782                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30441.157047                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22935.290478                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27914.047244                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 49003.644062                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32469.858077                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83544.776119                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 147789.738765                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 147552.384891                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150234.510785                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150234.510785                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83544.776119                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 148937.733024                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 148809.361266                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.241473                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 34108.908181                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 39336.900409                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 36310.043470                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62702.817586                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 62702.817586                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19926.217494                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19926.217494                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15072.044681                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15072.044681                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 560899.800000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 560899.800000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 38652.446498                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 38652.446498                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22362.048081                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22362.048081                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 27036.453370                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27036.453370                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 63037.326026                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 63037.326026                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 34108.908181                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 39336.900409                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22362.048081                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29172.766547                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27073.052707                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 34108.908181                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 39336.900409                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22362.048081                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29172.766547                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62702.817586                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37495.580260                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78932.835821                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145787.392973                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 145523.938360                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146938.876208                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 146938.876208                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78932.835821                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 146326.254280                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 146184.698100                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq        892292                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp      9878632                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            2                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        38264                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        15995                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback      7255897                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict      9976246                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq       974296                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp            4                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       447021                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       338151                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       459645                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           83                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          148                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1866908                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1075363                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5324617                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq      6289738                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq       523001                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp       416273                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     15972735                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16223776                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       373937                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1157245                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         33727693                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    340775856                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    514151471                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1371816                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4217048                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total         860516191                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                   12204948                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     33927884                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       1.375605                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.484279                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq        997626                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp     10426628                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        38204                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        14896                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback      7712009                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict     10305258                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq      1022601                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp           10                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       482744                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       380034                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       500528                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           70                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          136                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1988029                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1220428                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5404468                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      6543941                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       512654                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       405926                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     16212466                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     17789160                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       422162                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1316947                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         35740735                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    345886640                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    566771243                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1562912                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4846136                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total         919066931                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                   12378423                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     35388761                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       1.367817                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.482211                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1          21184404     62.44%     62.44% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2          12743480     37.56%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1          22372180     63.22%     63.22% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2          13016581     36.78%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      33927884                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   14269396468                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      35388761                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   15228808958                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    176820981                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    179948989                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   7990923619                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   8110869278                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   7460231410                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   8234240098                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    202704009                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    227095399                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    630714293                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    711723893                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40336                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40336                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136670                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136670                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47832                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                40342                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40342                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136642                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136642                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47708                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2991,13 +2995,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122766                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231166                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231166                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122642                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231246                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231246                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354012                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47852                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353968                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47728                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -3012,13 +3016,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155873                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338680                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7338680                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155749                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339000                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7339000                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7496639                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36328000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7496835                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36238000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -3046,71 +3050,71 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           569486466                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           569545477                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92827000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92731000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147862000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147942000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115572                       # number of replacements
-system.iocache.tags.tagsinuse               11.309139                       # Cycle average of tags in use
+system.iocache.tags.replacements               115612                       # number of replacements
+system.iocache.tags.tagsinuse               11.307418                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115588                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115628                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9081185715000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.844632                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     7.464507                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.240289                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.466532                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.706821                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         9081354759000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.848836                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     7.458583                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.240552                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.466161                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.706714                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1040604                       # Number of tag accesses
-system.iocache.tags.data_accesses             1040604                       # Number of data accesses
+system.iocache.tags.tag_accesses              1040964                       # Number of tag accesses
+system.iocache.tags.data_accesses             1040964                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8855                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8892                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8895                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8932                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8855                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8895                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8895                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8935                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8855                       # number of overall misses
-system.iocache.overall_misses::total             8895                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8895                       # number of overall misses
+system.iocache.overall_misses::total             8935                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5195000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1639991052                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1645186052                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::realview.ethernet       373000                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total       373000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  12624663414                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  12624663414                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5568000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1639991052                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1645559052                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5568000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1639991052                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1645559052                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1662593136                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1667788136                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12635360341                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12635360341                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5564000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1662593136                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1668157136                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5564000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1662593136                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1668157136                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8855                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8892                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8895                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8932                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8855                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8895                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8895                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8935                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8855                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8895                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8895                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8935                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -3125,54 +3129,54 @@ system.iocache.overall_miss_rate::realview.ethernet            1
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 185205.087747                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 185018.674314                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::realview.ethernet 124333.333333                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 124333.333333                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118288.203789                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118288.203789                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       139200                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 185205.087747                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 184998.207083                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       139200                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 185205.087747                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 184998.207083                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         32135                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 186913.224958                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 186720.570533                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118388.429850                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118388.429850                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 186913.224958                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 186699.175825                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 186913.224958                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 186699.175825                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         32654                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3455                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3383                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.301013                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.652380                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106702                       # number of writebacks
 system.iocache.writebacks::total               106702                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8855                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8892                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8895                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8932                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8855                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8895                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8895                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8935                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8855                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8895                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide         8895                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8935                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3345000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1197241052                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1200586052                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       223000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total       223000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7288263414                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   7288263414                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3568000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1197241052                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1200809052                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3568000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1197241052                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1200809052                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1217843136                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1221188136                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7298960341                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7298960341                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3564000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1217843136                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1221407136                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3564000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1217843136                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1221407136                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -3187,616 +3191,614 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet            1
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135205.087747                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 135018.674314                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 74333.333333                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 74333.333333                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68288.203789                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68288.203789                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89200                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 135205.087747                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 134998.207083                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89200                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 135205.087747                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 134998.207083                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136913.224958                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 136720.570533                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68388.429850                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68388.429850                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 136913.224958                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 136699.175825                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 136913.224958                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 136699.175825                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1677022                       # number of replacements
-system.l2c.tags.tagsinuse                63960.007157                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    5998379                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1737036                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     3.453227                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1760747                       # number of replacements
+system.l2c.tags.tagsinuse                63871.601453                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    6095006                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1821172                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     3.346749                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   15741.839802                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   357.273948                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   484.122298                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4874.372847                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    16502.292162                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 20727.343192                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    11.818696                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker     7.376448                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2388.813179                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1821.049873                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1043.704711                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.240201                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.005452                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.007387                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.074377                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.251805                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.316274                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000180                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.000113                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.036450                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.027787                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.015926                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.975952                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        10260                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          258                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        49496                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::0            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          879                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3          504                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4         8874                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          254                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          326                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2439                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         4866                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        41821                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.156555                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.003937                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.755249                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 75068652                       # Number of tag accesses
-system.l2c.tags.data_accesses                75068652                       # Number of data accesses
-system.l2c.Writeback_hits::writebacks         2604285                       # number of Writeback hits
-system.l2c.Writeback_hits::total              2604285                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data           28546                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data           29320                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               57866                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          6394                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          5412                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             11806                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           161030                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           157813                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               318843                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6923                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4910                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst       644950                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       656166                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       305817                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         5910                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4051                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst       543185                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       555453                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       279182                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          3006547                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          6923                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          4910                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              644950                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              817196                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       305817                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          5910                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          4051                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              543185                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              713266                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher       279182                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 3325390                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         6923                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         4910                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             644950                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             817196                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       305817                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         5910                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         4051                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             543185                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             713266                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       279182                       # number of overall hits
-system.l2c.overall_hits::total                3325390                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data         46522                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         43915                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             90437                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data        10622                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         7888                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           18510                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         567822                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data         117808                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             685630                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         3723                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker         3679                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        69821                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       197538                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       366356                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1749                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1250                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst        41953                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data       109150                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       201783                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         997002                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         3723                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         3679                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             69821                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            765360                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       366356                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         1749                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         1250                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             41953                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            226958                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       201783                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1682632                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         3723                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         3679                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            69821                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           765360                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       366356                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         1749                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         1250                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            41953                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           226958                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       201783                       # number of overall misses
-system.l2c.overall_misses::total              1682632                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data    264342500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    275145500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    539488000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data     60602000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data     45349000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total    105951000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  73693634000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data  12026393499                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  85720027499                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    347505000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    338090000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   6068374002                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  19146364498                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  50780119067                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    166591000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    119960500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst   3610747500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data  10634037494                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  27957366963                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total 119169156024                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    347505000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    338090000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   6068374002                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  92839998498                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  50780119067                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    166591000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    119960500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   3610747500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  22660430993                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  27957366963                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    204889183523                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    347505000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    338090000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   6068374002                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  92839998498                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  50780119067                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    166591000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    119960500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   3610747500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  22660430993                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  27957366963                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   204889183523                       # number of overall miss cycles
-system.l2c.Writeback_accesses::writebacks      2604285                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          2604285                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        75068                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        73235                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          148303                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        17016                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        13300                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         30316                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       728852                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       275621                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total          1004473                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        10646                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         8589                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst       714771                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       853704                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       672173                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         7659                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         5301                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst       585138                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       664603                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       480965                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      4003549                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        10646                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         8589                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          714771                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1582556                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       672173                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         7659                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         5301                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          585138                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          940224                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       480965                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             5008022                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        10646                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         8589                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         714771                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1582556                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       672173                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         7659                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         5301                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         585138                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         940224                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       480965                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            5008022                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.619731                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.599645                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.609812                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.624236                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.593083                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.610569                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.779064                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.427428                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.682577                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.349709                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.428339                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.097683                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.231389                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.545032                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.228359                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.235805                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.071698                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.164233                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.419538                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.249030                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.349709                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.428339                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.097683                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.483623                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.545032                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.228359                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.235805                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.071698                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.241387                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.419538                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.335987                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.349709                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.428339                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.097683                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.483623                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.545032                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.228359                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.235805                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.071698                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.241387                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.419538                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.335987                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  5682.096642                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6265.410452                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  5965.346042                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5705.328563                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5749.112576                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  5723.987034                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 129782.984809                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102084.692882                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 125023.740938                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 93340.048348                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 91897.254689                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 86913.306913                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 96924.968857                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 138608.673168                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 95249.285306                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 95968.400000                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86066.491073                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 97425.904663                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 138551.646883                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 119527.499467                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 93340.048348                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 91897.254689                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 86913.306913                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 121302.391682                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 138608.673168                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 95249.285306                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 95968.400000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 86066.491073                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 99844.160563                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 138551.646883                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 121767.078911                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 93340.048348                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 91897.254689                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 86913.306913                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 121302.391682                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 138608.673168                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 95249.285306                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 95968.400000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 86066.491073                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 99844.160563                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 138551.646883                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 121767.078911                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs              9470                       # number of cycles access was blocked
+system.l2c.tags.occ_blocks::writebacks   18326.572985                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   182.034797                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   268.280441                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4619.393037                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     9002.087865                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11374.868707                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   179.474155                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   242.215899                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     2745.232497                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     8268.941513                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  8662.499555                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.279641                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002778                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.004094                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.070486                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.137361                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.173567                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002739                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.003696                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.041889                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.126174                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.132179                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.974603                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        11384                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          237                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        48804                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::0            8                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2         1357                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3          826                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4         9193                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          233                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          346                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2623                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5288                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        40501                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.173706                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003616                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.744690                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 76795315                       # Number of tag accesses
+system.l2c.tags.data_accesses                76795315                       # Number of data accesses
+system.l2c.Writeback_hits::writebacks         2680735                       # number of Writeback hits
+system.l2c.Writeback_hits::total              2680735                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data           32943                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data           31048                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               63991                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data          6336                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data          5767                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total             12103                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           174506                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data           154775                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               329281                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6806                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4586                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst       614111                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       638498                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       286433                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6534                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4346                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst       583459                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       618336                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       287570                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          3050679                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          6806                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          4586                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              614111                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              813004                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher       286433                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          6534                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          4346                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              583459                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              773111                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher       287570                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 3379960                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         6806                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         4586                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             614111                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             813004                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher       286433                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         6534                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         4346                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             583459                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             773111                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher       287570                       # number of overall hits
+system.l2c.overall_hits::total                3379960                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data         48112                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data         44467                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             92579                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data        10023                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data         8706                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total           18729                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         523780                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data         170521                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             694301                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         2882                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.itb.walker         2624                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.inst        74362                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       179746                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       302363                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         2755                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.itb.walker         2528                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.inst        39827                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data       128012                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       323843                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total        1058942                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.dtb.walker         2882                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker         2624                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             74362                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            703526                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.l2cache.prefetcher       302363                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker         2755                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker         2528                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst             39827                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data            298533                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.l2cache.prefetcher       323843                       # number of demand (read+write) misses
+system.l2c.demand_misses::total               1753243                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker         2882                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker         2624                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            74362                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           703526                       # number of overall misses
+system.l2c.overall_misses::cpu0.l2cache.prefetcher       302363                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker         2755                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker         2528                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst            39827                       # number of overall misses
+system.l2c.overall_misses::cpu1.data           298533                       # number of overall misses
+system.l2c.overall_misses::cpu1.l2cache.prefetcher       323843                       # number of overall misses
+system.l2c.overall_misses::total              1753243                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data    280230500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data    263754000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    543984500                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data     55711000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data     50228500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total    105939500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data  68581440500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data  18910817992                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  87492258492                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    268423000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    251208500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.inst   6463422502                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data  17884384500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  42388472929                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    254889500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    239052000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst   3438315000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data  12527996000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  45486797416                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total 129202961347                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker    268423000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker    251208500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   6463422502                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  86465825000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  42388472929                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker    254889500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker    239052000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst   3438315000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data  31438813992                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  45486797416                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total    216695219839                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker    268423000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker    251208500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   6463422502                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  86465825000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  42388472929                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker    254889500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker    239052000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst   3438315000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data  31438813992                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  45486797416                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total   216695219839                       # number of overall miss cycles
+system.l2c.Writeback_accesses::writebacks      2680735                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          2680735                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        81055                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data        75515                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          156570                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data        16359                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data        14473                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total         30832                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       698286                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       325296                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total          1023582                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         9688                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         7210                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst       688473                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       818244                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       588796                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         9289                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         6874                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst       623286                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       746348                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       611413                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      4109621                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         9688                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         7210                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          688473                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1516530                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       588796                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         9289                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         6874                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          623286                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data         1071644                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher       611413                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             5133203                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         9688                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         7210                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         688473                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1516530                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       588796                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         9289                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         6874                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         623286                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data        1071644                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher       611413                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            5133203                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.593572                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.588850                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.591295                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.612690                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.601534                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.607453                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.750094                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.524203                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.678305                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.297481                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.363939                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.108010                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.219673                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.513528                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.296587                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.367763                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.063898                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.171518                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.529663                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.257674                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.297481                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.363939                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.108010                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.463905                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.513528                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.296587                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.367763                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.063898                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.278575                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.529663                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.341550                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.297481                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.363939                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.108010                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.463905                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.513528                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.296587                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.367763                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.063898                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.278575                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.529663                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.341550                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  5824.544812                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5931.454787                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  5875.895181                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5558.315873                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5769.411900                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  5656.441882                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 130935.584597                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 110900.229250                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 126014.881862                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 93137.751561                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 95734.946646                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 86918.352142                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 99498.094533                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 140190.674550                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 92518.874773                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 94561.708861                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86331.257690                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 97865.793832                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 140459.412172                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 122011.367334                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 93137.751561                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 95734.946646                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 86918.352142                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 122903.524532                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 140190.674550                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92518.874773                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 94561.708861                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 86331.257690                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 105311.017516                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 140459.412172                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 123596.797386                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 93137.751561                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 95734.946646                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 86918.352142                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 122903.524532                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 140190.674550                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92518.874773                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 94561.708861                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 86331.257690                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 105311.017516                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 140459.412172                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 123596.797386                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs             12094                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                      105                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                      115                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     90.190476                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs    105.165217                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1291985                       # number of writebacks
-system.l2c.writebacks::total                  1291985                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          127                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data           25                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          183                       # number of ReadSharedReq MSHR hits
+system.l2c.writebacks::writebacks             1358225                       # number of writebacks
+system.l2c.writebacks::total                  1358225                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          229                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu0.data           34                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          211                       # number of ReadSharedReq MSHR hits
 system.l2c.ReadSharedReq_mshr_hits::cpu1.data           37                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total          372                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst            127                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             25                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst            183                       # number of demand (read+write) MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total          511                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst            229                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data             34                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst            211                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu1.data             37                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                372                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst           127                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            25                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst           183                       # number of overall MSHR hits
+system.l2c.demand_mshr_hits::total                511                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst           229                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data            34                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst           211                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.data            37                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               372                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks        57543                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total        57543                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        46522                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        43915                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        90437                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        10622                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         7888                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total        18510                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       567822                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data       117808                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        685630                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         3723                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         3679                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        69694                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       197513                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       366356                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         1749                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1250                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        41770                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data       109113                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       201783                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       996630                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         3723                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         3679                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        69694                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       765335                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       366356                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         1749                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker         1250                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        41770                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data       226921                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       201783                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total          1682260                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         3723                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         3679                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        69694                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       765335                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       366356                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker         1749                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker         1250                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst        41770                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data       226921                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       201783                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total         1682260                       # number of overall MSHR misses
+system.l2c.overall_mshr_hits::total               511                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks        57055                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total        57055                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data        48112                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data        44467                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        92579                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        10023                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         8706                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total        18729                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data       523780                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data       170521                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        694301                       # number of ReadExReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         2882                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         2624                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        74133                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data       179712                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       302363                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         2755                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         2528                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        39616                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data       127975                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       323843                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total      1058431                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker         2882                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker         2624                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        74133                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       703492                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       302363                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker         2755                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker         2528                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst        39616                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data       298496                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       323843                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total          1752732                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker         2882                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker         2624                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        74133                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       703492                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       302363                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker         2755                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker         2528                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst        39616                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data       298496                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       323843                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total         1752732                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        21294                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        20289                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data        21352                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data        18066                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        59716                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        22269                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data        15995                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        38264                       # number of WriteReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data        16933                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        59646                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        23308                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data        14896                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        38204                       # number of WriteReq MSHR uncacheable
 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        21294                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        42558                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        44660                       # number of overall MSHR uncacheable misses
 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        34061                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        97980                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    967860505                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    912939509                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total   1880800014                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    220678503                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    163861499                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total    384540002                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  68015414000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  10848313499                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  78863727499                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    310275000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    301300000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   5361144002                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  17169186498                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  47116559067                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    149101000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    107460500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   3179316500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   9539742994                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  25939536963                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total 109173622524                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    310275000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    301300000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   5361144002                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  85184600498                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  47116559067                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    149101000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    107460500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst   3179316500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data  20388056493                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  25939536963                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 188037350023                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    310275000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    301300000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   5361144002                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  85184600498                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  47116559067                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    149101000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    107460500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst   3179316500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data  20388056493                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  25939536963                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 188037350023                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        31829                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        97850                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   1000759503                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    924536001                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total   1925295504                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    208161502                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    180991502                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total    389153004                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  63343640500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  17205607992                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  80549248492                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    239603000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    224968500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   5703318002                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  16083965000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  39364842929                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    227339500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    213772000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   3027081000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  11244495000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  42248367416                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total 118577752347                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    239603000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    224968500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   5703318002                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  79427605500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  39364842929                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    227339500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    213772000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst   3027081000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data  28450102992                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  42248367416                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 199127000839                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    239603000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    224968500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   5703318002                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  79427605500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  39364842929                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    227339500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    213772000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst   3027081000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data  28450102992                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  42248367416                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 199127000839                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1320748000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3168263000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      4391000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2345032500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   6838434500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   3288254533                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2131065000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5419319533                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3340995000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      4081500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2164071000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   6829895500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   3477095533                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1935550000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   5412645533                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1320748000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   6456517533                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      4391000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   4476097500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  12257754033                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   6818090533                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      4081500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   4099621000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  12242541033                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.619731                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.599645                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.609812                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.624236                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.593083                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.610569                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.779064                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.427428                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.682577                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.349709                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.428339                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.097505                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.231360                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.545032                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.228359                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.235805                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.071385                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.164178                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.419538                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.248937                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.349709                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.428339                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.097505                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.483607                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.545032                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.228359                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.235805                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.071385                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.241348                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.419538                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.335913                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.349709                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.428339                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.097505                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.483607                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.545032                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.228359                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.235805                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.071385                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.241348                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.419538                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.335913                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20804.361485                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20788.785358                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20796.797926                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20775.607513                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20773.516608                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20774.716478                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 119782.984809                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92084.692882                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 115023.740938                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 83340.048348                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 81897.254689                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 76924.039401                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 86926.868095                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 128608.673168                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 85249.285306                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 85968.400000                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76114.831219                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 87429.939549                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128551.646883                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 109542.781698                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83340.048348                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 81897.254689                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76924.039401                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 111303.678125                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 128608.673168                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 85249.285306                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 85968.400000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76114.831219                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 89846.495005                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128551.646883                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 111776.627883                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83340.048348                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 81897.254689                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76924.039401                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 111303.678125                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 128608.673168                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 85249.285306                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 85968.400000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76114.831219                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 89846.495005                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128551.646883                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 111776.627883                       # average overall mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.593572                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.588850                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.591295                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.612690                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.601534                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.607453                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.750094                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.524203                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.678305                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.297481                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.363939                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.107677                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.219631                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.513528                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.296587                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.367763                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.063560                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.171468                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.529663                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.257550                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.297481                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.363939                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.107677                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.463883                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.513528                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.296587                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.367763                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.063560                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.278540                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.529663                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.341450                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.297481                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.363939                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.107677                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.463883                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.513528                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.296587                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.367763                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.063560                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.278540                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.529663                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.341450                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20800.621529                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20791.508332                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20796.244332                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20768.382919                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20789.283483                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20778.098350                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 120935.584597                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 100900.229250                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 116014.881862                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 83137.751561                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 85734.946646                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 76933.592354                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 89498.558805                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130190.674550                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82518.874773                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 84561.708861                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76410.566438                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 87864.778277                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130459.412172                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 112031.632054                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83137.751561                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 85734.946646                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76933.592354                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 112904.774326                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130190.674550                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82518.874773                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 84561.708861                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76410.566438                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 95311.504985                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130459.412172                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 113609.496968                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83137.751561                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 85734.946646                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76933.592354                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 112904.774326                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130190.674550                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82518.874773                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 84561.708861                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76410.566438                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 95311.504985                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130459.412172                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 113609.496968                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 156156.685889                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 65537.313433                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 129803.636666                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 114515.950499                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147660.628362                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133233.197874                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141629.718090                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 156472.227426                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60917.910448                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 127801.984291                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 114507.184053                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149180.347220                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 129937.567132                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141677.456104                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151711.018680                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 65537.313433                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 131414.154018                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 125104.654348                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152666.603963                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60917.910448                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 128801.438939                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 125115.391242                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               59716                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1065238                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38264                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38264                       # Transaction distribution
-system.membus.trans_dist::Writeback           1398687                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           273545                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           431435                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         293289                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          115559                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            699678                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           679021                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       1005522                       # Transaction distribution
+system.membus.trans_dist::ReadReq               59646                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1127009                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38204                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38204                       # Transaction distribution
+system.membus.trans_dist::Writeback           1464927                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           280718                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           444619                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         331926                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          118163                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            4                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            708914                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           687449                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1067363                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106728                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106728                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122766                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122642                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           78                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25252                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5818316                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      5966412                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342390                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       342390                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6308802                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155873                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25116                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6087631                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      6235467                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342027                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       342027                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6577494                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155749                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          572                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        50504                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    190243904                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    190450853                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7261952                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7261952                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               197712805                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           632700                       # Total snoops (count)
-system.membus.snoop_fanout::samples           4309210                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        50232                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    198978048                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    199184601                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7249472                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7249472                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               206434073                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           682959                       # Total snoops (count)
+system.membus.snoop_fanout::samples           4505681                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 4309210    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 4505681    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             4309210                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            98315494                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             4505681                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            98301494                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               54500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            21255984                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            21116985                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          9692600374                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy         10136025529                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         9139212712                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         9507659574                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          229129958                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          229108938                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -3840,50 +3842,50 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq              59718                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           4906213                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38264                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38264                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          4003012                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         1629651                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          482692                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        305095                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         787787                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          148                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          148                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          1150777                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         1150777                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      4853770                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq              59648                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           5069827                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38204                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38204                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          4145743                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1638680                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          501758                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        344029                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         845787                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          136                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          136                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          1170821                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         1170821                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      5017419                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq       106728                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9404841                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6602998                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              16007839                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    297836822                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    190023375                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              487860197                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         3506825                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         13882904                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.137454                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.344326                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9001938                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7449274                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              16451212                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    278573838                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    222195147                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              500768985                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         3698425                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         14333755                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.138980                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.345926                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1               11974647     86.25%     86.25% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                1908257     13.75%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1               12341651     86.10%     86.10% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                1992104     13.90%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           13882904                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         8939333587                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           14333755                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         9346036195                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2427000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2541000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        5448458649                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        5271518855                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4022349362                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4504542320                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    4812                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                    4738                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   13871                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                   14252                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
index 5f37e786a8418ec7530fbe5dda933e2b155a566c..aba26f57db57e6d3d0e8a32b8869759bc708f218 100644 (file)
@@ -4,11 +4,11 @@ sim_seconds                                 47.216814                       # Nu
 sim_ticks                                47216814145000                       # Number of ticks simulated
 final_tick                               47216814145000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1322702                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1556041                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            64025133870                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 730036                       # Number of bytes of host memory used
-host_seconds                                   737.47                       # Real time elapsed on the host
+host_inst_rate                                1175010                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1382295                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            56876129335                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 728240                       # Number of bytes of host memory used
+host_seconds                                   830.17                       # Real time elapsed on the host
 sim_insts                                   975457230                       # Number of instructions simulated
 sim_ops                                    1147538415                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -1472,7 +1472,7 @@ system.membus.trans_dist::ReadResp             560921                       # Tr
 system.membus.trans_dist::WriteReq              38802                       # Transaction distribution
 system.membus.trans_dist::WriteResp             38802                       # Transaction distribution
 system.membus.trans_dist::Writeback           1578732                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           418758                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           418759                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq           328366                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq         314759                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp          149960                       # Transaction distribution
@@ -1484,11 +1484,11 @@ system.membus.trans_dist::InvalidateResp       106728                       # Tr
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122570                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        27558                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6659521                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      6809741                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6659522                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      6809742                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       346873                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       346873                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                7156614                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                7156615                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155677                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        55116                       # Cumulative packet size per connected master and slave (bytes)
@@ -1498,17 +1498,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7398848
 system.membus.pkt_size_system.iocache.mem_side::total      7398848                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total               217946321                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           4958638                       # Request fanout histogram
+system.membus.snoop_fanout::samples           4958639                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 4958638    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 4958639    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             4958638                       # Request fanout histogram
+system.membus.snoop_fanout::total             4958639                       # Request fanout histogram
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
index 0006790d0b3a98d394c8982a02a6f969aec54b4a..ba04235c3c4359a7de36b5845b96ce82fc6ad19a 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.496387                       # Number of seconds simulated
-sim_ticks                                47496386980500                       # Number of ticks simulated
-final_tick                               47496386980500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.456680                       # Number of seconds simulated
+sim_ticks                                47456679626500                       # Number of ticks simulated
+final_tick                               47456679626500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 708538                       # Simulator instruction rate (inst/s)
-host_op_rate                                   833484                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            38555693115                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 757988                       # Number of bytes of host memory used
-host_seconds                                  1231.89                       # Real time elapsed on the host
-sim_insts                                   872840522                       # Number of instructions simulated
-sim_ops                                    1026761155                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 659863                       # Simulator instruction rate (inst/s)
+host_op_rate                                   776251                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            36196220555                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 759244                       # Number of bytes of host memory used
+host_seconds                                  1311.10                       # Real time elapsed on the host
+sim_insts                                   865142471                       # Number of instructions simulated
+sim_ops                                    1017738631                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker        77248                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker        78464                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          2962612                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         38823816                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     12701504                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       109824                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       113728                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2837560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         15245328                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     12552128                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        438080                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             85940292                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      2962612                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2837560                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5800172                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     72817088                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker        51904                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        48448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          2877620                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         38342664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     11776896                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       153536                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       163840                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2826616                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         16120336                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     11259712                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        435648                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             84057220                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      2877620                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2826616                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5704236                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     70891776                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          72837672                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1207                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1226                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             86698                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            606635                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       198461                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         1716                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         1777                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             44425                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            238221                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       196127                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6845                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1383338                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1137767                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          70912360                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker          811                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker          757                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             85370                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            599117                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       184014                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2399                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2560                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             44254                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            251893                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       175933                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6807                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1353915                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1107684                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1140341                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          1626                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          1652                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               62376                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              817406                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       267420                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          2312                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          2394                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               59743                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              320979                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       264275                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9223                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1809407                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          62376                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          59743                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             122118                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1533108                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data                433                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1110258                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          1094                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          1021                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               60637                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              807951                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       248161                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          3235                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          3452                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               59562                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              339685                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       237263                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9180                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1771241                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          60637                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          59562                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             120199                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1493821                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1533541                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1533108                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         1626                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         1652                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              62376                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             817839                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       267420                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         2312                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         2394                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              59743                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             320979                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       264275                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            9223                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3342948                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1383338                       # Number of read requests accepted
-system.physmem.writeReqs                      1140341                       # Number of write requests accepted
-system.physmem.readBursts                     1383338                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1140341                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 88503808                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     29824                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  72836864                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  85940292                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               72837672                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      466                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total                1494255                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1493821                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         1094                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         1021                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              60637                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             808384                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       248161                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         3235                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         3452                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              59562                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             339685                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       237263                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9180                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3265496                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1353915                       # Number of read requests accepted
+system.physmem.writeReqs                      1110258                       # Number of write requests accepted
+system.physmem.readBursts                     1353915                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1110258                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 86619200                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     31360                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  70911104                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  84057220                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               70912360                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      490                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         218501                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               80378                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               85683                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               84533                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               91641                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               87506                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               92565                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               85373                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               87361                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               80689                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              125890                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              79879                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              87722                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              73371                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              83748                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              77275                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              79258                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               66779                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               71701                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               72134                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               76164                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               73824                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               77776                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               71735                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               72120                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               69346                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               71851                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              68226                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              73306                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64374                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              72179                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              67114                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              69447                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         220771                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               83838                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               89540                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               77326                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               81695                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               84097                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               94926                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               83322                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               86179                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               76741                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              125350                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              75788                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              81366                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              76482                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              81797                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              77630                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              77348                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               68540                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               72321                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               65671                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               69464                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               70371                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               77894                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               70312                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               72647                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               65746                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               72323                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65450                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              68291                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              65769                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              69040                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              66651                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              67496                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          52                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47496383920000                       # Total gap between requests
+system.physmem.numWrRetry                          71                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47456676566000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                   43195                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1340113                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1310690                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1137767                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1131623                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     75605                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     35452                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     30271                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     26331                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     23289                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     20581                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     17115                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     14732                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      3112                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1389                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      848                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      676                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      510                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      378                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      327                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      250                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      202                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      102                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       68                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1107684                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1123748                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     74620                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     32556                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     27437                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                     23297                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                     20472                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                     17890                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     14951                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     12831                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      2528                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      983                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      550                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      416                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      288                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      209                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      175                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      158                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      139                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       98                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       62                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       12                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
@@ -188,167 +188,165 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    16550                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    19449                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    48905                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    57076                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    61582                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    64173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    65524                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    69411                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    70341                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    73639                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    73241                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    74463                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    72846                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    73821                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    77361                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    71631                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    68870                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    66897                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1594                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1048                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      987                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    16504                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    19352                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    48877                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    56560                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    60723                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    62814                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    63983                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    67411                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    68337                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    71503                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    71245                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    72329                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    70408                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    71228                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    74472                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    69249                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    66307                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    64601                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1352                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1011                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      857                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                      658                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      577                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      491                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      435                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      422                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      365                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      365                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      326                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      323                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      322                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      321                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      287                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      307                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      301                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      289                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      293                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      256                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      244                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      254                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      243                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      178                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      156                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      158                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       866706                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      186.153496                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     114.409994                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     244.608227                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         521785     60.20%     60.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       170596     19.68%     79.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        55940      6.45%     86.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        28866      3.33%     89.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        19331      2.23%     91.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        11894      1.37%     93.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         9595      1.11%     94.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         9879      1.14%     95.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        38820      4.48%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         866706                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         64746                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        21.358308                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      318.389928                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095          64744    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::37                      616                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      534                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      469                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      470                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      437                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      403                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      372                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      344                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      308                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      386                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      390                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      312                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      315                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      287                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      345                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      264                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      285                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      247                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      156                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      115                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                      100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      238                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       850568                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      185.205557                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     113.971853                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     243.835447                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         513606     60.38%     60.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       167161     19.65%     80.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        54824      6.45%     86.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        28166      3.31%     89.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        18449      2.17%     91.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        11525      1.35%     93.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         9338      1.10%     94.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         9545      1.12%     95.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        37954      4.46%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         850568                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         62842                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        21.536775                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      323.180031                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095          62840    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::20480-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::77824-81919            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           64746                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         64746                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.577549                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.073829                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        6.807966                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           61438     94.89%     94.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             935      1.44%     96.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             457      0.71%     97.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             214      0.33%     97.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             283      0.44%     97.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             509      0.79%     98.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             100      0.15%     98.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              37      0.06%     98.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              36      0.06%     98.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              29      0.04%     98.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              34      0.05%     98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              27      0.04%     99.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             442      0.68%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              39      0.06%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              47      0.07%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              53      0.08%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              11      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               2      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               4      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             3      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           62842                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         62842                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.631298                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.120021                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        6.777595                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           59398     94.52%     94.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            1045      1.66%     96.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             473      0.75%     96.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             210      0.33%     97.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             336      0.53%     97.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             469      0.75%     98.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             106      0.17%     98.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              34      0.05%     98.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              31      0.05%     98.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              28      0.04%     98.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              37      0.06%     98.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              34      0.05%     98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             449      0.71%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              44      0.07%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              47      0.07%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              32      0.05%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               9      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               2      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               4      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             5      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             2      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.00%     99.93% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::112-115             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            16      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             2      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             6      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             5      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           64746                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    34994473123                       # Total ticks spent queuing
-system.physmem.totMemAccLat               60923323123                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   6914360000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       25305.65                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::128-131            26      0.04%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             4      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             3      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::236-239             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           62842                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    31787428314                       # Total ticks spent queuing
+system.physmem.totMemAccLat               57164147064                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   6767125000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       23486.66                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44055.65                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.86                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.53                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.81                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.53                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  42236.66                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.83                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.49                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.77                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.49                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.44                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.88                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1113162                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    541079                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.50                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  47.54                       # Row buffer hit rate for writes
-system.physmem.avgGap                     18820295.26                       # Average gap between requests
-system.physmem.pageHitRate                      65.62                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 3392073720                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1850833875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                5421273000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3772869840                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3102232782480                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1205451752805                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27440415505500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31762537091220                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.735925                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45648791331206                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1586008580000                       # Time in different power states
+system.physmem.avgRdQLen                         1.31                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.28                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1086313                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    524528                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.26                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  47.34                       # Row buffer hit rate for writes
+system.physmem.avgGap                     19258662.67                       # Average gap between requests
+system.physmem.pageHitRate                      65.44                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 3335290560                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1819851000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                5311160400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3675585600                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3099639126480                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1204726391325                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27417225862500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31735733267865                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.730691                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45610216470982                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1584682580000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    261586624794                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    261780130518                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 3160223640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1724328375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                5365089600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3601862640                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3102232782480                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1192319355510                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27451935144000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31760338786245                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.689642                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45667995849266                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1586008580000                       # Time in different power states
+system.physmem_1.actEnergy                 3095003520                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1688742000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                5245507800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3504163680                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3099639126480                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1191482148060                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27428843611500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31733498303040                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.683596                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45629577337540                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1584682580000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    242377776984                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    242414504460                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -412,67 +410,71 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   104839                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               104839                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        10495                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        79742                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore            9                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       104830                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean     0.171707                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev    55.594229                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-2047       104829    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks                   105954                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               105954                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        10115                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        80576                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore           26                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       105928                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean     0.169927                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev    55.305347                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-2047       105927    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::16384-18431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       104830                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        90246                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 19548.112936                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 18016.919113                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 12415.253011                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535        89555     99.23%     99.23% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071          591      0.65%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607           29      0.03%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143           30      0.03%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679           26      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        90246                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples  -2134286464                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     1.271898                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0      580308492    -27.19%    -27.19% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1    -2714594956    127.19%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  -2134286464                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        79742     88.37%     88.37% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        10495     11.63%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total        90237                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       104839                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkWaitTime::total       105928                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        90717                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 19602.257570                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 18339.618281                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 10083.229942                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767        87482     96.43%     96.43% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535         2786      3.07%     99.51% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-98303          233      0.26%     99.76% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-131071          145      0.16%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839           15      0.02%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::163840-196607            6      0.01%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-229375           19      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::229376-262143            7      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-294911           11      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::294912-327679            9      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-360447            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        90717                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples   9139568088                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     1.172115                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0    -1573058396    -17.21%    -17.21% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1    10712626484    117.21%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total   9139568088                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        80577     88.85%     88.85% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        10115     11.15%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        90692                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       105954                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       104839                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        90237                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       105954                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        90692                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        90237                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       195076                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        90692                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       196646                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    85272873                       # DTB read hits
-system.cpu0.dtb.read_misses                     78883                       # DTB read misses
-system.cpu0.dtb.write_hits                   76479493                       # DTB write hits
-system.cpu0.dtb.write_misses                    25956                       # DTB write misses
+system.cpu0.dtb.read_hits                    80457124                       # DTB read hits
+system.cpu0.dtb.read_misses                     79863                       # DTB read misses
+system.cpu0.dtb.write_hits                   72637408                       # DTB write hits
+system.cpu0.dtb.write_misses                    26091                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              40618                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1028                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   39585                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid              39897                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1024                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   34410                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  4176                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  3731                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    10186                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                85351756                       # DTB read accesses
-system.cpu0.dtb.write_accesses               76505449                       # DTB write accesses
+system.cpu0.dtb.perms_faults                     8741                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                80536987                       # DTB read accesses
+system.cpu0.dtb.write_accesses               72663499                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        161752366                       # DTB hits
-system.cpu0.dtb.misses                         104839                       # DTB misses
-system.cpu0.dtb.accesses                    161857205                       # DTB accesses
+system.cpu0.dtb.hits                        153094532                       # DTB hits
+system.cpu0.dtb.misses                         105954                       # DTB misses
+system.cpu0.dtb.accesses                    153200486                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -502,240 +504,240 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    57460                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                57460                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2          729                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        51308                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples        57460                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          57460    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        57460                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        52037                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 22020.322079                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 19981.613647                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 15973.969343                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-32767        48320     92.86%     92.86% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-65535         2946      5.66%     98.52% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-98303          248      0.48%     98.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::98304-131071          406      0.78%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-163839           23      0.04%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::163840-196607            9      0.02%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-229375           33      0.06%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::229376-262143            6      0.01%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-294911           15      0.03%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::294912-327679           16      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-360447            8      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::360448-393215            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-425983            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        52037                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                    53482                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                53482                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2          578                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        47523                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples        53482                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          53482    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        53482                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        48101                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 21551.932392                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 19925.788685                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 13354.053067                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767        45094     93.75%     93.75% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535         2542      5.28%     99.03% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-98303          133      0.28%     99.31% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-131071          277      0.58%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839            5      0.01%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-196607            6      0.01%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-229375           18      0.04%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::229376-262143            2      0.00%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911            5      0.01%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679            8      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-360447            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::360448-393215            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-425983            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        48101                       # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walksPending::samples   -326738796                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::0     -326738796    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::total   -326738796                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        51308     98.60%     98.60% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M          729      1.40%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        52037                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K        47523     98.80%     98.80% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M          578      1.20%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        48101                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        57460                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        57460                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        53482                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        53482                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        52037                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        52037                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       109497                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   453477294                       # ITB inst hits
-system.cpu0.itb.inst_misses                     57460                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        48101                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        48101                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       101583                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   428491503                       # ITB inst hits
+system.cpu0.itb.inst_misses                     53482                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              40618                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1028                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   27698                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              39897                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1024                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   24315                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               453534754                       # ITB inst accesses
-system.cpu0.itb.hits                        453477294                       # DTB hits
-system.cpu0.itb.misses                          57460                       # DTB misses
-system.cpu0.itb.accesses                    453534754                       # DTB accesses
-system.cpu0.numCycles                     94992773961                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               428544985                       # ITB inst accesses
+system.cpu0.itb.hits                        428491503                       # DTB hits
+system.cpu0.itb.misses                          53482                       # DTB misses
+system.cpu0.itb.accesses                    428544985                       # DTB accesses
+system.cpu0.numCycles                     94913359253                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  453209687                       # Number of instructions committed
-system.cpu0.committedOps                    531499422                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            488089676                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                379595                       # Number of float alu accesses
-system.cpu0.num_func_calls                   26785883                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     68737200                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   488089676                       # number of integer instructions
-system.cpu0.num_fp_insts                       379595                       # number of float instructions
-system.cpu0.num_int_register_reads          710027821                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         387728381                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              639718                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             261592                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           118698555                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes          118319526                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    161743236                       # number of memory refs
-system.cpu0.num_load_insts                   85268904                       # Number of load instructions
-system.cpu0.num_store_insts                  76474332                       # Number of store instructions
-system.cpu0.num_idle_cycles              93849963781.964020                       # Number of idle cycles
-system.cpu0.num_busy_cycles              1142810179.035976                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.012030                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.987970                       # Percentage of idle cycles
-system.cpu0.Branches                        100837041                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                368748107     69.34%     69.34% # Class of executed instruction
-system.cpu0.op_class::IntMult                 1224660      0.23%     69.57% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    64156      0.01%     69.58% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             29994      0.01%     69.59% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.59% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.59% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.59% # Class of executed instruction
-system.cpu0.op_class::MemRead                85268904     16.03%     85.62% # Class of executed instruction
-system.cpu0.op_class::MemWrite               76474332     14.38%    100.00% # Class of executed instruction
+system.cpu0.committedInsts                  428232691                       # Number of instructions committed
+system.cpu0.committedOps                    502476550                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            461534262                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                406829                       # Number of float alu accesses
+system.cpu0.num_func_calls                   25466680                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     64818437                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   461534262                       # number of integer instructions
+system.cpu0.num_fp_insts                       406829                       # number of float instructions
+system.cpu0.num_int_register_reads          668961319                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         366250009                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              674435                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             305880                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           111832425                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes          111484776                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    153083738                       # number of memory refs
+system.cpu0.num_load_insts                   80450777                       # Number of load instructions
+system.cpu0.num_store_insts                  72632961                       # Number of store instructions
+system.cpu0.num_idle_cycles              93826651579.898026                       # Number of idle cycles
+system.cpu0.num_busy_cycles              1086707673.101977                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.011449                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.988551                       # Percentage of idle cycles
+system.cpu0.Branches                         95423987                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                348470598     69.31%     69.31% # Class of executed instruction
+system.cpu0.op_class::IntMult                 1120076      0.22%     69.53% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    60052      0.01%     69.54% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             44021      0.01%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::MemRead                80450777     16.00%     85.55% # Class of executed instruction
+system.cpu0.op_class::MemWrite               72632961     14.45%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 531810153                       # Class of executed instruction
+system.cpu0.op_class::total                 502778486                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   14069                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements          5594005                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          472.878328                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          155905526                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          5594517                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            27.867558                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       3986453000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   472.878328                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.923590                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.923590                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                   14022                       # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements          5233253                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          480.798924                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          147607157                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          5233765                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            28.202863                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       3987157000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   480.798924                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.939060                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.939060                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1           52                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          337                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          415                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        329066714                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       329066714                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     79426163                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       79426163                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     72239104                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      72239104                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       186194                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       186194                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       137014                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       137014                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1774977                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1774977                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1742409                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1742409                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    151665267                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       151665267                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    151851461                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      151851461                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      3027243                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      3027243                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1374655                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1374655                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       667737                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       667737                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       757348                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total       757348                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       163489                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       163489                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       194173                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       194173                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      4401898                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       4401898                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      5069635                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      5069635                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  43551375000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  43551375000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  25743175500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  25743175500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  46783649000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  46783649000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2342479000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   2342479000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4171693500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   4171693500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2590500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2590500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  69294550500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  69294550500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  69294550500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  69294550500                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     82453406                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     82453406                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     73613759                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     73613759                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       853931                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       853931                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       894362                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total       894362                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1938466                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      1938466                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1936582                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      1936582                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    156067165                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    156067165                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    156921096                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    156921096                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036715                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.036715                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018674                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.018674                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.781957                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.781957                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.846803                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.846803                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.084339                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.084339                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.100266                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.100266                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.028205                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.028205                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032307                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.032307                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14386.481363                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14386.481363                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18727.008231                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 18727.008231                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 61772.988111                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 61772.988111                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14328.052652                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14328.052652                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21484.415959                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21484.415959                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses        311404737                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       311404737                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     74943991                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       74943991                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     68564818                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      68564818                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       176894                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       176894                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       135340                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       135340                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1719391                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1719391                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1677698                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1677698                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    143508809                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       143508809                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    143685703                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      143685703                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      2840159                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      2840159                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1279764                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1279764                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       601589                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       601589                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       758772                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       758772                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       148889                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       148889                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       188945                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       188945                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      4119923                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       4119923                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      4721512                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      4721512                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  41012776500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  41012776500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  24489617000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  24489617000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  46337666000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  46337666000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2203666500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   2203666500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4074419000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   4074419000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2847000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2847000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  65502393500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  65502393500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  65502393500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  65502393500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     77784150                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     77784150                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     69844582                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     69844582                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       778483                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       778483                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       894112                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total       894112                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1868280                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      1868280                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1866643                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      1866643                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    147628732                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    147628732                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    148407215                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    148407215                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036513                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.036513                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018323                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.018323                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.772771                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.772771                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.848632                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.848632                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.079693                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.079693                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.101222                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.101222                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027907                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.027907                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.031815                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.031815                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14440.310032                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14440.310032                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19136.041489                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 19136.041489                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 61069.288271                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 61069.288271                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14800.734104                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14800.734104                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21564.047739                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21564.047739                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15741.970963                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 15741.970963                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13668.548229                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 13668.548229                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15898.936339                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 15898.936339                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13873.181621                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 13873.181621                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -744,158 +746,157 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      3814789                       # number of writebacks
-system.cpu0.dcache.writebacks::total          3814789                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        30828                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        30828                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21250                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        21250                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        41671                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        41671                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data        52078                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total        52078                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data        52078                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total        52078                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2996415                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      2996415                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1353405                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1353405                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       662134                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       662134                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       757348                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       757348                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       121818                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       121818                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       194173                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       194173                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4349820                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4349820                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      5011954                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      5011954                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        27090                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        27090                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        26689                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        26689                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        53779                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        53779                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  39330539500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  39330539500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  23857005000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  23857005000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13760399000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  13760399000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  46026301000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  46026301000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1597973500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1597973500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3977579500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3977579500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2531500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2531500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  63187544500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  63187544500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  76947943500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  76947943500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4585847500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4585847500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   4300128500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4300128500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   8885976000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   8885976000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036341                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036341                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018385                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018385                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.775395                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.775395                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.846803                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.846803                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.062842                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.062842                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.100266                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.100266                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027871                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.027871                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031939                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.031939                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13125.865242                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13125.865242                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17627.395347                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17627.395347                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20781.894601                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20781.894601                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 60772.988111                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 60772.988111                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13117.712489                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13117.712489                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20484.719812                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20484.719812                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      3560219                       # number of writebacks
+system.cpu0.dcache.writebacks::total          3560219                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        30162                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        30162                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21215                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        21215                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        39917                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        39917                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data        51377                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total        51377                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data        51377                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total        51377                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2809997                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      2809997                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1258549                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1258549                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       595949                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       595949                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       758772                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       758772                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       108972                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       108972                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       188945                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       188945                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      4068546                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4068546                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      4664495                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      4664495                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        26231                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        26231                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        25453                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        25453                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        51684                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        51684                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  36991828000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  36991828000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  22707525500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  22707525500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  12844611500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  12844611500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  45578894000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  45578894000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1445565000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1445565000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3885534000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3885534000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2787000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2787000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  59699353500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  59699353500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  72543965000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  72543965000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4455810500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4455810500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   4073355500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4073355500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   8529166000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   8529166000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036126                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036126                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018019                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018019                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.765526                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.765526                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.848632                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.848632                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.058327                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.058327                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.101222                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.101222                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027559                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.027559                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031430                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.031430                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13164.365656                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13164.365656                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18042.623291                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18042.623291                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21553.205895                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21553.205895                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 60069.288271                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 60069.288271                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13265.471864                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13265.471864                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20564.365291                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20564.365291                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14526.473394                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14526.473394                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15352.883027                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15352.883027                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169281.930602                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 169281.930602                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161119.880850                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 161119.880850                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 165231.335651                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 165231.335651                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14673.387864                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14673.387864                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15552.372765                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15552.372765                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169868.114064                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 169868.114064                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 160034.396731                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 160034.396731                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 165025.268942                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 165025.268942                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          4817420                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.881006                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          448659362                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          4817932                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            93.122809                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      42527405000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.881006                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999768                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999768                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          4666970                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.880807                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          423824020                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          4667482                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            90.803568                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      42558943000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.880807                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999767                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999767                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          158                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          121                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          229                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          326                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          124                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        911772520                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       911772520                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    448659362                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      448659362                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    448659362                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       448659362                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    448659362                       # number of overall hits
-system.cpu0.icache.overall_hits::total      448659362                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      4817932                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      4817932                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      4817932                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       4817932                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      4817932                       # number of overall misses
-system.cpu0.icache.overall_misses::total      4817932                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  51018469500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  51018469500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  51018469500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  51018469500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  51018469500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  51018469500                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    453477294                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    453477294                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    453477294                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    453477294                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    453477294                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    453477294                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.010624                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.010624                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.010624                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.010624                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.010624                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.010624                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10589.287997                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10589.287997                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10589.287997                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10589.287997                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10589.287997                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10589.287997                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        861650489                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       861650489                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    423824020                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      423824020                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    423824020                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       423824020                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    423824020                       # number of overall hits
+system.cpu0.icache.overall_hits::total      423824020                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      4667483                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      4667483                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      4667483                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       4667483                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      4667483                       # number of overall misses
+system.cpu0.icache.overall_misses::total      4667483                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  48694088500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  48694088500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  48694088500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  48694088500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  48694088500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  48694088500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    428491503                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    428491503                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    428491503                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    428491503                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    428491503                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    428491503                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.010893                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.010893                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.010893                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.010893                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.010893                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.010893                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10432.622572                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10432.622572                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10432.622572                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10432.622572                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10432.622572                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10432.622572                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -904,251 +905,252 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      4817932                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      4817932                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      4817932                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      4817932                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      4817932                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      4817932                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      4667483                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      4667483                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      4667483                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      4667483                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      4667483                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      4667483                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  48609503500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  48609503500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  48609503500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  48609503500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  48609503500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  48609503500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  46360347000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  46360347000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  46360347000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  46360347000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  46360347000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  46360347000                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3777715000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   3777715000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   3777715000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   3777715000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.010624                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010624                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.010624                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.010624                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.010624                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.010624                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10089.287997                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10089.287997                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10089.287997                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10089.287997                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10089.287997                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10089.287997                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.010893                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010893                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.010893                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.010893                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.010893                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.010893                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9932.622572                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9932.622572                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9932.622572                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  9932.622572                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9932.622572                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  9932.622572                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87599.188406                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87599.188406                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87599.188406                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87599.188406                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      7903007                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      7903048                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit           35                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      7039817                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      7039817                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage      1031104                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements         2447325                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       15787.482525                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          17072683                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2462926                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            6.931870                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle     38930323500                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  7763.481265                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    64.845053                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    94.926815                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  3265.491531                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3523.056672                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1075.681189                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.473845                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003958                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.005794                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.199310                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.215030                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.065654                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.963591                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1662                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           82                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        13857                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          291                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          746                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          625                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           11                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           46                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           25                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          107                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         2497                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5813                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         5388                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.101440                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005005                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.845764                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       352133802                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      352133802                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       213691                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       129371                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total        343062                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks      3814786                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total      3814786                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        99833                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total        99833                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        32914                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total        32914                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       902621                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       902621                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      4275985                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      4275985                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2838458                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total      2838458                       # number of ReadSharedReq hits
-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       175241                       # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total       175241                       # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       213691                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       129371                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      4275985                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      3741079                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        8360126                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       213691                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       129371                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      4275985                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      3741079                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       8360126                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker         9038                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         7286                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        16324                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       121358                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       121358                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       161252                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       161252                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            7                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            7                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       246467                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       246467                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       541947                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total       541947                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       941909                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total       941909                       # number of ReadSharedReq misses
-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       580933                       # number of InvalidateReq misses
-system.cpu0.l2cache.InvalidateReq_misses::total       580933                       # number of InvalidateReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker         9038                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker         7286                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       541947                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1188376                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total      1746647                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker         9038                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker         7286                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       541947                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1188376                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      1746647                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    297968500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    261413000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total    559381500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2650604000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total   2650604000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3370536000                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3370536000                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2441998                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2441998                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  11722428500                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total  11722428500                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  15931119500                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total  15931119500                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  30566703000                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total  30566703000                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  43739049000                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::total  43739049000                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    297968500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    261413000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst  15931119500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data  42289131500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total  58779632500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    297968500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    261413000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst  15931119500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data  42289131500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  58779632500                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       222729                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       136657                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total       359386                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks      3814786                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total      3814786                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       221191                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       221191                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       194166                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       194166                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            7                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            7                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1149088                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total      1149088                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      4817932                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      4817932                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3780367                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total      3780367                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       756174                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::total       756174                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       222729                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       136657                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      4817932                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data      4929455                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total     10106773                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       222729                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       136657                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      4817932                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data      4929455                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     10106773                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.040578                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.053316                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.045422                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.548657                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.548657                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.830485                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.830485                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.prefetcher.pfSpanPage       925071                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements         2212798                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16140.904175                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          16304400                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2228972                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            7.314762                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle     38965596000                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks  7022.512638                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    61.899316                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    62.792978                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  3705.081021                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  4185.062005                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1103.556217                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.428620                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003778                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003833                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.226140                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.255436                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.067356                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.985163                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1459                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           55                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14660                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           13                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          322                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          603                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          521                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           18                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           23                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           14                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          957                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4495                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5217                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3928                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.089050                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.003357                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.894775                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       335472623                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      335472623                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       224520                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       122258                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total        346778                       # number of ReadReq hits
+system.cpu0.l2cache.Writeback_hits::writebacks      3560218                       # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total      3560218                       # number of Writeback hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        92512                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total        92512                       # number of UpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        28864                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::total        28864                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       829198                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       829198                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      4185639                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      4185639                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2620915                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total      2620915                       # number of ReadSharedReq hits
+system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       197417                       # number of InvalidateReq hits
+system.cpu0.l2cache.InvalidateReq_hits::total       197417                       # number of InvalidateReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       224520                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker       122258                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      4185639                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data      3450113                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total        7982530                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       224520                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker       122258                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      4185639                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data      3450113                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total       7982530                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker         8873                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         6826                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total        15699                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       123328                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total       123328                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       160077                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total       160077                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            4                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total            4                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data       230435                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total       230435                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       481844                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total       481844                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       894003                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total       894003                       # number of ReadSharedReq misses
+system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       560192                       # number of InvalidateReq misses
+system.cpu0.l2cache.InvalidateReq_misses::total       560192                       # number of InvalidateReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker         8873                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker         6826                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst       481844                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data      1124438                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total      1621981                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker         8873                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker         6826                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst       481844                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data      1124438                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total      1621981                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    259670000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    210027000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total    469697000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2651049500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total   2651049500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3319563500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3319563500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2697000                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2697000                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  11221935999                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total  11221935999                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  14420808000                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total  14420808000                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  28972230000                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total  28972230000                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  43145750500                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::total  43145750500                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    259670000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    210027000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst  14420808000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data  40194165999                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total  55084670999                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    259670000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    210027000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  14420808000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data  40194165999                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  55084670999                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       233393                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       129084                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total       362477                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::writebacks      3560218                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total      3560218                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       215840                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total       215840                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       188941                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total       188941                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            4                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            4                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1059633                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total      1059633                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      4667483                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      4667483                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3514918                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total      3514918                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       757609                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::total       757609                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       233393                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       129084                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      4667483                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data      4574551                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total      9604511                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       233393                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       129084                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      4667483                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data      4574551                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      9604511                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.038017                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.052880                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.043310                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.571386                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.571386                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.847233                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.847233                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.214489                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.214489                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.112485                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.112485                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.249158                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.249158                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.768253                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.768253                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.040578                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.053316                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.112485                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.241077                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.172819                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.040578                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.053316                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.112485                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.241077                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.172819                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32968.411153                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 35878.808674                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34267.428326                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21841.197119                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21841.197119                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20902.289584                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20902.289584                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 348856.857143                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 348856.857143                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 47561.858180                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47561.858180                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 29396.083934                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 29396.083934                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32451.864246                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32451.864246                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 75291.038726                       # average InvalidateReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 75291.038726                       # average InvalidateReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32968.411153                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 35878.808674                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29396.083934                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35585.649239                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 33652.840271                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32968.411153                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 35878.808674                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29396.083934                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35585.649239                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 33652.840271                       # average overall miss latency
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.217467                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.217467                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.103234                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.103234                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.254345                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.254345                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.739421                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.739421                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.038017                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.052880                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.103234                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.245803                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.168877                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.038017                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.052880                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.103234                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.245803                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.168877                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 29265.186521                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 30768.678582                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 29918.912033                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21495.925499                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21495.925499                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20737.292053                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20737.292053                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       674250                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       674250                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48698.921600                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48698.921600                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 29928.375159                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 29928.375159                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32407.307358                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32407.307358                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 77019.576324                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 77019.576324                       # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 29265.186521                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 30768.678582                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29928.375159                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35746.004670                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 33961.354047                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 29265.186521                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 30768.678582                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29928.375159                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35746.004670                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 33961.354047                       # average overall miss latency
 system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -1157,218 +1159,216 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1370697                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1370697                       # number of writebacks
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         4625                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         4625                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          320                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          320                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         4945                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         4945                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         4945                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         4945                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker         9038                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         7286                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        16324                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks        97439                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::total        97439                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       677798                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       677798                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       121358                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       121358                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       161252                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       161252                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            7                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            7                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       241842                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       241842                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       541947                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       541947                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       941589                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       941589                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       580933                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::total       580933                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker         9038                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         7286                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       541947                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1183431                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total      1741702                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker         9038                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         7286                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       541947                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1183431                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       677798                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total      2419500                       # number of overall MSHR misses
+system.cpu0.l2cache.writebacks::writebacks      1248318                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1248318                       # number of writebacks
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         3799                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         3799                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          319                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          319                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         4118                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total         4118                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         4118                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total         4118                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker         8873                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         6826                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total        15699                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks        86363                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::total        86363                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       615430                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       615430                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       123328                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total       123328                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       160077                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       160077                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            4                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       226636                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total       226636                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       481844                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       481844                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       893684                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       893684                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       560192                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::total       560192                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker         8873                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         6826                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       481844                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1120320                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total      1617863                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker         8873                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         6826                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       481844                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1120320                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       615430                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total      2233293                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        27090                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        70215                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        26689                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        26689                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        26231                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        69356                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        25453                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        25453                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        53779                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        96904                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    243740500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    217697000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    461437500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  28787351301                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  28787351301                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2500247000                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2500247000                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2505266500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2505266500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2087998                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2087998                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   9802286000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   9802286000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  12679437500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  12679437500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  24890887500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  24890887500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  40253451000                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  40253451000                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    243740500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    217697000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  12679437500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  34693173500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total  47834048500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    243740500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    217697000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  12679437500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  34693173500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  28787351301                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  76621399801                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        51684                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        94809                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    206432000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    169071000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    375503000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  25855371219                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  25855371219                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2504859500                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2504859500                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2454464000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2454464000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2337000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2337000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   9468370499                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   9468370499                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  11529744000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  11529744000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  23586536500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  23586536500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  39784598500                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  39784598500                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    206432000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    169071000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  11529744000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  33054906999                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total  44960153999                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    206432000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    169071000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  11529744000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  33054906999                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  25855371219                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  70815525218                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3454277500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4369127500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7823405000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   4099961000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4099961000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4245962500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7700240000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3882458000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3882458000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   3454277500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   8469088500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11923366000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.040578                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.053316                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.045422                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   8128420500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11582698000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.038017                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.052880                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.043310                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.548657                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.548657                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.830485                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.830485                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.571386                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.571386                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.847233                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.847233                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.210464                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.210464                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.112485                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.112485                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.249073                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.249073                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.768253                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.768253                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.040578                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.053316                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.112485                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.240073                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.172330                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.040578                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.053316                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.112485                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.240073                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.213882                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.213882                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.103234                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.103234                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.254255                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.254255                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.739421                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.739421                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.038017                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.052880                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.103234                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.244903                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.168448                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.038017                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.052880                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.103234                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.244903                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.239394                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26968.411153                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 29878.808674                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28267.428326                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 42471.874070                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 42471.874070                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20602.242951                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20602.242951                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15536.343735                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15536.343735                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 298285.428571                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 298285.428571                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40531.776945                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40531.776945                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 23396.083934                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23396.083934                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26434.981186                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26434.981186                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69291.038726                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69291.038726                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26968.411153                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 29878.808674                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23396.083934                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29315.755207                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27463.968291                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26968.411153                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 29878.808674                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23396.083934                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29315.755207                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 42471.874070                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 31668.278488                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.232525                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 23265.186521                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 24768.678582                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23918.912033                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 42011.879855                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 42011.879855                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20310.549916                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20310.549916                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15333.020984                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15333.020984                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       584250                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       584250                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41777.875090                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41777.875090                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 23928.375159                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23928.375159                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26392.479333                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26392.479333                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 71019.576324                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 71019.576324                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 23265.186521                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 24768.678582                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23928.375159                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29504.879855                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27789.840054                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 23265.186521                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 24768.678582                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23928.375159                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29504.879855                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 42011.879855                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 31709.016783                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80099.188406                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 161281.930602                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 111420.707826                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153619.880850                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153619.880850                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 161868.114064                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 111024.857258                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 152534.396731                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 152534.396731                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80099.188406                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 157479.471541                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 123043.073557                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 157271.505688                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 122168.760350                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq        556196                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      9235290                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        37997                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        26689                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback      7191964                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict      8875110                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       964168                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp            5                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       427001                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       350742                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       480184                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           44                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           96                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1494626                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1158048                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      4817932                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5665215                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq       862902                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp       756174                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     14539205                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18068890                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       308145                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       526057                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         33442297                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    308520148                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    566266158                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1093256                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1781832                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         877661394                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    9623929                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     31244724                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       1.314212                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.464201                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq        548810                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      8811478                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        38603                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        25453                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback      6868539                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      8637410                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       769123                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       445989                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       351950                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       473125                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           65                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          121                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1446257                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1069406                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      4667483                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5564741                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       864337                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       757609                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     14087759                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     16981197                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       288818                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       540500                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         31898274                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    298891412                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    527370978                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1032672                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1867144                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         829162206                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    9613339                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     30204161                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       1.324614                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.468231                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1          21427251     68.58%     68.58% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2           9817473     31.42%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1          20399459     67.54%     67.54% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2           9804702     32.46%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      31244724                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   14779167493                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      30204161                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   14006094999                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    183875487                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    188261483                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   7270023000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   7044349500                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   8020770875                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   7482254107                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    171488000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    159734000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    303329497                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    307107000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -1399,74 +1399,68 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   102079                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               102079                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         8198                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        78187                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore           17                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       102062                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean     0.078384                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev    25.041362                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-511       102061    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                   101352                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               101352                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         8872                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        77968                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore            3                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       101349                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean     0.078935                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev    25.129292                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-511       101348    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::7680-8191            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       102062                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        86402                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 20584.963311                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 18803.464379                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 14594.922091                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767        82288     95.24%     95.24% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535         3069      3.55%     98.79% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303          485      0.56%     99.35% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-131071          417      0.48%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-163839           20      0.02%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::163840-196607           14      0.02%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-229375           31      0.04%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::229376-262143           11      0.01%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-294911           20      0.02%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::294912-327679           27      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-360447            7      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::360448-393215            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-425983            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        86402                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  -6989065760                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.774297                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.418044                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0    -1577450036     22.57%     22.57% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1    -5411615724     77.43%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  -6989065760                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        78188     90.51%     90.51% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M         8198      9.49%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total        86386                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       102079                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::total       101349                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        86843                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 20976.923874                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 18678.710286                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 17538.002789                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535        85298     98.22%     98.22% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1315      1.51%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607           45      0.05%     99.79% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143           84      0.10%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679           70      0.08%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215           23      0.03%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        86843                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples   -857364308                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean    -0.833676                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    -1572128036    183.37%    183.37% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1      714763728    -83.37%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total   -857364308                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        77968     89.78%     89.78% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M         8872     10.22%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        86840                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       101352                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       102079                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        86386                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       101352                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        86840                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        86386                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       188465                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        86840                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       188192                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    79156855                       # DTB read hits
-system.cpu1.dtb.read_misses                     74074                       # DTB read misses
-system.cpu1.dtb.write_hits                   72945567                       # DTB write hits
-system.cpu1.dtb.write_misses                    28005                       # DTB write misses
+system.cpu1.dtb.read_hits                    82714274                       # DTB read hits
+system.cpu1.dtb.read_misses                     74721                       # DTB read misses
+system.cpu1.dtb.write_hits                   75460503                       # DTB write hits
+system.cpu1.dtb.write_misses                    26631                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              40618                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1028                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   34474                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid              39897                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1024                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   38549                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  4171                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                  4418                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                     9254                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                79230929                       # DTB read accesses
-system.cpu1.dtb.write_accesses               72973572                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    10567                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                82788995                       # DTB read accesses
+system.cpu1.dtb.write_accesses               75487134                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        152102422                       # DTB hits
-system.cpu1.dtb.misses                         102079                       # DTB misses
-system.cpu1.dtb.accesses                    152204501                       # DTB accesses
+system.cpu1.dtb.hits                        158174777                       # DTB hits
+system.cpu1.dtb.misses                         101352                       # DTB misses
+system.cpu1.dtb.accesses                    158276129                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1496,241 +1490,242 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    60277                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                60277                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          437                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        54558                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        60277                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          60277    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        60277                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        54995                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 23406.355123                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 21056.017834                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 18686.344458                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767        50855     92.47%     92.47% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535         2976      5.41%     97.88% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303          347      0.63%     98.51% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071          645      1.17%     99.69% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839           26      0.05%     99.73% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607           14      0.03%     99.76% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375           61      0.11%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143            8      0.01%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911           27      0.05%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679           12      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-360447           10      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-425983            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-491519            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::491520-524287            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        54995                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  -1687858036                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    -1687858036    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  -1687858036                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        54558     99.21%     99.21% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          437      0.79%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        54995                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                    60693                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                60693                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          593                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        54830                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        60693                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          60693    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        60693                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        55423                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 24648.566480                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 21393.176042                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 22659.824821                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767        49924     90.08%     90.08% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535         3716      6.70%     96.78% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303          553      1.00%     97.78% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071          965      1.74%     99.52% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839           32      0.06%     99.58% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607           27      0.05%     99.63% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375           86      0.16%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143           15      0.03%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911           45      0.08%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679           26      0.05%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447           10      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::360448-393215           12      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-425983            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::425984-458751            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-491519            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::491520-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        55423                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  -1656015036                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    -1656015036    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  -1656015036                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        54830     98.93%     98.93% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          593      1.07%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        55423                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        60277                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        60277                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        60693                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        60693                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        54995                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        54995                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       115272                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   419908062                       # ITB inst hits
-system.cpu1.itb.inst_misses                     60277                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        55423                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        55423                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       116116                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   437193188                       # ITB inst hits
+system.cpu1.itb.inst_misses                     60693                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              40618                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1028                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   24325                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              39897                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1024                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   27130                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               419968339                       # ITB inst accesses
-system.cpu1.itb.hits                        419908062                       # DTB hits
-system.cpu1.itb.misses                          60277                       # DTB misses
-system.cpu1.itb.accesses                    419968339                       # DTB accesses
-system.cpu1.numCycles                     94992773961                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               437253881                       # ITB inst accesses
+system.cpu1.itb.hits                        437193188                       # DTB hits
+system.cpu1.itb.misses                          60693                       # DTB misses
+system.cpu1.itb.accesses                    437253881                       # DTB accesses
+system.cpu1.numCycles                     94913359253                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  419630835                       # Number of instructions committed
-system.cpu1.committedOps                    495261733                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            455389756                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                523939                       # Number of float alu accesses
-system.cpu1.num_func_calls                   25402387                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     63797614                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   455389756                       # number of integer instructions
-system.cpu1.num_fp_insts                       523939                       # number of float instructions
-system.cpu1.num_int_register_reads          660733277                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         360799808                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              826391                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes             485612                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           108763380                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes          108525865                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                    152092816                       # number of memory refs
-system.cpu1.num_load_insts                   79152639                       # Number of load instructions
-system.cpu1.num_store_insts                  72940177                       # Number of store instructions
-system.cpu1.num_idle_cycles              94000482737.518021                       # Number of idle cycles
-system.cpu1.num_busy_cycles              992291223.481979                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.010446                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.989554                       # Percentage of idle cycles
-system.cpu1.Branches                         93826575                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                342323632     69.08%     69.08% # Class of executed instruction
-system.cpu1.op_class::IntMult                  986133      0.20%     69.28% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    54444      0.01%     69.29% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.29% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.29% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.29% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.29% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.29% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.29% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.29% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.29% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.29% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.29% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.29% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.29% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.29% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.29% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.29% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.29% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             82001      0.02%     69.31% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.31% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.31% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.31% # Class of executed instruction
-system.cpu1.op_class::MemRead                79152639     15.97%     85.28% # Class of executed instruction
-system.cpu1.op_class::MemWrite               72940177     14.72%    100.00% # Class of executed instruction
+system.cpu1.committedInsts                  436909780                       # Number of instructions committed
+system.cpu1.committedOps                    515262081                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            474007520                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                488695                       # Number of float alu accesses
+system.cpu1.num_func_calls                   26553696                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     66234119                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   474007520                       # number of integer instructions
+system.cpu1.num_fp_insts                       488695                       # number of float instructions
+system.cpu1.num_int_register_reads          687449190                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes         375811208                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              781283                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes             430208                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           112572477                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes          112287439                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                    158166235                       # number of memory refs
+system.cpu1.num_load_insts                   82712263                       # Number of load instructions
+system.cpu1.num_store_insts                  75453972                       # Number of store instructions
+system.cpu1.num_idle_cycles              93876093406.586029                       # Number of idle cycles
+system.cpu1.num_busy_cycles              1037265846.413978                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.010929                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.989071                       # Percentage of idle cycles
+system.cpu1.Branches                         97493416                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                356171607     69.09%     69.09% # Class of executed instruction
+system.cpu1.op_class::IntMult                 1079497      0.21%     69.30% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    59940      0.01%     69.31% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             68277      0.01%     69.32% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.32% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.32% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.32% # Class of executed instruction
+system.cpu1.op_class::MemRead                82712263     16.04%     85.36% # Class of executed instruction
+system.cpu1.op_class::MemWrite               75453972     14.64%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 495539069                       # Class of executed instruction
+system.cpu1.op_class::total                 515545598                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    5086                       # number of quiesce instructions executed
-system.cpu1.dcache.tags.replacements          4879882                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          454.664905                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          147036928                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          4880392                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            30.128098                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8391455352000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   454.664905                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.888017                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.888017                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          414                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        309114667                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       309114667                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     73769374                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       73769374                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     69164773                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      69164773                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       181014                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       181014                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data       188653                       # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total       188653                       # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1698614                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1698614                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1666903                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1666903                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    142934147                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       142934147                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    143115161                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      143115161                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      2759570                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      2759570                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      1240940                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      1240940                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       581228                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       581228                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data       477261                       # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total       477261                       # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       156018                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       156018                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       186042                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       186042                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      4000510                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       4000510                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      4581738                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      4581738                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  39233003500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  39233003500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  20835462500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  20835462500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  14509055000                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total  14509055000                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2381741000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   2381741000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   3985246000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   3985246000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1637000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1637000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  60068466000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  60068466000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  60068466000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  60068466000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     76528944                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     76528944                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     70405713                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     70405713                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       762242                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       762242                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       665914                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total       665914                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1854632                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      1854632                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1852945                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      1852945                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    146934657                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    146934657                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    147696899                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    147696899                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.036059                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.036059                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.017626                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.017626                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.762524                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.762524                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.716701                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total     0.716701                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.084123                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.084123                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.100403                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.100403                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.027226                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.027226                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.031021                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.031021                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14217.071319                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14217.071319                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16790.064387                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 16790.064387                       # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 30400.671750                       # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 30400.671750                       # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15265.809073                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15265.809073                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21421.216715                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21421.216715                       # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce                    5256                       # number of quiesce instructions executed
+system.cpu1.dcache.tags.replacements          5176711                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          457.282743                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          152806636                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          5177218                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            29.515202                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8391490917000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   457.282743                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.893130                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.893130                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          507                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          474                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.990234                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses        321544722                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       321544722                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     77092949                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       77092949                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     71608224                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      71608224                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       188155                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       188155                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data       187532                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total       187532                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1684198                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1684198                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1657450                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1657450                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    148701173                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       148701173                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    148889328                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      148889328                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      2950342                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      2950342                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      1305907                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      1305907                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       613815                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       613815                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       479868                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       479868                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       172330                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       172330                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       197330                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       197330                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      4256249                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       4256249                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      4870064                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      4870064                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  42135771000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  42135771000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  22153910000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  22153910000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  15218762000                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  15218762000                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2580362000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   2580362000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4225919000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   4225919000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2953000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2953000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  64289681000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  64289681000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  64289681000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  64289681000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     80043291                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     80043291                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     72914131                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     72914131                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       801970                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       801970                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       667400                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       667400                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1856528                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      1856528                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1854780                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      1854780                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    152957422                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    152957422                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    153759392                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    153759392                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.036859                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.036859                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.017910                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.017910                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.765384                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.765384                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.719011                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.719011                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.092824                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.092824                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.106390                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.106390                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.027826                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.027826                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.031673                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.031673                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14281.656499                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14281.656499                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16964.385672                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 16964.385672                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 31714.475647                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 31714.475647                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14973.376661                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14973.376661                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21415.491816                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21415.491816                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15015.202062                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 15015.202062                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13110.410504                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 13110.410504                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15104.774415                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 15104.774415                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13200.993046                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 13200.993046                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1739,157 +1734,158 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      3169454                       # number of writebacks
-system.cpu1.dcache.writebacks::total          3169454                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        14967                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        14967                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          437                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total          437                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        44200                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        44200                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data        15404                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total        15404                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data        15404                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total        15404                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2744603                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      2744603                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1240503                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1240503                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       581228                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       581228                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       477261                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total       477261                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       111818                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       111818                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       186042                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       186042                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      3985106                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      3985106                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      4566334                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      4566334                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        11055                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        11055                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        11308                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        11308                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        22363                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        22363                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  35762824500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  35762824500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  19580379500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  19580379500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  11426394500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  11426394500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  14031794000                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  14031794000                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1521108000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1521108000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3799241000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3799241000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1600000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1600000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  55343204000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  55343204000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  66769598500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  66769598500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1911574500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   1911574500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2027224500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   2027224500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   3938799000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   3938799000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035864                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035864                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017619                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017619                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.762524                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.762524                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.716701                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.716701                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.060291                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.060291                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.100403                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.100403                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027122                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.027122                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.030917                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.030917                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13030.235885                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13030.235885                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15784.225834                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15784.225834                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19659.057203                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19659.057203                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 29400.671750                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 29400.671750                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13603.426997                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13603.426997                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20421.415594                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20421.415594                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      3350646                       # number of writebacks
+system.cpu1.dcache.writebacks::total          3350646                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        17552                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        17552                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          421                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total          421                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        45020                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        45020                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data        17973                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total        17973                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data        17973                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total        17973                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2932790                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      2932790                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1305486                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1305486                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       613815                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       613815                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       479868                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       479868                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       127310                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       127310                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       197330                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       197330                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4238276                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4238276                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      4852091                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      4852091                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        12503                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total        12503                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        13150                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total        13150                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        25653                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        25653                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  38342874000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  38342874000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  20834838000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  20834838000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12333914500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  12333914500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  14738894000                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  14738894000                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1690256500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1690256500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4028650000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4028650000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2892000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2892000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  59177712000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  59177712000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  71511626500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  71511626500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2070021000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2070021000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2282534000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   2282534000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   4352555000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   4352555000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036640                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036640                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017904                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017904                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.765384                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.765384                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.719011                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.719011                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.068574                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.068574                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.106390                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.106390                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027709                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.027709                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031556                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.031556                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13073.855953                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13073.855953                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15959.449584                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15959.449584                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20093.862972                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20093.862972                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 30714.475647                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 30714.475647                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13276.698610                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13276.698610                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20415.800943                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20415.800943                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13887.511148                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13887.511148                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14622.145139                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14622.145139                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172914.925373                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172914.925373                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179273.478953                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 179273.478953                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 176130.170371                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 176130.170371                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13962.684828                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13962.684828                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14738.311070                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14738.311070                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165561.945133                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165561.945133                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 173576.730038                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173576.730038                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 169670.408919                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 169670.408919                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          5061942                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          496.285809                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          414845603                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          5062454                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            81.945555                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8391427807000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.285809                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969308                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.969308                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements          5209177                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          496.272261                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          431983494                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          5209689                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            82.919248                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8391463454000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.272261                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969282                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.969282                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          327                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          126                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          440                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        844878583                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       844878583                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    414845603                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      414845603                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    414845603                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       414845603                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    414845603                       # number of overall hits
-system.cpu1.icache.overall_hits::total      414845603                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      5062459                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      5062459                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      5062459                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       5062459                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      5062459                       # number of overall misses
-system.cpu1.icache.overall_misses::total      5062459                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  51775886000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  51775886000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  51775886000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  51775886000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  51775886000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  51775886000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    419908062                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    419908062                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    419908062                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    419908062                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    419908062                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    419908062                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.012056                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.012056                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.012056                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.012056                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.012056                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.012056                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10227.418336                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 10227.418336                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10227.418336                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 10227.418336                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10227.418336                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 10227.418336                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses        879596070                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       879596070                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    431983494                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      431983494                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    431983494                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       431983494                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    431983494                       # number of overall hits
+system.cpu1.icache.overall_hits::total      431983494                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      5209694                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      5209694                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      5209694                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       5209694                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      5209694                       # number of overall misses
+system.cpu1.icache.overall_misses::total      5209694                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  53989351000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  53989351000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  53989351000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  53989351000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  53989351000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  53989351000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    437193188                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    437193188                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    437193188                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    437193188                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    437193188                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    437193188                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.011916                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.011916                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.011916                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.011916                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.011916                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.011916                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10363.248014                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 10363.248014                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10363.248014                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 10363.248014                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10363.248014                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 10363.248014                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1898,256 +1894,251 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5062459                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      5062459                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      5062459                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      5062459                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      5062459                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      5062459                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5209694                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      5209694                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      5209694                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      5209694                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      5209694                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      5209694                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          110                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          110                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  49244656500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  49244656500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  49244656500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  49244656500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  49244656500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  49244656500                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9661500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      9661500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      9661500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      9661500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.012056                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.012056                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.012056                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.012056                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.012056                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.012056                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9727.418336                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9727.418336                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9727.418336                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  9727.418336                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9727.418336                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  9727.418336                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87831.818182                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 87831.818182                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87831.818182                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 87831.818182                       # average overall mshr uncacheable latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  51384504000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  51384504000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  51384504000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  51384504000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  51384504000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  51384504000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9739500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      9739500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      9739500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      9739500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011916                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.011916                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.011916                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.011916                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.011916                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.011916                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9863.248014                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9863.248014                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9863.248014                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  9863.248014                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9863.248014                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  9863.248014                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88540.909091                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 88540.909091                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88540.909091                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 88540.909091                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      6553328                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      6553344                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit           14                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      7168932                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      7168932                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       818232                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements         1797985                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13499.130791                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          17098114                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         1814056                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            9.425351                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    10027287971500                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  5261.606925                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    74.626364                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    80.602782                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3547.198081                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3740.075738                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   795.020901                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.321143                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004555                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004920                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.216504                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.228276                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.048524                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.823922                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1537                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           61                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14473                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           17                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          338                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          619                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          563                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           23                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           24                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           14                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          884                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4486                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5048                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3979                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.093811                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003723                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.883362                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       335653129                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      335653129                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       217635                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       143511                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        361146                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks      3169452                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total      3169452                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        61375                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total        61375                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        29429                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total        29429                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       854276                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       854276                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4594945                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      4594945                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2597133                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total      2597133                       # number of ReadSharedReq hits
-system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       245829                       # number of InvalidateReq hits
-system.cpu1.l2cache.InvalidateReq_hits::total       245829                       # number of InvalidateReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       217635                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       143511                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      4594945                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3451409                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        8407500                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       217635                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       143511                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      4594945                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3451409                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       8407500                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker         9790                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         8267                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        18057                       # number of ReadReq misses
-system.cpu1.l2cache.Writeback_misses::writebacks            1                       # number of Writeback misses
-system.cpu1.l2cache.Writeback_misses::total            1                       # number of Writeback misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       120456                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       120456                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       156608                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       156608                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            5                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       206111                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       206111                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       467514                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total       467514                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       840516                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total       840516                       # number of ReadSharedReq misses
-system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       229973                       # number of InvalidateReq misses
-system.cpu1.l2cache.InvalidateReq_misses::total       229973                       # number of InvalidateReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker         9790                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         8267                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       467514                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1046627                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      1532198                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker         9790                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         8267                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       467514                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1046627                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      1532198                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    350581000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    322699500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total    673280500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2589720500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total   2589720500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3249045500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3249045500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1543999                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1543999                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   8558602000                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   8558602000                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  14244872000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total  14244872000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  26670955500                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total  26670955500                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  11700893500                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::total  11700893500                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    350581000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    322699500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  14244872000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data  35229557500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  50147710000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    350581000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    322699500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  14244872000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  35229557500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  50147710000                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       227425                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       151778                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       379203                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks      3169453                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total      3169453                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       181831                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       181831                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       186037                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       186037                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1060387                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1060387                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      5062459                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total      5062459                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3437649                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total      3437649                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       475802                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::total       475802                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       227425                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       151778                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      5062459                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data      4498036                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total      9939698                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       227425                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       151778                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      5062459                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data      4498036                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total      9939698                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.043047                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.054468                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.047618                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000000                       # miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_miss_rate::total     0.000000                       # miss rate for Writeback accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.662461                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.662461                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.841811                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.841811                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.prefetcher.pfSpanPage       888356                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements         2018400                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13471.145620                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          17736817                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         2034046                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            8.719968                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    9876432033500                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks  5731.708202                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    71.533292                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker   100.125774                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3516.826700                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3218.371115                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   832.580536                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.349836                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004366                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.006111                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.214650                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.196434                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.050817                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.822213                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1631                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           83                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13932                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          249                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          762                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          620                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           11                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           42                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           30                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1           12                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         2682                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         6101                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         5119                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.099548                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005066                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.850342                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       350300692                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      350300692                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       208719                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       141350                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        350069                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks      3350644                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total      3350644                       # number of Writeback hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        65287                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total        65287                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        34260                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total        34260                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       879078                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total       879078                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4680645                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      4680645                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2771065                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total      2771065                       # number of ReadSharedReq hits
+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       220708                       # number of InvalidateReq hits
+system.cpu1.l2cache.InvalidateReq_hits::total       220708                       # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       208719                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       141350                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      4680645                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data      3650143                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total        8680857                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       208719                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker       141350                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      4680645                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data      3650143                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total       8680857                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        10729                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9390                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total        20119                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       125786                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total       125786                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       163059                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total       163059                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data           11                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::total           11                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data       237067                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total       237067                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       529049                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total       529049                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       902850                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total       902850                       # number of ReadSharedReq misses
+system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       257687                       # number of InvalidateReq misses
+system.cpu1.l2cache.InvalidateReq_misses::total       257687                       # number of InvalidateReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        10729                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9390                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst       529049                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data      1139917                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total      1689085                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        10729                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9390                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst       529049                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data      1139917                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total      1689085                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    428489500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    413569000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total    842058500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2736210500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total   2736210500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3427875000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3427875000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2800500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2800500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   9388085997                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total   9388085997                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  15677246500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total  15677246500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  28842829500                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total  28842829500                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  12565083500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::total  12565083500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    428489500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    413569000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst  15677246500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data  38230915497                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total  54750220497                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    428489500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    413569000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst  15677246500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data  38230915497                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total  54750220497                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       219448                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       150740                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total       370188                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks      3350644                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total      3350644                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       191073                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       191073                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       197319                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       197319                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data           11                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total           11                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1116145                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total      1116145                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      5209694                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total      5209694                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3673915                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total      3673915                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       478395                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::total       478395                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       219448                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       150740                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst      5209694                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data      4790060                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total     10369942                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       219448                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       150740                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      5209694                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data      4790060                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total     10369942                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.048891                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.062293                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.054348                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.658314                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.658314                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.826373                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.826373                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.194373                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.194373                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.092349                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.092349                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.244503                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.244503                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.483338                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.483338                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.043047                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.054468                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.092349                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.232685                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.154149                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.043047                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.054468                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.092349                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.232685                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.154149                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 35810.112360                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 39034.655861                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 37286.398627                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21499.306801                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21499.306801                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20746.357147                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20746.357147                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 308799.800000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 308799.800000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 41524.236940                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41524.236940                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 30469.401986                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 30469.401986                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 31731.645204                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 31731.645204                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 50879.422802                       # average InvalidateReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 50879.422802                       # average InvalidateReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 35810.112360                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 39034.655861                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30469.401986                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33660.088551                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 32729.262145                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 35810.112360                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 39034.655861                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30469.401986                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33660.088551                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 32729.262145                       # average overall miss latency
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.212398                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.212398                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.101551                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.101551                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.245746                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.245746                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.538649                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.538649                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.048891                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.062293                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.101551                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.237976                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.162883                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.048891                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.062293                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.101551                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.237976                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.162883                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39937.505825                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 44043.556976                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 41853.894329                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21752.901754                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21752.901754                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 21022.298677                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 21022.298677                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 254590.909091                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 254590.909091                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39600.981988                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39600.981988                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 29632.881831                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 29632.881831                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 31946.424655                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 31946.424655                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 48761.029854                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 48761.029854                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39937.505825                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 44043.556976                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29632.881831                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33538.332613                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 32414.129838                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39937.505825                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 44043.556976                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29632.881831                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33538.332613                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 32414.129838                       # average overall miss latency
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -2156,226 +2147,219 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks       868662                       # number of writebacks
-system.cpu1.l2cache.writebacks::total          868662                       # number of writebacks
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         5194                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total         5194                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          348                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          348                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            2                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::total            2                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data         5542                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total         5542                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data         5542                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         5542                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker         9790                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         8267                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        18057                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.Writeback_mshr_misses::writebacks            1                       # number of Writeback MSHR misses
-system.cpu1.l2cache.Writeback_mshr_misses::total            1                       # number of Writeback MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks        85466                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::total        85466                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       604026                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       604026                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       120456                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       120456                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       156608                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       156608                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            5                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       200917                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total       200917                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       467514                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       467514                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       840168                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       840168                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       229971                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::total       229971                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker         9790                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         8267                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       467514                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1041085                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total      1526656                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker         9790                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         8267                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       467514                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1041085                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       604026                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total      2130682                       # number of overall MSHR misses
+system.cpu1.l2cache.writebacks::writebacks       952252                       # number of writebacks
+system.cpu1.l2cache.writebacks::total          952252                       # number of writebacks
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         3771                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total         3771                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          320                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          320                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data         4091                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total         4091                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data         4091                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total         4091                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        10729                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         9390                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total        20119                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks        95458                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::total        95458                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       646749                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total       646749                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       125786                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total       125786                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       163059                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       163059                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data           11                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total           11                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       233296                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total       233296                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       529049                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       529049                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       902530                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       902530                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       257687                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::total       257687                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        10729                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         9390                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       529049                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1135826                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total      1684994                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        10729                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         9390                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       529049                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1135826                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       646749                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total      2331743                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        11055                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        11165                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        11308                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        11308                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        12503                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        12613                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        13150                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        13150                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        22363                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        22473                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    291841000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    273097500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    564938500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  27533861444                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  27533861444                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2500623000                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2500623000                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2389472000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2389472000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1321999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1321999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   6820721500                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   6820721500                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  11439788000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  11439788000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  21593362000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  21593362000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  10321018000                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  10321018000                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    291841000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    273097500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  11439788000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  28414083500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  40418810000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    291841000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    273097500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  11439788000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  28414083500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  27533861444                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total  67952671444                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8836500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   1823134500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   1831971000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1942414500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1942414500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8836500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   3765549000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   3774385500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.043047                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.054468                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.047618                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000000                       # mshr miss rate for Writeback accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        25653                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        25763                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    364115500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    357229000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    721344500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  24507257017                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  24507257017                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2611582999                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2611582999                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2531997500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2531997500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2434500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2434500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   7622486997                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   7622486997                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  12502952500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  12502952500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  23395380000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  23395380000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  11018961500                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  11018961500                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    364115500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    357229000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  12502952500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  31017866997                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total  44242163997                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    364115500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    357229000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  12502952500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  31017866997                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  24507257017                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total  68749421014                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8914500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   1969997000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   1978911500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   2183909000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   2183909000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8914500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   4153906000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   4162820500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.048891                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.062293                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.054348                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.662461                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.662461                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.841811                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.841811                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.658314                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.658314                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.826373                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.826373                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.189475                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.189475                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.092349                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.092349                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.244402                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.244402                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.483333                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.483333                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.043047                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.054468                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.092349                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.231453                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.153592                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.043047                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.054468                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.092349                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.231453                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.209019                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.209019                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.101551                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.101551                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.245659                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.245659                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.538649                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.538649                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.048891                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.062293                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.101551                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.237121                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.162488                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.048891                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.062293                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.101551                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.237121                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.214361                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 29810.112360                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33034.655861                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 31286.398627                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45583.901097                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45583.901097                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20759.638374                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20759.638374                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15257.662444                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15257.662444                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 264399.800000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 264399.800000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33947.956121                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33947.956121                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 24469.401986                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 24469.401986                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25701.243085                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25701.243085                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 44879.650043                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 44879.650043                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 29810.112360                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33034.655861                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 24469.401986                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27292.760437                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26475.388038                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 29810.112360                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33034.655861                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 24469.401986                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27292.760437                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45583.901097                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31892.451076                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 80331.818182                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164914.925373                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164081.594268                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171773.478953                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 171773.478953                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 80331.818182                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 168382.998703                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 167952.009078                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.224856                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 33937.505825                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38043.556976                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 35853.894329                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37892.995609                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37892.995609                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20762.111833                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20762.111833                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15528.106391                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15528.106391                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 221318.181818                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 221318.181818                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32673.029100                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32673.029100                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 23632.881831                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23632.881831                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25921.997053                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25921.997053                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 42761.029854                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 42761.029854                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 33937.505825                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38043.556976                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23632.881831                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27308.643223                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26256.570645                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 33937.505825                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38043.556976                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23632.881831                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27308.643223                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37892.995609                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29484.133120                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81040.909091                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 157561.945133                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156894.592880                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166076.730038                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166076.730038                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81040.909091                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 161926.714224                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161581.356985                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq        559173                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp      9082723                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        37997                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        11308                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback      6546630                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict      9047745                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq       872762                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp           38                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       399618                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       347237                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       434764                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           64                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           96                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1786739                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1070352                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5062459                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq      5562594                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq       582530                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp       475802                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     15186455                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15778247                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       332058                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       524938                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         31821698                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    323997816                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    497415771                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1214224                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1819400                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total         824447211                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                   10229580                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     30806602                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       1.338828                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.473311                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq        557907                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp      9467454                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        38603                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        13150                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback      6658964                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict      9333240                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq       797552                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       400874                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       357340                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       454404                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           71                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          121                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1816504                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1125838                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5209694                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      5632852                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       585123                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       478395                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     15628224                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16712375                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       332083                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       514043                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         33186725                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    333420856                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    527793939                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1205920                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1755584                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total         864176299                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    9912470                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     31389750                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       1.322129                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.467292                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1          20368466     66.12%     66.12% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2          10438136     33.88%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1          21278201     67.79%     67.79% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2          10111549     32.21%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      30806602                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   13598256460                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      31389750                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   14234291993                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    189037985                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    190598993                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   7593798500                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   7814651000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   7185863072                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   7637949368                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    180280000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    181343000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    297513000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    294595499                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40323                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40323                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40360                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40360                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136623                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136623                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47688                       # Packet count per connected master and slave (bytes)
@@ -2394,11 +2378,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122622                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231190                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231190                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231264                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231264                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353892                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353966                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47708                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2415,11 +2399,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155729                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338776                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7338776                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339072                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7339072                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7496591                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7496887                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy             36209000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
@@ -2448,71 +2432,71 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           569692377                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           569839842                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92730000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147886000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147960000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115590                       # number of replacements
-system.iocache.tags.tagsinuse               11.304878                       # Cycle average of tags in use
+system.iocache.tags.replacements               115629                       # number of replacements
+system.iocache.tags.tagsinuse               11.301329                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115606                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115645                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9148728954000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     7.397645                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     3.907233                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.462353                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.244202                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.706555                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         9148621285000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     7.403816                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     3.897512                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.462739                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.243595                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.706333                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1040712                       # Number of tag accesses
-system.iocache.tags.data_accesses             1040712                       # Number of data accesses
+system.iocache.tags.tag_accesses              1041045                       # Number of tag accesses
+system.iocache.tags.data_accesses             1041045                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8867                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8904                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8904                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8941                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8867                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8907                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8904                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8944                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8867                       # number of overall misses
-system.iocache.overall_misses::total             8907                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8904                       # number of overall misses
+system.iocache.overall_misses::total             8944                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5195000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1652925028                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1658120028                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1656855076                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1662050076                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  12636024349                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  12636024349                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12632251766                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12632251766                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5564000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1652925028                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1658489028                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1656855076                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1662419076                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5564000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1652925028                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1658489028                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1656855076                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1662419076                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8867                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8904                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8904                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8941                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8867                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8907                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8904                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8944                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8867                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8907                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8904                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8944                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2527,54 +2511,54 @@ system.iocache.overall_miss_rate::realview.ethernet            1
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 186413.107928                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 186221.925876                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 186079.860288                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 185890.848451                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118394.651347                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118394.651347                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118359.303707                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118359.303707                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 186413.107928                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 186200.631863                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 186079.860288                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 185869.753578                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 186413.107928                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 186200.631863                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         32852                       # number of cycles access was blocked
+system.iocache.overall_avg_miss_latency::realview.ide 186079.860288                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 185869.753578                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         32671                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3487                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3430                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.421279                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.525073                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks          106693                       # number of writebacks
-system.iocache.writebacks::total               106693                       # number of writebacks
+system.iocache.writebacks::writebacks          106695                       # number of writebacks
+system.iocache.writebacks::total               106695                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8867                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8904                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8904                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8941                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8867                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8907                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8904                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8944                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8867                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8907                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide         8904                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8944                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3345000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1209575028                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1212920028                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1211655076                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1215000076                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7299624349                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   7299624349                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7295851766                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7295851766                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3564000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1209575028                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1213139028                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1211655076                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1215219076                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3564000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1209575028                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1213139028                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1211655076                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1215219076                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -2589,613 +2573,612 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet            1
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136413.107928                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 136221.925876                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136079.860288                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 135890.848451                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68394.651347                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68394.651347                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68359.303707                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68359.303707                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 136413.107928                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 136200.631863                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 136079.860288                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 135869.753578                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 136413.107928                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 136200.631863                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 136079.860288                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 135869.753578                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1309168                       # number of replacements
-system.l2c.tags.tagsinuse                63754.864014                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4916621                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1368931                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     3.591577                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1275038                       # number of replacements
+system.l2c.tags.tagsinuse                63572.316878                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4892898                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1334308                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     3.666993                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   19091.859701                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   105.912894                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   155.127533                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3615.637235                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     7840.243629                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  8325.501182                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   220.931545                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   308.618632                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3602.401841                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     8895.404165                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11593.225658                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.291319                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001616                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.002367                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.055170                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.119633                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.127037                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.003371                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.004709                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.054968                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.135733                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.176899                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.972822                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        11100                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          278                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        48385                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          212                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3          379                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        10509                       # Occupied blocks per task id
+system.l2c.tags.occ_blocks::writebacks   18943.726739                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    66.506889                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker    88.082899                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3576.388780                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     7769.332592                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  6333.160086                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   237.192415                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   333.040502                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3918.032205                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     9111.997525                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13194.856246                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.289058                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001015                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.001344                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.054571                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.118551                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.096636                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.003619                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.005082                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.059784                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.139038                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.201338                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.970037                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        10413                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          223                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        48634                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          260                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3          499                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4         9654                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          277                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           85                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1364                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         4701                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        42219                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.169373                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.004242                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.738297                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 62372649                       # Number of tag accesses
-system.l2c.tags.data_accesses                62372649                       # Number of data accesses
-system.l2c.Writeback_hits::writebacks         2239360                       # number of Writeback hits
-system.l2c.Writeback_hits::total              2239360                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data           30980                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data           24512                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               55492                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          6081                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          5027                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             11108                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           167543                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           144880                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               312423                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         5175                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4181                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst       498211                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       558223                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       295485                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         4952                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4009                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst       423075                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       457635                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       236791                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          2487737                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          5175                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          4181                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              498211                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              725766                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       295485                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          4952                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          4009                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              423075                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              602515                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher       236791                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2800160                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         5175                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         4181                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             498211                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             725766                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       295485                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         4952                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         4009                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             423075                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             602515                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       236791                       # number of overall hits
-system.l2c.overall_hits::total                2800160                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data         43560                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         41893                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             85453                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data        11005                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         9001                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           20006                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         491114                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data         139826                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             630940                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1207                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1226                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        43736                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       119131                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       198612                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1716                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1777                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst        44439                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data       101598                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       196208                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         709650                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         1207                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         1226                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             43736                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            610245                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       198612                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         1716                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         1777                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             44439                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            241424                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       196208                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1340590                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         1207                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         1226                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            43736                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           610245                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       198612                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         1716                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         1777                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            44439                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           241424                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       196208                       # number of overall misses
-system.l2c.overall_misses::total              1340590                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data    242100000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    225831000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    467931000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data     53618000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data     45210000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total     98828000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  41035187500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data  11309941500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  52345129000                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    108698500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    110530000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   3653235500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  10597934000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  23810682130                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    150819000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    156924500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst   3723508500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data   8959752500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  23335976587                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  74608061217                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    108698500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    110530000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   3653235500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  51633121500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  23810682130                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    150819000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    156924500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   3723508500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  20269694000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  23335976587                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    126953190217                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    108698500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    110530000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   3653235500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  51633121500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  23810682130                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    150819000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    156924500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   3723508500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  20269694000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  23335976587                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   126953190217                       # number of overall miss cycles
-system.l2c.Writeback_accesses::writebacks      2239360                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          2239360                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        74540                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        66405                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          140945                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        17086                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        14028                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         31114                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       658657                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       284706                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           943363                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         6382                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         5407                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst       541947                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       677354                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       494097                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         6668                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         5786                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst       467514                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       559233                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       432999                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      3197387                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         6382                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         5407                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          541947                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1336011                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       494097                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         6668                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         5786                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          467514                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          843939                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       432999                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             4140750                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         6382                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         5407                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         541947                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1336011                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       494097                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         6668                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         5786                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         467514                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         843939                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       432999                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            4140750                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.584384                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.630871                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.606286                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.644095                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.641645                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.642990                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.745629                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.491124                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.668820                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.189126                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.226743                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.080702                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.175877                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.401970                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.257349                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.307121                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.095054                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.181674                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.453137                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.221947                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.189126                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.226743                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.080702                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.456766                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.401970                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.257349                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.307121                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.095054                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.286068                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.453137                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.323755                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.189126                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.226743                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.080702                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.456766                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.401970                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.257349                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.307121                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.095054                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.286068                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.453137                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.323755                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  5557.851240                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5390.661924                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  5475.887330                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  4872.149023                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5022.775247                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  4939.918025                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83555.320150                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80885.825955                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 82963.719213                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 90056.752278                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90154.975530                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83529.255076                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88960.337779                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119885.415433                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 87889.860140                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 88308.666292                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 83789.205428                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 88188.276344                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 118934.888419                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 105133.602786                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90056.752278                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90154.975530                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 83529.255076                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 84610.478578                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119885.415433                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87889.860140                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88308.666292                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 83789.205428                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 83958.902180                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 118934.888419                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 94699.490685                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90056.752278                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90154.975530                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 83529.255076                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 84610.478578                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119885.415433                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87889.860140                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88308.666292                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 83789.205428                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 83958.902180                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 118934.888419                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 94699.490685                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                67                       # number of cycles access was blocked
+system.l2c.tags.age_task_id_blocks_1023::4          222                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1           99                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         1442                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5047                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        42029                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.158890                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003403                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.742096                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 61952788                       # Number of tag accesses
+system.l2c.tags.data_accesses                61952788                       # Number of data accesses
+system.l2c.Writeback_hits::writebacks         2200570                       # number of Writeback hits
+system.l2c.Writeback_hits::total              2200570                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data           25702                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data           29550                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               55252                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data          5421                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data          6216                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total             11637                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           145994                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data           170556                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               316550                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         4694                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker         3455                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst       439478                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       496055                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       255928                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         5679                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4922                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst       484783                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       520043                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       283587                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          2498624                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          4694                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          3455                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              439478                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              642049                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher       255928                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          5679                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          4922                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              484783                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              690599                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher       283587                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2815174                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         4694                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         3455                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             439478                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             642049                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher       255928                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         5679                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         4922                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             484783                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             690599                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher       283587                       # number of overall hits
+system.l2c.overall_hits::total                2815174                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data         41366                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data         45574                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             86940                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data         9742                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data        11031                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total           20773                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         487808                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data         146598                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             634406                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker          811                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.itb.walker          757                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.inst        42366                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       114531                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       184040                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         2399                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.itb.walker         2560                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.inst        44266                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data       108963                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       176139                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         676832                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.dtb.walker          811                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker          757                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             42366                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            602339                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.l2cache.prefetcher       184040                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker         2399                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker         2560                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst             44266                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data            255561                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.l2cache.prefetcher       176139                       # number of demand (read+write) misses
+system.l2c.demand_misses::total               1311238                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker          811                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker          757                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            42366                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           602339                       # number of overall misses
+system.l2c.overall_misses::cpu0.l2cache.prefetcher       184040                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker         2399                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker         2560                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst            44266                       # number of overall misses
+system.l2c.overall_misses::cpu1.data           255561                       # number of overall misses
+system.l2c.overall_misses::cpu1.l2cache.prefetcher       176139                       # number of overall misses
+system.l2c.overall_misses::total              1311238                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data    225555000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data    234735000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    460290000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data     48941500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data     54202000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total    103143500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data  40891325500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data  11909713000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  52801038500                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker     72944500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker     67955000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.inst   3540995500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data  10155548500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  21472556269                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    211977500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    227366000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst   3707983000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data   9711131500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  19710657061                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  68879114830                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker     72944500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker     67955000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   3540995500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  51046874000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  21472556269                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker    211977500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker    227366000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst   3707983000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data  21620844500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  19710657061                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total    121680153330                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker     72944500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker     67955000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   3540995500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  51046874000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  21472556269                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker    211977500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker    227366000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst   3707983000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data  21620844500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  19710657061                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total   121680153330                       # number of overall miss cycles
+system.l2c.Writeback_accesses::writebacks      2200570                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          2200570                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        67068                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data        75124                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          142192                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data        15163                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data        17247                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total         32410                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       633802                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       317154                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           950956                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         5505                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         4212                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst       481844                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       610586                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       439968                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         8078                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         7482                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst       529049                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       629006                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       459726                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      3175456                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         5505                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         4212                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          481844                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1244388                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       439968                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         8078                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         7482                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          529049                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          946160                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher       459726                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             4126412                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         5505                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         4212                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         481844                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1244388                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       439968                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         8078                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         7482                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         529049                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         946160                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher       459726                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            4126412                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.616777                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.606650                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.611427                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.642485                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.639589                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.640944                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.769654                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.462230                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.667124                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.147321                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.179725                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.087925                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.187576                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.418303                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.296979                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.342155                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.083671                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.173230                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.383139                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.213145                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.147321                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.179725                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.087925                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.484044                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.418303                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.296979                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.342155                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.083671                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.270103                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.383139                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.317767                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.147321                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.179725                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.087925                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.484044                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.418303                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.296979                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.342155                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.083671                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.270103                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.383139                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.317767                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  5452.666441                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5150.634133                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  5294.340925                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5023.763088                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  4913.607107                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  4965.267414                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83826.680784                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81240.624019                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 83229.096982                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 89943.896424                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89768.824306                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83581.067365                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88670.739800                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 116673.311612                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 88360.775323                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 88814.843750                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 83765.937740                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89123.202371                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 111903.990945                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 101766.930095                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 89943.896424                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89768.824306                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 83581.067365                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 84747.748361                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 116673.311612                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88360.775323                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88814.843750                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 83765.937740                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 84601.502185                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 111903.990945                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 92797.915657                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 89943.896424                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89768.824306                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 83581.067365                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 84747.748361                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 116673.311612                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88360.775323                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88814.843750                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 83765.937740                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 84601.502185                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 111903.990945                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 92797.915657                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        1                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs            67                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1031074                       # number of writebacks
-system.l2c.writebacks::total                  1031074                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          126                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data           17                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          108                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data           18                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total          269                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst            126                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             17                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst            108                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             18                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                269                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst           126                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            17                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst           108                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            18                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               269                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks        39567                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total        39567                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        43560                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        41893                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        85453                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        11005                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         9001                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total        20006                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       491114                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data       139826                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        630940                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1207                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1226                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        43610                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       119114                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       198612                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         1716                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1777                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        44331                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data       101580                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       196208                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       709381                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         1207                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         1226                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        43610                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       610228                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       198612                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         1716                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker         1777                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        44331                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data       241406                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       196208                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total          1340321                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         1207                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         1226                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        43610                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       610228                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       198612                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker         1716                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker         1777                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst        44331                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data       241406                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       196208                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total         1340321                       # number of overall MSHR misses
+system.l2c.writebacks::writebacks             1000989                       # number of writebacks
+system.l2c.writebacks::total                  1000989                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst           84                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu0.data           16                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          106                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.data           84                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total          290                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst             84                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data             16                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst            106                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data             84                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                290                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst            84                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data            16                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst           106                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.data            84                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total               290                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks        40865                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total        40865                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data        41366                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data        45574                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        86940                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data         9742                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        11031                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total        20773                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data       487808                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data       146598                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        634406                       # number of ReadExReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker          811                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker          757                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        42282                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data       114515                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       184040                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         2399                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         2560                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        44160                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data       108879                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       176139                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total       676542                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker          811                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker          757                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        42282                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       602323                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       184040                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker         2399                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker         2560                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst        44160                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data       255477                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       176139                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total          1310948                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker          811                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker          757                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        42282                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       602323                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       184040                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker         2399                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker         2560                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst        44160                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data       255477                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       176139                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total         1310948                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        27090                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data        26231                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data        11053                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        81378                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        26689                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data        11308                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        37997                       # number of WriteReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data        12501                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        81967                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        25453                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data        13150                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        38603                       # number of WriteReq MSHR uncacheable
 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        53779                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        51684                       # number of overall MSHR uncacheable misses
 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        22361                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total       119375                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    904276500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    870415500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total   1774692000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    228388000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    186718499                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total    415106499                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  36124047500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   9911681500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  46035729000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker     96628500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker     98270000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   3207900500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   9405362000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  21824562130                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    133659000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    139154500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   3272125000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   7942788500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  21373896587                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  67494346717                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker     96628500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker     98270000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   3207900500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  45529409500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  21824562130                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    133659000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    139154500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst   3272125000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data  17854470000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  21373896587                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 113530075717                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker     96628500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker     98270000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   3207900500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  45529409500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  21824562130                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    133659000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    139154500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst   3272125000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data  17854470000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  21373896587                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 113530075717                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        25651                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total       120570                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    858580500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    946408001                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total   1804988501                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    202067500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    228990999                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total    431058499                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  36013245500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  10443733000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  46456978500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker     64834500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker     60385000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   3112031500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   9009218000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  19632156269                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    187987500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    201766000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   3258945500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   8616011500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  17949267061                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  62092602830                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker     64834500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker     60385000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   3112031500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  45022463500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  19632156269                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    187987500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    201766000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst   3258945500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data  19059744500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  17949267061                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 108549581330                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker     64834500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker     60385000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   3112031500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  45022463500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  19632156269                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    187987500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    201766000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst   3258945500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data  19059744500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  17949267061                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 108549581330                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   2678027000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3881489500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6856500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1624141500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   8190514500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   3646235000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1750167000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5396402000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3773796500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6934000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1744943000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   8203700500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   3449741500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1960350500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   5410092000                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   2678027000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   7527724500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6856500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3374308500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  13586916500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   7223538000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6934000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3705293500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  13613792500                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.584384                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.630871                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.606286                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.644095                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.641645                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.642990                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.745629                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.491124                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.668820                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.189126                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.226743                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.080469                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.175852                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.401970                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.257349                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.307121                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.094823                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.181642                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.453137                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.221863                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.189126                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.226743                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.080469                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.456754                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.401970                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.257349                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.307121                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.094823                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.286047                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.453137                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.323690                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.189126                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.226743                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.080469                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.456754                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.401970                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.257349                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.307121                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.094823                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.286047                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.453137                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.323690                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20759.331956                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20777.110734                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20768.047933                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20753.112222                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20744.194978                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20749.100220                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73555.320150                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70885.825955                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 72963.719213                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80056.752278                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80154.975530                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73558.828250                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78961.012140                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109885.415433                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 77889.860140                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78308.666292                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73811.215628                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78192.444379                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108934.888419                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 95145.410882                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80056.752278                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80154.975530                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73558.828250                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74610.489030                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109885.415433                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77889.860140                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78308.666292                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73811.215628                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73960.340671                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108934.888419                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 84703.646154                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80056.752278                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80154.975530                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73558.828250                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74610.489030                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109885.415433                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77889.860140                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78308.666292                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73811.215628                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73960.340671                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108934.888419                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 84703.646154                       # average overall mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.616777                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.606650                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.611427                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.642485                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.639589                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.640944                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.769654                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.462230                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.667124                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.147321                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.179725                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.087750                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.187549                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.418303                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.296979                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.342155                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.083471                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.173097                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.383139                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.213053                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.147321                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.179725                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.087750                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.484032                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.418303                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.296979                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.342155                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.083471                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.270015                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.383139                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.317697                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.147321                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.179725                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.087750                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.484032                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.418303                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.296979                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.342155                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.083471                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.270015                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.383139                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.317697                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20755.705168                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20766.401918                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20761.312411                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20741.890782                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20758.861300                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20750.902566                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73826.680784                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71240.624019                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 73229.096982                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 79943.896424                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79768.824306                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73601.804550                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78672.820155                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106673.311612                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 78360.775323                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78814.843750                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73798.584692                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79133.822868                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101903.990945                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 91779.376343                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79943.896424                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79768.824306                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73601.804550                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74748.039673                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106673.311612                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78360.775323                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78814.843750                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73798.584692                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74604.541700                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101903.990945                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 82802.354731                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79943.896424                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79768.824306                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73601.804550                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74748.039673                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106673.311612                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78360.775323                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78814.843750                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73798.584692                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74604.541700                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101903.990945                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 82802.354731                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62099.176812                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 143281.266150                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62331.818182                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146941.237673                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 100647.773354                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 136619.393758                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154772.461974                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142021.791194                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 143867.809081                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63036.363636                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 139584.273258                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 100085.406322                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 135533.787766                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149076.083650                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 140146.931586                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62099.176812                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 139975.166887                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62331.818182                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 150901.502616                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 113817.101571                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 139763.524495                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63036.363636                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 144450.255351                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 112911.939123                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               81378                       # Transaction distribution
-system.membus.trans_dist::ReadResp             799663                       # Transaction distribution
-system.membus.trans_dist::WriteReq              37997                       # Transaction distribution
-system.membus.trans_dist::WriteResp             37997                       # Transaction distribution
-system.membus.trans_dist::Writeback           1137767                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           200903                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           374437                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         306668                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          111797                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            646745                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           624605                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        718285                       # Transaction distribution
+system.membus.trans_dist::ReadReq               81967                       # Transaction distribution
+system.membus.trans_dist::ReadResp             767450                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38603                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38603                       # Transaction distribution
+system.membus.trans_dist::Writeback           1107684                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           202348                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           391044                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         311393                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          114065                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            650749                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           628057                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        685483                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106728                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106728                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122622                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        24438                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4799197                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4946349                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342551                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       342551                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5288900                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        26828                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4735959                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4885501                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342529                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       342529                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5228030                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155729                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        48876                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    151511532                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    151716341                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7266432                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7266432                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               158982773                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           594252                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3613210                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        53656                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    147705452                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    147915041                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7264128                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7264128                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               155179169                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           613936                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3578377                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3613210    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3578377    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3613210                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           101221000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3578377                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           101272500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               54500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               55000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            21240500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            23177500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          7773596350                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          7575699049                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         7468178118                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         7326536131                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          229090524                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          229377455                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -3239,46 +3222,46 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq              81380                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           4075375                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             37997                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            37997                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          3377178                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         1228761                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          423594                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        317776                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         741370                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           96                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           96                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          1071890                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         1071890                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      4001246                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq              81969                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           4074898                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38603                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38603                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          3308322                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1226405                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          439947                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        323030                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         762977                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          121                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          121                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          1086983                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         1086983                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      4000171                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq       106728                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      7774731                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5765311                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              13540042                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    240674354                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    168156931                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              408831285                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         3034988                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         11680683                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.131880                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.338360                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      7169000                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6360157                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              13529157                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    219530790                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    185908027                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              405438817                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         3048406                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         11669556                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.129089                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.335298                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1               10140239     86.81%     86.81% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                1540444     13.19%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1               10163148     87.09%     87.09% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                1506408     12.91%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           11680683                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         7606203373                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           11669556                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         7690985653                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2481000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2550000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4538781481                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4244781764                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        3532073491                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        3859650249                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
index 37d15d84bd4c169af6b60296b6f6369ef842ce2d..6f66b7dfaf04584774503f3026b6e3480170b170 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.058174                       # Number of seconds simulated
-sim_ticks                                 58174017500                       # Number of ticks simulated
-final_tick                                58174017500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.058182                       # Number of seconds simulated
+sim_ticks                                 58182114500                       # Number of ticks simulated
+final_tick                                58182114500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 129950                       # Simulator instruction rate (inst/s)
-host_op_rate                                   130597                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               83449704                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 446256                       # Number of bytes of host memory used
-host_seconds                                   697.11                       # Real time elapsed on the host
+host_inst_rate                                 128679                       # Simulator instruction rate (inst/s)
+host_op_rate                                   129320                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               82645168                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 446228                       # Number of bytes of host memory used
+host_seconds                                   704.00                       # Real time elapsed on the host
 sim_insts                                    90589799                       # Number of instructions simulated
 sim_ops                                      91041030                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             44480                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             49984                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher       930560                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1025024                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        44480                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           44480                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks        26560                       # Number of bytes written to this memory
-system.physmem.bytes_written::total             26560                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                695                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                781                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher        14540                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 16016                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks             415                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                  415                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               764603                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               859215                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     15996145                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                17619962                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          764603                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             764603                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            456561                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 456561                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            456561                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              764603                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              859215                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     15996145                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18076524                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         16016                       # Number of read requests accepted
-system.physmem.writeReqs                          415                       # Number of write requests accepted
-system.physmem.readBursts                       16016                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                        415                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  1011776                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     13248                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                     25088                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   1025024                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                  26560                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      207                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       5                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bytes_read::cpu.inst             44288                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             51456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher       933184                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1028928                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        44288                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           44288                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks        27456                       # Number of bytes written to this memory
+system.physmem.bytes_written::total             27456                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                692                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                804                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher        14581                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 16077                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks             429                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  429                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               761196                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               884395                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     16039018                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                17684610                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          761196                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             761196                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            471898                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 471898                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            471898                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              761196                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              884395                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     16039018                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               18156508                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         16077                       # Number of read requests accepted
+system.physmem.writeReqs                          429                       # Number of write requests accepted
+system.physmem.readBursts                       16077                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                        429                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  1014080                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     14848                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                     26048                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   1028928                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                  27456                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      232                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       4                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                1014                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                1011                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 876                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 957                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                1028                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                1065                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                1144                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                1126                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                1093                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                1040                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                1029                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                1060                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                1137                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                1146                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                1099                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                1049                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 962                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                938                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                903                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                912                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                940                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                901                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                907                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                888                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                938                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                925                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                  43                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                960                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                923                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                  29                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                   7                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                   6                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                  10                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                  44                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                  74                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                  25                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                  45                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                   8                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                   7                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                   4                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                  30                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                 102                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                  27                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                  34                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::10                 10                       # Per bank write bursts
+system.physmem.perBankWrBursts::10                 11                       # Per bank write bursts
 system.physmem.perBankWrBursts::11                  5                       # Per bank write bursts
-system.physmem.perBankWrBursts::12                 11                       # Per bank write bursts
-system.physmem.perBankWrBursts::13                 32                       # Per bank write bursts
-system.physmem.perBankWrBursts::14                 48                       # Per bank write bursts
-system.physmem.perBankWrBursts::15                 32                       # Per bank write bursts
+system.physmem.perBankWrBursts::12                  6                       # Per bank write bursts
+system.physmem.perBankWrBursts::13                 38                       # Per bank write bursts
+system.physmem.perBankWrBursts::14                 82                       # Per bank write bursts
+system.physmem.perBankWrBursts::15                 24                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     58173860500                       # Total gap between requests
+system.physmem.totGap                     58181957500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   16016                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   16077                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                    415                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     10954                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2453                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       522                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       347                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       301                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       287                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       308                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       284                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       291                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                    429                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     10965                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2513                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       454                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       396                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       298                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       294                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       297                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       275                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       295                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                        58                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
@@ -148,24 +148,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                       24                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                       24                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                       23                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -197,92 +197,93 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1930                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      536.107772                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     304.077638                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     432.159932                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            590     30.57%     30.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          221     11.45%     42.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           97      5.03%     47.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           69      3.58%     50.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           71      3.68%     54.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           49      2.54%     56.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           51      2.64%     59.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           42      2.18%     61.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          740     38.34%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1930                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples            22                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean       717.636364                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       31.597036                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     3209.686449                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511              21     95.45%     95.45% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14848-15359            1      4.55%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total              22                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples            22                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.818182                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.808292                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.588490                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16                  2      9.09%      9.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                 20     90.91%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total              22                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      169690298                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 466109048                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     79045000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10733.78                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1937                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      535.822406                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     300.454496                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     434.844935                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            623     32.16%     32.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          199     10.27%     42.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           99      5.11%     47.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           70      3.61%     51.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           49      2.53%     53.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           51      2.63%     56.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           51      2.63%     58.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           47      2.43%     61.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          748     38.62%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1937                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples            23                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean       687.695652                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       31.373989                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     3139.186163                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511              22     95.65%     95.65% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14848-15359            1      4.35%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total              23                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples            23                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.695652                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.676543                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.822125                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16                  4     17.39%     17.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                 18     78.26%     95.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  1      4.35%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total              23                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      162696744                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 459790494                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     79225000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10268.02                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29483.78                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          17.39                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.43                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       17.62                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.46                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29018.02                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          17.43                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.45                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       17.68                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.47                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.14                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.31                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        17.30                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      14150                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                       110                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.51                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  26.83                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3540494.22                       # Average gap between requests
-system.physmem.pageHitRate                      87.92                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    7832160                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    4273500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  64506000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                  1289520                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3799451760                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2476215945                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            32730681000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              39084249885                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              671.881619                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    54439969881                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1942460000                       # Time in different power states
+system.physmem.avgRdQLen                         1.47                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        18.75                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      14165                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                       138                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.40                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  32.47                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3524897.46                       # Average gap between requests
+system.physmem.pageHitRate                      87.91                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    7749000                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    4228125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  64591800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                  1302480                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             3799960320                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2489657400                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            32723562000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              39091051125                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              671.908601                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    54427806081                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1942720000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1788917619                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1808607669                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    6667920                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    3638250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  58507800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                  1146960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3799451760                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2448182205                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            32755263750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              39072858645                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.685955                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    54482617084                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1942460000                       # Time in different power states
+system.physmem_1.actEnergy                    6811560                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    3716625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  58687200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                  1211760                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             3799960320                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             2472306885                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            32738773500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              39081467850                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.744040                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    54453180249                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1942720000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1747288416                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1783438751                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                28257086                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          23279263                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            837830                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             11842064                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                11784394                       # Number of BTB hits
+system.cpu.branchPred.lookups                28257673                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          23279792                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            837861                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             11842586                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                11784928                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.513007                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                   75760                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             99.513130                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                   75759                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 88                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -402,93 +403,93 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                        116348036                       # number of cpu cycles simulated
+system.cpu.numCycles                        116364230                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles             748817                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      134985012                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    28257086                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           11860154                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     114705506                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1679063                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 1007                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles          831                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  32301197                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   575                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          116295692                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.165959                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.319053                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles             748840                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      134987137                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    28257673                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           11860687                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     114722877                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1679131                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  949                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.IcacheWaitRetryStallCycles          833                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  32301983                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   576                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          116313064                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.165803                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.319035                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 58725363     50.50%     50.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 13942075     11.99%     62.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  9230802      7.94%     70.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 34397452     29.58%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 58742008     50.50%     50.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 13941997     11.99%     62.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  9231022      7.94%     70.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 34398037     29.57%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            116295692                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.242867                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.160183                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                  8839821                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              64036145                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  33034290                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               9558144                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 827292                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              4101248                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 12341                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              114428571                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               1996975                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 827292                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 15280810                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                49891272                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         109349                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  35424705                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              14762264                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              110897410                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               1415598                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents              11131669                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1144033                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1526935                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                 476507                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           129954934                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             483266147                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        119472382                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               420                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            116313064                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.242838                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.160040                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                  8839881                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              64052748                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  33035096                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9558012                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 827327                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              4101304                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 12342                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              114430189                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               1996961                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 827327                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 15280915                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                49896712                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         109420                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  35425336                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              14773354                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              110898724                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               1415582                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              11131047                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1144428                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1527040                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                 487812                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           129956476                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             483272365                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        119474128                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               430                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             107312919                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 22642015                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                 22643557                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts               4363                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts           4358                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  21506426                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26812625                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             5349337                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads            517439                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           253975                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  109689181                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts                  21506605                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26812984                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             5349507                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads            517744                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           254125                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  109690412                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                8247                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 101387653                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1074699                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        18656398                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     41685630                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                 101387626                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1074735                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        18657629                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     41690294                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             29                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     116295692                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.871809                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.989320                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples     116313064                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.871679                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.989298                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            54655211     47.00%     47.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            31361654     26.97%     73.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            22008607     18.92%     92.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7072409      6.08%     98.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             1197497      1.03%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 314      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            54672209     47.00%     47.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            31362113     26.96%     73.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            22008866     18.92%     92.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7072036      6.08%     98.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             1197527      1.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 313      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       116295692                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       116313064                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 9793566     48.69%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 9793385     48.69%     48.69% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                     50      0.00%     48.69% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     48.69% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     48.69% # attempts to use FU when none available
@@ -511,18 +512,18 @@ system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     48.69% # at
 system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     48.69% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     48.69% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                13      0.00%     48.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                14      0.00%     48.69% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     48.69% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     48.69% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     48.69% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     48.69% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                9616917     47.81%     96.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                703878      3.50%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                9616432     47.81%     96.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                703828      3.50%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              71983899     71.00%     71.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              71984128     71.00%     71.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                10709      0.01%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     71.01% # Type of FU issued
@@ -547,88 +548,88 @@ system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     71.01% # Ty
 system.cpu.iq.FU_type_0::SimdFloatCmp               2      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt              53      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     71.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc            124      0.00%     71.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc            123      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     71.01% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             24343332     24.01%     95.02% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             5049532      4.98%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             24343025     24.01%     95.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             5049584      4.98%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              101387653                       # Type of FU issued
-system.cpu.iq.rate                           0.871417                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    20114424                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.198391                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          340259668                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         128354519                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     99625011                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total              101387626                       # Type of FU issued
+system.cpu.iq.rate                           0.871295                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    20113709                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.198384                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          340276307                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         128356979                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     99625202                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                 453                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                612                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          114                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              121501841                       # Number of integer alu accesses
+system.cpu.iq.fp_inst_queue_writes                618                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          112                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              121501099                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                     236                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           290489                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads           290480                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      4336714                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads      4337073                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses         1516                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation         1340                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       604493                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         1343                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       604663                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         7566                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        130818                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         7562                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        130598                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 827292                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 8117300                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                684188                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           109710095                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                 827327                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 8118752                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                684481                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           109711326                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26812625                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              5349337                       # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts              26812984                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              5349507                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts               4359                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 178987                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                342189                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents           1340                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         436578                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       412874                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               849452                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             100126762                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              23806670                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1260891                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewIQFullEvents                 179113                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                342349                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           1343                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         436660                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       412872                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               849532                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             100126680                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              23806374                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1260946                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                         12667                       # number of nop insts executed
-system.cpu.iew.exec_refs                     28724538                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 20624131                       # Number of branches executed
-system.cpu.iew.exec_stores                    4917868                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.860580                       # Inst execution rate
-system.cpu.iew.wb_sent                       99709725                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      99625125                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  59703453                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95545682                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     28724279                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 20624229                       # Number of branches executed
+system.cpu.iew.exec_stores                    4917905                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.860459                       # Inst execution rate
+system.cpu.iew.wb_sent                       99709898                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      99625314                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  59703303                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95544285                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.856268                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.624868                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.856151                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.624876                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        17384546                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        17385621                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            8218                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            825591                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    113603530                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.801504                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.738080                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            825623                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    113620717                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.801382                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.737978                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     77180399     67.94%     67.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     18615023     16.39%     84.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      7150693      6.29%     90.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      3466326      3.05%     93.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1641860      1.45%     95.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       544762      0.48%     95.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       704352      0.62%     96.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       180030      0.16%     96.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      4120085      3.63%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     77197638     67.94%     67.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     18614899     16.38%     84.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      7150727      6.29%     90.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      3466583      3.05%     93.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1641577      1.44%     95.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       544810      0.48%     95.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       704355      0.62%     96.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       179975      0.16%     96.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      4120153      3.63%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    113603530                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    113620717                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             90602408                       # Number of instructions committed
 system.cpu.commit.committedOps               91053639                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -674,78 +675,78 @@ system.cpu.commit.op_class_0::MemWrite        4744844      5.21%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          91053639                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               4120085                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    217915896                       # The number of ROB reads
-system.cpu.rob.rob_writes                   219569120                       # The number of ROB writes
-system.cpu.timesIdled                             587                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           52344                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               4120153                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    217934090                       # The number of ROB reads
+system.cpu.rob.rob_writes                   219571457                       # The number of ROB writes
+system.cpu.timesIdled                             581                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           51166                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    90589799                       # Number of Instructions Simulated
 system.cpu.committedOps                      91041030                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.284339                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.284339                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.778610                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.778610                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                108111439                       # number of integer regfile reads
-system.cpu.int_regfile_writes                58700930                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        59                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       95                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 369063438                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 58693153                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                28414947                       # number of misc regfile reads
+system.cpu.cpi                               1.284518                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.284518                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.778502                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.778502                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                108111423                       # number of integer regfile reads
+system.cpu.int_regfile_writes                58700979                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        58                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       92                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 369063033                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 58693305                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                28414934                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                   7784                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           5470195                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.789215                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            18252015                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           5470707                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              3.336317                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          35049500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.789215                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999588                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999588                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           5470204                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.787652                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            18251843                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           5470716                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              3.336280                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          35373500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.787652                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999585                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999585                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          343                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          169                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          357                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          155                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          61908703                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         61908703                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     13889937                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13889937                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4353797                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4353797                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          61908596                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         61908596                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     13889769                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13889769                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4353793                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4353793                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          522                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total           522                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data         3872                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total         3872                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      18243734                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         18243734                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     18244256                       # number of overall hits
-system.cpu.dcache.overall_hits::total        18244256                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      9585777                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       9585777                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       381184                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       381184                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      18243562                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         18243562                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     18244084                       # number of overall hits
+system.cpu.dcache.overall_hits::total        18244084                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      9585887                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       9585887                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       381188                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       381188                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            7                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            7                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data           15                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total           15                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      9966961                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9966961                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9966968                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9966968                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  88717689000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  88717689000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   3954782792                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   3954782792                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data      9967075                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9967075                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9967082                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9967082                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  88721516500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  88721516500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   4007000296                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   4007000296                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       296500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       296500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  92672471792                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  92672471792                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  92672471792                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  92672471792                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23475714                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23475714                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data  92728516796                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  92728516796                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  92728516796                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  92728516796                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23475656                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23475656                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data          529                       # number of SoftPFReq accesses(hits+misses)
@@ -754,298 +755,298 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887
 system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     28210695                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     28210695                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     28211224                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     28211224                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.408327                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.408327                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080504                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.080504                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     28210637                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     28210637                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     28211166                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     28211166                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.408333                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.408333                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080505                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.080505                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.013233                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.013233                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.003859                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.003859                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.353304                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.353304                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.353298                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.353298                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9255.138003                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  9255.138003                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10374.996831                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 10374.996831                       # average WriteReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.353309                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.353309                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.353303                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.353303                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9255.431083                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total  9255.431083                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10511.874183                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 10511.874183                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19766.666667                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19766.666667                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  9297.966731                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total  9297.966731                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  9297.960201                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total  9297.960201                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       330068                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        99317                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            121445                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           12837                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     2.717839                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     7.736777                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data  9303.483399                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total  9303.483399                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data  9303.476865                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total  9303.476865                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       329940                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       111027                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            121461                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           12838                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     2.716427                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     8.648310                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      5436552                       # number of writebacks
-system.cpu.dcache.writebacks::total           5436552                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4337556                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4337556                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       158702                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       158702                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      5432438                       # number of writebacks
+system.cpu.dcache.writebacks::total           5432438                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4337660                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      4337660                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       158703                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       158703                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           15                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total           15                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      4496258                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      4496258                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      4496258                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      4496258                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5248221                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5248221                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       222482                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       222482                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      4496363                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      4496363                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      4496363                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      4496363                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5248227                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5248227                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       222485                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       222485                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            4                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            4                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      5470703                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      5470703                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      5470707                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      5470707                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43246268500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  43246268500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2278267197                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2278267197                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      5470712                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      5470712                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      5470716                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      5470716                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43248007500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  43248007500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2284927222                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2284927222                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       214500                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       214500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  45524535697                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  45524535697                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  45524750197                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  45524750197                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  45532934722                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  45532934722                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  45533149222                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  45533149222                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.223560                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.223560                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046987                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046987                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046988                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046988                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.007561                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.007561                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.193923                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.193923                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.193924                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.193924                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.193920                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.193920                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8240.176719                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8240.176719                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10240.231556                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10240.231556                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8240.498648                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8240.498648                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10270.028191                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10270.028191                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53625                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53625                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8321.514748                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  8321.514748                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8321.547873                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  8321.547873                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8323.036329                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  8323.036329                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8323.069452                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  8323.069452                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements               451                       # number of replacements
-system.cpu.icache.tags.tagsinuse           428.509106                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            32300030                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           428.507566                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            32300812                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               910                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          35494.538462                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          35495.397802                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   428.509106                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.836932                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.836932                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   428.507566                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.836929                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.836929                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          459                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3           22                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          331                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.896484                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          64603278                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         64603278                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     32300030                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        32300030                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      32300030                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         32300030                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     32300030                       # number of overall hits
-system.cpu.icache.overall_hits::total        32300030                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1154                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1154                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1154                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1154                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1154                       # number of overall misses
-system.cpu.icache.overall_misses::total          1154                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     61388483                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     61388483                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     61388483                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     61388483                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     61388483                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     61388483                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     32301184                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     32301184                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     32301184                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     32301184                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     32301184                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     32301184                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses          64604850                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         64604850                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     32300812                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        32300812                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      32300812                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         32300812                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     32300812                       # number of overall hits
+system.cpu.icache.overall_hits::total        32300812                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1158                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1158                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1158                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1158                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1158                       # number of overall misses
+system.cpu.icache.overall_misses::total          1158                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     61588984                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     61588984                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     61588984                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     61588984                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     61588984                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     61588984                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     32301970                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     32301970                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     32301970                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     32301970                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     32301970                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     32301970                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000036                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000036                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000036                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000036                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000036                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000036                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53196.259099                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 53196.259099                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 53196.259099                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 53196.259099                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 53196.259099                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 53196.259099                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        19635                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          107                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               227                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53185.651123                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 53185.651123                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 53185.651123                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 53185.651123                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 53185.651123                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 53185.651123                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        19024                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          135                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               225                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    86.497797                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    21.400000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    84.551111                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets           27                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          244                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          244                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          244                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          244                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          244                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          244                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          248                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          248                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          248                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          248                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          248                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          248                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          910                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          910                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          910                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          910                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          910                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          910                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     50524487                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     50524487                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     50524487                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     50524487                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     50524487                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     50524487                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     49864488                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     49864488                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     49864488                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     49864488                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     49864488                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     49864488                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000028                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000028                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000028                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55521.414286                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55521.414286                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55521.414286                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 55521.414286                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55521.414286                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 55521.414286                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54796.140659                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54796.140659                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54796.140659                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54796.140659                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54796.140659                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54796.140659                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued      4525641                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified      5296015                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit       665258                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued      4982376                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified      5297288                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit       273784                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage     14074393                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements              580                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        12072.245633                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           10689052                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            16020                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           667.231710                       # Average number of references to valid blocks.
+system.cpu.l2cache.prefetcher.pfSpanPage     14074296                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements              642                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        12072.124687                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           10689018                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            16082                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           664.657257                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 11065.307975                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   570.003280                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   229.604220                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   207.330158                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.675373                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.034790                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.014014                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.012654                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.736831                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          262                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15178                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 11058.580214                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   574.634156                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   222.368326                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   216.541992                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.674962                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.035073                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.013572                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.013217                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.736824                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022          275                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15165                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::0            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1           10                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2           23                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3            8                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4          220                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          972                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1056                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13076                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.015991                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.926392                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        175272106                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       175272106                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      5436552                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      5436552                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       226009                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       226009                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst          213                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total          213                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      5243702                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      5243702                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst          213                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      5469711                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         5469924                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst          213                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      5469711                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        5469924                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data          509                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total          509                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          697                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          697                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          487                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          487                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          697                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          996                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          1693                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          697                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          996                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         1693                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     35228000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     35228000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     48202000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     48202000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     30204500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     30204500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     48202000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     65432500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    113634500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     48202000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     65432500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    113634500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      5436552                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      5436552                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       226518                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       226518                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1            9                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2           17                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3           10                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4          238                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          966                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1062                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13065                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.016785                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.925598                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        175272448                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       175272448                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      5432438                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      5432438                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       226006                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       226006                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst          217                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total          217                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      5243653                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      5243653                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst          217                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      5469659                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         5469876                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst          217                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      5469659                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        5469876                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data          504                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total          504                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          693                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          693                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          553                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          553                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          693                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         1057                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          1750                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          693                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         1057                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         1750                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     42131500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     42131500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     47516500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     47516500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     32807500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     32807500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     47516500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     74939000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    122455500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     47516500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     74939000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    122455500                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks      5432438                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      5432438                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       226510                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       226510                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          910                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::total          910                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      5244189                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      5244189                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      5244206                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      5244206                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          910                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      5470707                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      5471617                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      5470716                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      5471626                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          910                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      5470707                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      5471617                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.002247                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.002247                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.765934                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.765934                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000093                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000093                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.765934                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.000182                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.000309                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.765934                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.000182                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.000309                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69210.216110                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69210.216110                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 69156.384505                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 69156.384505                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 62021.560575                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 62021.560575                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69156.384505                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65695.281124                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 67120.200827                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69156.384505                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65695.281124                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 67120.200827                       # average overall miss latency
+system.cpu.l2cache.overall_accesses::cpu.data      5470716                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      5471626                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.002225                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.002225                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.761538                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.761538                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000105                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000105                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.761538                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.000193                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.000320                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.761538                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.000193                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.000320                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83594.246032                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83594.246032                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68566.378066                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68566.378066                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59326.401447                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59326.401447                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68566.378066                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70897.824030                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 69974.571429                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68566.378066                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70897.824030                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69974.571429                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1054,141 +1055,141 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks          415                       # number of writebacks
-system.cpu.l2cache.writebacks::total              415                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data          169                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total          169                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           46                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total           46                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data          215                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total          217                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data          215                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total          217                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks           11                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total           11                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher        20231                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total        20231                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          340                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total          340                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          695                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          695                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          441                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          441                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          695                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          781                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         1476                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          695                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          781                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher        20231                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        21707                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    860658985                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    860658985                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     26049500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     26049500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     43944500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     43944500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     25180500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     25180500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     43944500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     51230000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     95174500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     43944500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     51230000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    860658985                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    955833485                       # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks          429                       # number of writebacks
+system.cpu.l2cache.writebacks::total              429                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data          163                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total          163                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           90                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total           90                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data          253                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total          254                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data          253                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total          254                       # number of overall MSHR hits
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks           13                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total           13                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher        20697                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total        20697                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          341                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total          341                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          692                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          692                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          463                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          463                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          692                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          804                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         1496                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          692                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          804                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher        20697                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        22193                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    848986877                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    848986877                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     32854500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     32854500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     43305000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     43305000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     25953500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     25953500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     43305000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     58808000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    102113000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     43305000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     58808000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    848986877                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    951099877                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001501                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001501                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.763736                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.763736                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000084                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.763736                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.000143                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.000270                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.763736                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.000143                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001505                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001505                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.760440                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.760440                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000088                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000088                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.760440                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.000147                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.000273                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.760440                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.000147                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.003967                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 42541.593841                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 42541.593841                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76616.176471                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76616.176471                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63229.496403                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63229.496403                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 57098.639456                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 57098.639456                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63229.496403                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65595.390525                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64481.368564                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63229.496403                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65595.390525                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 42541.593841                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44033.421707                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.004056                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41019.803691                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 41019.803691                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96347.507331                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96347.507331                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62579.479769                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62579.479769                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 56055.075594                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 56055.075594                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62579.479769                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73144.278607                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68257.352941                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62579.479769                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73144.278607                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41019.803691                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42855.849908                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp       5245099                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      5436967                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        31344                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq        22118                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       226518                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       226518                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       5245116                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      5432867                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        35515                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq        22583                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       226510                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       226510                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq          910                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      5244189                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      5244206                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2259                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     16408706                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          16410965                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     16408733                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          16410992                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        58240                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    698064576                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          698122816                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       22698                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     10964961                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.002070                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.045451                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    697801856                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          697860096                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       23225                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     10965506                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.002118                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.045973                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           10942263     99.79%     99.79% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              22698      0.21%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           10942281     99.79%     99.79% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              23225      0.21%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       10964961                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    10907683500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization         18.8                       # Layer utilization (%)
+system.cpu.toL2Bus.snoop_fanout::total       10965506                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    10903578500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization         18.7                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       1366996                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    8206064991                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    8206077992                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization         14.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              15676                       # Transaction distribution
-system.membus.trans_dist::Writeback               415                       # Transaction distribution
-system.membus.trans_dist::CleanEvict              117                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               340                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              340                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         15676                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        32564                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  32564                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1051584                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1051584                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              15736                       # Transaction distribution
+system.membus.trans_dist::Writeback               429                       # Transaction distribution
+system.membus.trans_dist::CleanEvict              169                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               341                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              341                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         15736                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        32752                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  32752                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1056384                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1056384                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             16548                       # Request fanout histogram
+system.membus.snoop_fanout::samples             16675                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   16548    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   16675    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               16548                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            27912645                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total               16675                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            28309413                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           83778508                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           84107303                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
index 7cef0aacd8bf2984ef976ae2c4742617943c4922..c93b4b47a25eb8073fe17f669a61c80306bbfcac 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.233283                       # Number of seconds simulated
-sim_ticks                                233282768000                       # Number of ticks simulated
-final_tick                               233282768000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.233332                       # Number of seconds simulated
+sim_ticks                                233331881000                       # Number of ticks simulated
+final_tick                               233331881000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 136250                       # Simulator instruction rate (inst/s)
-host_op_rate                                   147606                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               62910352                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 320784                       # Number of bytes of host memory used
-host_seconds                                  3708.18                       # Real time elapsed on the host
+host_inst_rate                                 137799                       # Simulator instruction rate (inst/s)
+host_op_rate                                   149285                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               63638999                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 320760                       # Number of bytes of host memory used
+host_seconds                                  3666.49                       # Real time elapsed on the host
 sim_insts                                   505237724                       # Number of instructions simulated
 sim_ops                                     547350945                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            683136                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9221056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher     16463744                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             26367936                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       683136                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          683136                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18705728                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18705728                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              10674                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             144079                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher       257246                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                411999                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          292277                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               292277                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2928360                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             39527377                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     70574197                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               113029935                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2928360                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2928360                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          80184782                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               80184782                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          80184782                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2928360                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            39527377                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     70574197                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              193214717                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        411999                       # Number of read requests accepted
-system.physmem.writeReqs                       292277                       # Number of write requests accepted
-system.physmem.readBursts                      411999                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     292277                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 26229824                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    138112                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18703872                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  26367936                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18705728                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     2158                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       4                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bytes_read::cpu.inst            689792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9194752                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher     16497856                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             26382400                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       689792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          689792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18714240                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18714240                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              10778                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             143668                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher       257779                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                412225                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          292410                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               292410                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2956270                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             39406325                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     70705537                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               113068132                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2956270                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2956270                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          80204385                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               80204385                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          80204385                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2956270                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            39406325                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     70705537                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              193272517                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        412225                       # Number of read requests accepted
+system.physmem.writeReqs                       292410                       # Number of write requests accepted
+system.physmem.readBursts                      412225                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     292410                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 26244608                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                    137792                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18711808                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  26382400                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18714240                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     2153                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       7                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              3                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               26728                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25477                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25253                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24678                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               27151                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               26546                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25195                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24195                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25840                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               24882                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              24886                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              26093                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              26302                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              26067                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              24895                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25653                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               18973                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               18287                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               17868                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               17935                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               18795                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               18319                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               17931                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               17655                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18179                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               17927                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              17987                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              18662                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              18697                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              18344                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              18231                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              18458                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               26528                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25539                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25303                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24713                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               27194                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               26607                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24941                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24442                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25767                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               24723                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25091                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              26187                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              26462                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              26013                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25052                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25510                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               18779                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               18326                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               18027                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               17939                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               18703                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               18353                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               17755                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               17808                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               18074                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               17824                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              18093                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              18724                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              18814                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              18339                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              18411                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              18403                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    233282750000                       # Total gap between requests
+system.physmem.totGap                    233331863000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  411999                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  412225                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 292277                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    312898                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     47873                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     13110                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      9133                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      7330                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      6176                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      5273                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4418                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3450                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        96                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       40                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       11                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        6                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 292410                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    311682                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     49314                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     13194                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      9237                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      7343                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      6192                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      5234                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4415                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3338                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        64                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       32                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       14                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       10                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
@@ -148,31 +148,31 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6395                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     6689                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    13204                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    15353                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    16370                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    16918                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17192                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17443                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17610                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    17839                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    18048                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    18366                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    18616                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    18818                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    19964                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    18185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17613                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17459                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6393                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     6662                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    13233                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    15393                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    16401                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    16959                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17206                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17395                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17650                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    17892                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    17983                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    18388                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    18586                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    18721                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    19985                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    18227                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17652                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17464                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       47                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       29                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
@@ -197,102 +197,102 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       306889                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      146.413224                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     102.997180                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     182.093051                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         184151     60.01%     60.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        82036     26.73%     86.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        16582      5.40%     92.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7394      2.41%     94.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         4756      1.55%     96.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2254      0.73%     96.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1661      0.54%     97.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1625      0.53%     97.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6430      2.10%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         306889                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         17312                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.673001                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      116.829793                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           17311     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       307255                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      146.312346                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     102.902161                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     182.114345                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         184693     60.11%     60.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        81851     26.64%     86.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        16642      5.42%     92.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7320      2.38%     94.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         4729      1.54%     96.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2259      0.74%     96.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1737      0.57%     97.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1607      0.52%     97.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6417      2.09%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         307255                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17328                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.664070                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      116.589701                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           17327     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::14848-15359            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17312                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         17312                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.881238                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.838780                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.240848                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              10485     60.56%     60.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                306      1.77%     62.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               5502     31.78%     94.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                671      3.88%     97.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                134      0.77%     98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 74      0.43%     99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 42      0.24%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 45      0.26%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 29      0.17%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 14      0.08%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  9      0.05%     99.99% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           17328                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17328                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.872807                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.831610                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.219578                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              10506     60.63%     60.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                279      1.61%     62.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               5596     32.29%     94.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                616      3.55%     98.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                141      0.81%     98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 60      0.35%     99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 44      0.25%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 41      0.24%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 25      0.14%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 12      0.07%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  7      0.04%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::28                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17312                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     9036310212                       # Total ticks spent queuing
-system.physmem.totMemAccLat               16720828962                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2049205000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       22048.33                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           17328                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     9022211140                       # Total ticks spent queuing
+system.physmem.totMemAccLat               16711061140                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2050360000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       22001.53                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  40798.33                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         112.44                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          80.18                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      113.03                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       80.18                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  40751.53                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         112.48                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          80.19                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      113.07                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       80.20                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.50                       # Data bus utilization in percentage
+system.physmem.busUtil                           1.51                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.88                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.63                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.15                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.78                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     299552                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95641                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   73.09                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  32.72                       # Row buffer hit rate for writes
-system.physmem.avgGap                       331237.68                       # Average gap between requests
-system.physmem.pageHitRate                      56.29                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1156763160                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  631170375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1600435200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                944401680                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            15236457600                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            74473770375                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            74637909000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             168680907390                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              723.094931                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   123643637069                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      7789600000                       # Time in different power states
+system.physmem.avgRdQLen                         1.17                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        21.59                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     299444                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     95740                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   73.02                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  32.74                       # Row buffer hit rate for writes
+system.physmem.avgGap                       331138.62                       # Average gap between requests
+system.physmem.pageHitRate                      56.26                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1156823640                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  631203375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1601035800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                944071200                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            15240017520                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            75187551735                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            74044498500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             168805201770                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              723.458661                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   122654182736                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      7791420000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    101845250931                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    102885452264                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1163007720                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  634577625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1595802000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                949158000                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            15236457600                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            74040443550                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            75018020250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             168637466745                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              722.908711                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   124281047938                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      7789600000                       # Time in different power states
+system.physmem_1.actEnergy                 1166024160                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  636223500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1597377600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                950499360                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            15240017520                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            74554879950                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            74599507500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             168744529590                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              723.198461                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   123580654566                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      7791420000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    101208398062                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    101958813184                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               175089811                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         131337021                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           7444155                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             90376647                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                83876100                       # Number of BTB hits
+system.cpu.branchPred.lookups               175090137                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         131338905                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           7443529                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             90540858                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                83879425                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.807271                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                12110019                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             104160                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             92.642622                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                12110692                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             104166                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -411,129 +411,129 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                        466565537                       # number of cpu cycles simulated
+system.cpu.numCycles                        466663763                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles            7838065                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      731795546                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   175089811                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           95986119                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     450385778                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                14940817                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 5837                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           243                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles        14677                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 236716672                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 34578                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          465715008                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.701748                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.179403                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles            7839248                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      731808788                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   175090137                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           95990117                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     450472274                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                14939659                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 5656                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           157                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles        14269                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 236720425                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 34587                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          465801433                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.701462                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.179511                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 93791115     20.14%     20.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                132693411     28.49%     48.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 57855471     12.42%     61.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                181375011     38.95%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 93869731     20.15%     20.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                132699774     28.49%     48.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 57852108     12.42%     61.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                181379820     38.94%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            465715008                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.375274                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.568473                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 32367511                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             117249871                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 287084329                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              22031549                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                6981748                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             24050134                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                496459                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              715800999                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              30008433                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                6981748                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 63425626                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                54212557                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       40336788                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 276681526                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              24076763                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              686589929                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              13340569                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               9410638                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2384158                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1669115                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                1841927                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           831018421                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3019159141                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        723918647                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total            465801433                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.375195                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.568171                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 32373679                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             117343382                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 287062106                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              22041011                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                6981255                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             24049971                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                496386                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              715809364                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              30003912                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                6981255                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 63434666                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                54211510                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       40338612                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 276664591                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              24170799                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              686600417                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              13340367                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               9416739                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2386420                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1670076                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                1927738                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           831025477                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3019202538                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        723925996                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups               416                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             654123751                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                176894670                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1544698                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        1534992                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  42289780                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            143526215                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            67981217                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          12855514                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         11197113                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  668159255                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2978326                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 610231748                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           5860169                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       123786636                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    319274742                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            694                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     465715008                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.310312                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.101358                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                176901726                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1544701                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        1534906                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  42308307                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            143530339                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            67981565                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          12860716                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         11266999                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  668170903                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2978331                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 610248763                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           5854866                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       123798289                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    319264737                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            699                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     465801433                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.310105                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.101429                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           148574576     31.90%     31.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           101171602     21.72%     53.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           145766544     31.30%     84.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            63282576     13.59%     98.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6919220      1.49%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 490      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           148653685     31.91%     31.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           101184506     21.72%     53.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           145749505     31.29%     84.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            63290175     13.59%     98.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             6923088      1.49%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 474      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       465715008                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       465801433                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                71921517     52.96%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     30      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               44556516     32.81%     85.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              19328890     14.23%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                71924616     52.97%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     30      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               44553347     32.81%     85.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              19296722     14.21%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             413144323     67.70%     67.70% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               351745      0.06%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             413148587     67.70%     67.70% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               351752      0.06%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.76% # Type of FU issued
@@ -561,84 +561,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.76% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            134209580     21.99%     89.75% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            62526097     10.25%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            134215566     21.99%     89.75% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            62532855     10.25%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              610231748                       # Type of FU issued
-system.cpu.iq.rate                           1.307923                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   135806953                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.222550                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         1827845333                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         794952356                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    594966802                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total              610248763                       # Type of FU issued
+system.cpu.iq.rate                           1.307684                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   135774715                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.222491                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1827928247                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         794975703                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    594980555                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                 293                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                316                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              746038524                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses              746023301                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                     177                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          7273046                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads          7276983                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     27641459                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        25471                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        28891                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     11120740                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     27645583                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        25497                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        28922                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     11121088                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       225190                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         22470                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       225125                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         22421                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                6981748                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                23001930                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                919984                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           672625014                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                6981255                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                22978687                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                924846                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           672636723                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             143526215                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             67981217                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1489784                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 258650                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                525178                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          28891                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3821630                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3731398                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              7553028                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             599382547                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             129570228                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          10849201                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             143530339                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             67981565                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1489789                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 258799                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                529739                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          28922                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3821583                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3731049                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              7552632                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             599397786                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             129576337                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          10850977                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       1487433                       # number of nop insts executed
-system.cpu.iew.exec_refs                    190523509                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                131370037                       # Number of branches executed
-system.cpu.iew.exec_stores                   60953281                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.284670                       # Inst execution rate
-system.cpu.iew.wb_sent                      596261681                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     594966818                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 349901968                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 570648646                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       1487489                       # number of nop insts executed
+system.cpu.iew.exec_refs                    190533026                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                131372234                       # Number of branches executed
+system.cpu.iew.exec_stores                   60956689                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.284432                       # Inst execution rate
+system.cpu.iew.wb_sent                      596275489                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     594980571                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 349907425                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 570632122                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.275205                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.613165                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.274966                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.613193                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       110016162                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       110027797                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls         2977632                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           6955495                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    448601420                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.223123                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.887905                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           6954955                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    448686365                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.222892                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.888131                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    219539851     48.94%     48.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    116349885     25.94%     74.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     43748468      9.75%     84.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     23302371      5.19%     89.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     11552802      2.58%     92.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      7777273      1.73%     94.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8275373      1.84%     95.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      4252092      0.95%     96.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     13803305      3.08%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    219669318     48.96%     48.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    116312485     25.92%     74.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     43742979      9.75%     84.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     23278779      5.19%     89.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     11577691      2.58%     92.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      7777719      1.73%     94.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      8261206      1.84%     95.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      4236050      0.94%     96.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     13830138      3.08%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    448601420                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    448686365                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            506581608                       # Number of instructions committed
 system.cpu.commit.committedOps              548694829                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -684,182 +684,182 @@ system.cpu.commit.op_class_0::MemWrite       56860477     10.36%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         548694829                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              13803305                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1093501968                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1334565325                       # The number of ROB writes
-system.cpu.timesIdled                           13884                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          850529                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              13830138                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1093571715                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1334590067                       # The number of ROB writes
+system.cpu.timesIdled                           13966                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          862330                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   505237724                       # Number of Instructions Simulated
 system.cpu.committedOps                     547350945                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.923457                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.923457                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.082887                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.082887                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                611072880                       # number of integer regfile reads
-system.cpu.int_regfile_writes               328111730                       # number of integer regfile writes
+system.cpu.cpi                               0.923652                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.923652                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.082659                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.082659                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                611088796                       # number of integer regfile reads
+system.cpu.int_regfile_writes               328119086                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                2170116632                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                376537008                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               217962216                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                2170176811                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                376539852                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               217970841                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                2977084                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           2820796                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.631791                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           169351038                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2821308                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             60.025718                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         498038000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.631791                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999281                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999281                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2820945                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.631358                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           169354520                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2821457                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             60.023782                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         498530000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.631358                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999280                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999280                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          170                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          275                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          164                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          281                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         356237372                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        356237372                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    114646487                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       114646487                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     51724617                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       51724617                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data         2783                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total          2783                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses         356242117                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        356242117                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    114648793                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       114648793                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     51725790                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       51725790                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data         2786                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total          2786                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488560                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total      1488560                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     166371104                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        166371104                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    166373887                       # number of overall hits
-system.cpu.dcache.overall_hits::total       166373887                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      4842277                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       4842277                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2514689                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2514689                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data           12                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total           12                       # number of SoftPFReq misses
+system.cpu.dcache.demand_hits::cpu.data     166374583                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        166374583                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    166377369                       # number of overall hits
+system.cpu.dcache.overall_hits::total       166377369                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      4842267                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       4842267                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2513516                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2513516                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data           11                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total           11                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data           66                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total           66                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      7356966                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        7356966                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      7356978                       # number of overall misses
-system.cpu.dcache.overall_misses::total       7356978                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  56244825000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  56244825000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  18846227941                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  18846227941                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      1242500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total      1242500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  75091052941                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  75091052941                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  75091052941                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  75091052941                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    119488764                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    119488764                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      7355783                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        7355783                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      7355794                       # number of overall misses
+system.cpu.dcache.overall_misses::total       7355794                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  56187510500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  56187510500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  19050466441                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  19050466441                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      1271500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total      1271500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  75237976941                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  75237976941                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  75237976941                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  75237976941                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    119491060                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    119491060                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data         2795                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total         2795                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         2797                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         2797                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488626                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total      1488626                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    173728070                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    173728070                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    173730865                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    173730865                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040525                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.040525                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.046363                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.046363                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.004293                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.004293                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    173730366                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    173730366                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    173733163                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    173733163                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040524                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.040524                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.046341                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.046341                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.003933                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.003933                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000044                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000044                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.042348                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.042348                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.042347                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.042347                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11615.367109                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11615.367109                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  7494.456746                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  7494.456746                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18825.757576                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18825.757576                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 10206.796245                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 10206.796245                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 10206.779596                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 10206.779596                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs           15                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       911242                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          221024                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     7.500000                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     4.122819                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.042340                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.042340                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.042340                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.042340                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11603.554802                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11603.554802                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  7579.210334                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  7579.210334                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19265.151515                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19265.151515                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 10228.411706                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 10228.411706                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 10228.396410                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 10228.396410                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs           19                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       931670                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 3                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          221105                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     6.333333                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     4.213699                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2356243                       # number of writebacks
-system.cpu.dcache.writebacks::total           2356243                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2540565                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      2540565                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1995076                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1995076                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      2357131                       # number of writebacks
+system.cpu.dcache.writebacks::total           2357131                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2540406                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      2540406                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1993903                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1993903                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           66                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total           66                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      4535641                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      4535641                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      4535641                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      4535641                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2301712                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      2301712                       # number of ReadReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      4534309                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      4534309                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      4534309                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      4534309                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2301861                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      2301861                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       519613                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total       519613                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           10                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total           10                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2821325                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2821325                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2821335                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2821335                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  28710026000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  28710026000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4575255494                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4575255494                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       657000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       657000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  33285281494                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  33285281494                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  33285938494                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  33285938494                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.019263                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.019263                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2821474                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2821474                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2821484                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2821484                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  28687651000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  28687651000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4620185994                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4620185994                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       674500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       674500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  33307836994                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  33307836994                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  33308511494                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  33308511494                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.019264                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.019264                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009580                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009580                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.003578                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.003578                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016240                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016240                       # mshr miss rate for demand accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.003575                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.003575                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016241                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016241                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.016240                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.016240                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12473.335500                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12473.335500                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8805.121300                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8805.121300                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        65700                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        65700                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11797.748042                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11797.748042                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11797.939094                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11797.939094                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12462.807702                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12462.807702                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8891.590461                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8891.590461                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        67450                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        67450                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11805.119237                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11805.119237                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11805.316455                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11805.316455                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             73477                       # number of replacements
-system.cpu.icache.tags.tagsinuse           466.193561                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           236634038                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             73989                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           3198.232683                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      114977932500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   466.193561                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.910534                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.910534                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements             73454                       # number of replacements
+system.cpu.icache.tags.tagsinuse           466.198570                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           236637753                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             73966                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           3199.277411                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      114991601500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   466.198570                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.910544                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.910544                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
@@ -867,203 +867,202 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2          119
 system.cpu.icache.tags.age_task_id_blocks_1024::3           18                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4           17                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         473507120                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        473507120                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    236634038                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       236634038                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     236634038                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        236634038                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    236634038                       # number of overall hits
-system.cpu.icache.overall_hits::total       236634038                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        82514                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         82514                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        82514                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          82514                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        82514                       # number of overall misses
-system.cpu.icache.overall_misses::total         82514                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1544948153                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1544948153                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1544948153                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1544948153                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1544948153                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1544948153                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    236716552                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    236716552                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    236716552                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    236716552                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    236716552                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    236716552                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         473514607                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        473514607                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    236637753                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       236637753                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     236637753                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        236637753                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    236637753                       # number of overall hits
+system.cpu.icache.overall_hits::total       236637753                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        82554                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         82554                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        82554                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          82554                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        82554                       # number of overall misses
+system.cpu.icache.overall_misses::total         82554                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1566745159                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1566745159                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1566745159                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1566745159                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1566745159                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1566745159                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    236720307                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    236720307                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    236720307                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    236720307                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    236720307                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    236720307                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000349                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000349                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000349                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000349                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000349                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000349                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18723.466963                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18723.466963                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18723.466963                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18723.466963                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18723.466963                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18723.466963                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs       193180                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets           95                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              6947                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               4                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    27.807687                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    23.750000                       # average number of cycles each access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18978.428168                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18978.428168                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18978.428168                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18978.428168                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18978.428168                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18978.428168                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs       198034                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          192                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              7006                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               6                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    28.266343                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets           32                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         8497                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         8497                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         8497                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         8497                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         8497                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         8497                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        74017                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        74017                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        74017                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        74017                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        74017                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        74017                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1266772756                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1266772756                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1266772756                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1266772756                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1266772756                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1266772756                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         8560                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         8560                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         8560                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         8560                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         8560                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         8560                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        73994                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        73994                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        73994                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        73994                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        73994                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        73994                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1278636265                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1278636265                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1278636265                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1278636265                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1278636265                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1278636265                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000313                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000313                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000313                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000313                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000313                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000313                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17114.619020                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17114.619020                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17114.619020                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 17114.619020                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17114.619020                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 17114.619020                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17280.269549                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17280.269549                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17280.269549                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 17280.269549                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17280.269549                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 17280.269549                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued      8510429                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified      8512950                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit         1055                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued      8511909                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified      8513040                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit          167                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage       742850                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements           400878                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        15418.113154                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            5066482                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           417216                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            12.143547                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      34592827000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  8451.219479                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   476.205325                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  4934.937237                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  1555.751112                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.515822                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.029065                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.301205                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.094956                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.941047                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022         1092                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15246                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2           37                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3          235                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4          819                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          145                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          210                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1560                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         9946                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3385                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.066650                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.930542                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         93192221                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        93192221                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      2356243                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2356243                       # number of Writeback hits
+system.cpu.l2cache.prefetcher.pfSpanPage       743544                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements           401080                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        15418.085448                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            5068240                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           417417                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            12.141911                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      34601120500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks  8466.854939                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   473.689855                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  4911.860449                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  1565.680205                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.516776                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.028912                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.299796                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.095562                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.941045                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022         1090                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15247                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2           32                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3          243                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4          815                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          141                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          209                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1541                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        10024                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3332                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.066528                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.930603                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         93191002                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        93191002                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      2357131                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2357131                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           25                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           25                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       516767                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       516767                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        63301                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        63301                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      2154697                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      2154697                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        63301                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2671464                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2734765                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        63301                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2671464                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2734765                       # number of overall hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       516789                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       516789                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        63176                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        63176                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      2155511                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      2155511                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        63176                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2672300                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2735476                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        63176                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2672300                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2735476                       # number of overall hits
 system.cpu.l2cache.UpgradeReq_misses::cpu.data            2                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total            2                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         5205                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         5205                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        10683                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        10683                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       144639                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       144639                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        10683                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       149844                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        160527                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        10683                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       149844                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       160527                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    460413000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    460413000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    779781500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    779781500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  11147875000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  11147875000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    779781500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  11608288000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  12388069500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    779781500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  11608288000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  12388069500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      2356243                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2356243                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_misses::cpu.data         5171                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         5171                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        10785                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        10785                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       143986                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       143986                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst        10785                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       149157                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        159942                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst        10785                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       149157                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       159942                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    505481000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    505481000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    792508500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    792508500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  11120056000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  11120056000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    792508500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  11625537000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  12418045500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    792508500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  11625537000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  12418045500                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks      2357131                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2357131                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data           27                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total           27                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       521972                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       521972                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        73984                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        73984                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      2299336                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      2299336                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        73984                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2821308                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2895292                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        73984                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2821308                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2895292                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       521960                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       521960                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        73961                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        73961                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      2299497                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      2299497                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        73961                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2821457                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2895418                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        73961                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2821457                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2895418                       # number of overall (read+write) accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.074074                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.074074                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.009972                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.009972                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.144396                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.144396                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.062905                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.062905                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.144396                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.053112                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.055444                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.144396                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.053112                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.055444                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88455.907781                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88455.907781                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72992.745483                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72992.745483                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77073.783696                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77073.783696                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72992.745483                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77469.154587                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77171.251565                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72992.745483                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77469.154587                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77171.251565                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.009907                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.009907                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.145820                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.145820                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.062616                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.062616                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.145820                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.052865                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.055240                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.145820                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.052865                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.055240                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 97753.045833                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 97753.045833                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73482.475661                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73482.475661                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77230.119595                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77230.119595                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73482.475661                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77941.611859                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77640.929212                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73482.475661                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77941.611859                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77640.929212                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1072,153 +1071,153 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       292277                       # number of writebacks
-system.cpu.l2cache.writebacks::total           292277                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1529                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total         1529                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            8                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total            8                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data         4235                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total         4235                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            8                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data         5764                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total         5772                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            8                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data         5764                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total         5772                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         6839                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total         6839                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       274923                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total       274923                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks       292410                       # number of writebacks
+system.cpu.l2cache.writebacks::total           292410                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1449                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total         1449                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            6                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            6                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data         4039                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total         4039                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            6                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data         5488                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total         5494                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            6                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data         5488                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total         5494                       # number of overall MSHR hits
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         6957                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         6957                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       275571                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total       275571                       # number of HardPFReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            2                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total            2                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3676                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         3676                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        10675                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        10675                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       140404                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       140404                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        10675                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       144080                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       154755                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        10675                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       144080                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       274923                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       429678                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  19117391245                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  19117391245                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        33000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        33000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    289648000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    289648000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    715179500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    715179500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   9979387500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   9979387500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    715179500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10269035500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  10984215000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    715179500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10269035500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  19117391245                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  30101606245                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3722                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         3722                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        10779                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        10779                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       139947                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       139947                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        10779                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       143669                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       154448                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        10779                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       143669                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       275571                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       430019                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  19018555494                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  19018555494                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        33500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        33500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    344223500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    344223500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    727200000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    727200000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   9979336000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   9979336000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    727200000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10323559500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  11050759500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    727200000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10323559500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  19018555494                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  30069314994                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.074074                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.074074                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.007043                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.007043                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.144288                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.144288                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.061063                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.061063                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.144288                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.051069                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.053451                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.144288                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.051069                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.007131                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.007131                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.145739                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.145739                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.060860                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.060860                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.145739                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.050920                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.053342                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.145739                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.050920                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.148406                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69537.256777                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69537.256777                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        16500                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        16500                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78794.341676                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78794.341676                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66995.737705                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66995.737705                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71076.233583                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71076.233583                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66995.737705                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71273.150333                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70978.094407                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66995.737705                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71273.150333                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69537.256777                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70056.196140                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.148517                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69015.083205                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69015.083205                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        16750                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        16750                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92483.476625                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92483.476625                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67464.514333                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67464.514333                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71307.966587                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71307.966587                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67464.514333                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71856.555694                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71550.033021                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67464.514333                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71856.555694                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69015.083205                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69925.549787                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp       2373352                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2648520                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       622852                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       320716                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2373490                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2649541                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       621819                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       317371                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq           27                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp           27                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       521972                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       521972                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        74017                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      2299336                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       220623                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8440541                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8661164                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4734912                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    331363264                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          336098176                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      721627                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      6511219                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.110823                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.313913                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadExReq       521960                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       521960                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        73994                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      2299497                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       220555                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8440647                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8661202                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4733440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    331429632                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          336163072                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      718484                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      6508328                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.110389                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.313375                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            5789625     88.92%     88.92% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             721594     11.08%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            5789877     88.96%     88.96% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             718451     11.04%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        6511219                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5251055500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        6508328                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5252069500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          2.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     111049948                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     111018442                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    4231992466                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    4232215467                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.8                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             408324                       # Transaction distribution
-system.membus.trans_dist::Writeback            292277                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           103036                       # Transaction distribution
+system.membus.trans_dist::ReadResp             408504                       # Transaction distribution
+system.membus.trans_dist::Writeback            292410                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           103085                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq                3                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              3675                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3675                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        408324                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1219317                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1219317                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     45073664                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                45073664                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq              3721                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3721                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        408504                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1219951                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1219951                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     45096640                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                45096640                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            807315                       # Request fanout histogram
+system.membus.snoop_fanout::samples            807723                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  807315    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  807723    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              807315                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          2175050688                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              807723                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          2173813941                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2177979128                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2179181168                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
index 8a385b77d56302eaf158b84202b40d42180761fe..c456278d9d309ac1264f494336c02f81cadb22bf 100644 (file)
@@ -1,46 +1,46 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.112686                       # Number of seconds simulated
-sim_ticks                                112686104500                       # Number of ticks simulated
-final_tick                               112686104500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.112687                       # Number of seconds simulated
+sim_ticks                                112687034500                       # Number of ticks simulated
+final_tick                               112687034500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 125538                       # Simulator instruction rate (inst/s)
-host_op_rate                                   150722                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               51811162                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 327864                       # Number of bytes of host memory used
-host_seconds                                  2174.94                       # Real time elapsed on the host
+host_inst_rate                                 126437                       # Simulator instruction rate (inst/s)
+host_op_rate                                   151802                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               52182660                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 327844                       # Number of bytes of host memory used
+host_seconds                                  2159.47                       # Real time elapsed on the host
 sim_insts                                   273037220                       # Number of instructions simulated
 sim_ops                                     327811602                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            187072                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            112896                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher       167936                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               467904                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            112448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher       169152                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               468672                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst       187072                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          187072                       # Number of instructions bytes read from this memory
 system.physmem.num_reads::cpu.inst               2923                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1764                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher         2624                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7311                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1660116                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1001863                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher      1490299                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4152278                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1660116                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1660116                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1660116                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1001863                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher      1490299                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4152278                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7311                       # Number of read requests accepted
+system.physmem.num_reads::cpu.data               1757                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher         2643                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7323                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1660102                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               997879                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher      1501078                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4159059                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1660102                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1660102                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1660102                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              997879                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher      1501078                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4159059                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7323                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        7311                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        7323                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   467904                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   468672                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    467904                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    468672                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
@@ -52,7 +52,7 @@ system.physmem.perBankRdBursts::3                 520                       # Pe
 system.physmem.perBankRdBursts::4                 444                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 346                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 153                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 252                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 251                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 219                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 290                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                315                       # Per bank write bursts
@@ -60,7 +60,7 @@ system.physmem.perBankRdBursts::11                411                       # Pe
 system.physmem.perBankRdBursts::12                547                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                678                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                615                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                542                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                555                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    112685946000                       # Total gap between requests
+system.physmem.totGap                    112686876000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7311                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7323                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -94,21 +94,21 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      3986                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1457                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       456                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       293                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4012                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1463                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       466                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       286                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                       235                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       200                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       175                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       198                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       151                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        66                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       30                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       20                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       17                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       210                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       170                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       170                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       174                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        54                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       22                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       18                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       16                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
@@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1367                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      340.646672                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     198.022122                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     348.529599                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            486     35.55%     35.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          298     21.80%     57.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          139     10.17%     67.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           76      5.56%     73.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           63      4.61%     77.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           51      3.73%     81.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           27      1.98%     83.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           26      1.90%     85.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          201     14.70%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1367                       # Bytes accessed per row activation
-system.physmem.totQLat                      102208518                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 239289768                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     36555000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13980.10                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1371                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      339.932896                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     197.349943                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     349.457617                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            486     35.45%     35.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          309     22.54%     57.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          132      9.63%     67.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           75      5.47%     73.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           64      4.67%     77.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           48      3.50%     81.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           26      1.90%     83.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           25      1.82%     84.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          206     15.03%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1371                       # Bytes accessed per row activation
+system.physmem.totQLat                       95174041                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 232480291                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     36615000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12996.59                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  32730.10                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.15                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31746.59                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.16                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.15                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.16                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.49                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.45                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       5935                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       5943                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.18                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.16                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15413205.58                       # Average gap between requests
-system.physmem.pageHitRate                      81.18                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                     15388075.38                       # Average gap between requests
+system.physmem.pageHitRate                      81.16                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                    4815720                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                    2627625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  28657200                       # Energy for read commands per rank (pJ)
+system.physmem_0.readEnergy                  28641600                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy             7359880320                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             3231673425                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            64774920750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              75402575040                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.157389                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   107755851914                       # Time in different power states
+system.physmem_0.actBackEnergy             3233168820                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            64773630750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              75402764835                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.158858                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   107753956620                       # Time in different power states
 system.physmem_0.memoryStateTime::REF      3762720000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1164613086                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1166688380                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    5496120                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2998875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  28064400                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    5526360                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    3015375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  28126800                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy             7359880320                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             3295137510                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            64719250500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              75410827725                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.230627                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   107661884129                       # Time in different power states
+system.physmem_1.actBackEnergy             3309876000                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            64706325000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              75412749855                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.247655                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   107640832624                       # Time in different power states
 system.physmem_1.memoryStateTime::REF      3762720000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1258279621                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1279848380                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                37742989                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          20164516                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1746156                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             18663196                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                17299233                       # Number of BTB hits
+system.cpu.branchPred.lookups                37743135                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          20164607                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1746155                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             18663607                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                17299273                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.691697                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 7223653                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               3816                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             92.689870                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 7223670                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               3815                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -381,95 +381,95 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                        225372210                       # number of cpu cycles simulated
+system.cpu.numCycles                        225374070                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           12439138                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      334051202                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    37742989                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           24522886                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     210855691                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 3510707                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 1284                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles         2593                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  89092155                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 21708                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          225054059                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.800470                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.229417                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           12439227                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      334051995                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    37743135                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           24522943                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     210854521                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 3510703                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 1310                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.IcacheWaitRetryStallCycles         2474                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  89092353                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 21704                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          225052883                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.800484                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.229411                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 51374086     22.83%     22.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 42891136     19.06%     41.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 30054592     13.35%     55.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                100734245     44.76%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 51372314     22.83%     22.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 42891452     19.06%     41.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 30054577     13.35%     55.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                100734540     44.76%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            225054059                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.167470                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.482220                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 27837229                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              63912010                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 108618315                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              23065911                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1620594                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              6880048                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                135198                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              363546099                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               6169805                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1620594                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 45200014                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                17874059                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         342377                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 113380979                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              46636036                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              355768136                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               2890465                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               6610669                       # Number of times rename has blocked due to ROB full
+system.cpu.fetch.rateDist::total            225052883                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.167469                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.482211                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 27836779                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              63911722                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 108618516                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              23065273                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1620593                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              6880055                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                135197                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              363544847                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               6170021                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1620593                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 45199707                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                17872689                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         341815                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 113380410                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              46637669                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              355768309                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               2890306                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               6609751                       # Number of times rename has blocked due to ROB full
 system.cpu.rename.IQFullEvents                 177931                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                7803674                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               21223053                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents          2890533                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           403406015                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2534023592                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        350247327                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         194894263                       # Number of floating rename lookups
+system.cpu.rename.LQFullEvents                7804271                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               21223751                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents          2890543                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           403406246                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2534025265                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        350247395                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         194894231                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             372230051                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 31175964                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                 31176195                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts              17016                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts          17025                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  55505783                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             92416404                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            88498336                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1661010                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1846418                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  353252226                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts                  55506509                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             92416612                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            88498373                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1661373                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1847329                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  353252571                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded               28026                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 346438238                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           2301579                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        25468650                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     73725461                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                 346438287                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           2302047                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        25468995                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     73729207                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved           5906                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     225054059                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.539356                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.099855                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples     225052883                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.539364                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.099868                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            40665072     18.07%     18.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            78300215     34.79%     52.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            60997700     27.10%     79.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            34882254     15.50%     95.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             9557051      4.25%     99.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5              642945      0.29%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                8822      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            40665148     18.07%     18.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            78299865     34.79%     52.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            60995131     27.10%     79.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            34883362     15.50%     95.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             9557615      4.25%     99.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5              642958      0.29%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                8804      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       225054059                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       225052883                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 9490410      7.63%      7.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   7314      0.01%      7.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 9490613      7.63%      7.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   7317      0.01%      7.64% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.64% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.64% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.64% # attempts to use FU when none available
@@ -488,22 +488,22 @@ system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.64% # at
 system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.64% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.64% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd            255762      0.21%      7.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd            255761      0.21%      7.84% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp            126866      0.10%      7.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt             93218      0.07%      8.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp            126865      0.10%      7.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt             93219      0.07%      8.02% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatDiv             68015      0.05%      8.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc           721741      0.58%      8.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult           297231      0.24%      8.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc        683043      0.55%      9.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc           721837      0.58%      8.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult           297231      0.24%      8.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc        683044      0.55%      9.44% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               53642366     43.14%     52.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              58960700     47.42%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               53642383     43.14%     52.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              58959382     47.42%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             110655140     31.94%     31.94% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2148362      0.62%     32.56% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             110655137     31.94%     31.94% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2148355      0.62%     32.56% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     32.56% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     32.56% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     32.56% # Type of FU issued
@@ -522,93 +522,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     32.56% # Ty
 system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     32.56% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     32.56% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd         6798396      1.96%     34.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         6798397      1.96%     34.52% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     34.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp         8668155      2.50%     37.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         3332481      0.96%     37.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         8668117      2.50%     37.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         3332482      0.96%     37.99% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv         1592458      0.46%     38.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       20930094      6.04%     44.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult        7182326      2.07%     46.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       20930149      6.04%     44.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult        7182320      2.07%     46.56% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc      7148962      2.06%     48.63% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt         175286      0.05%     48.68% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             91923219     26.53%     75.21% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            85883359     24.79%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             91923270     26.53%     75.21% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            85883354     24.79%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              346438238                       # Type of FU issued
-system.cpu.iq.rate                           1.537183                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   124346666                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.358929                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          757024395                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         251740362                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    223260150                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           287554385                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          127018791                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    117424955                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              303230405                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               167554499                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          5064919                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              346438287                       # Type of FU issued
+system.cpu.iq.rate                           1.537170                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   124345667                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.358926                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          757022758                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         251740405                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    223260402                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           287554413                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          127019437                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    117424930                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              303229780                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               167554174                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          5064825                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      6684129                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        13573                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        10255                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6122719                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      6684337                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        13570                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        10254                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      6122756                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       155303                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        607776                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       155338                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        607759                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1620594                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 2118849                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                332046                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           353281117                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                1620593                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 2118874                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                332196                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           353281462                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              92416404                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             88498336                       # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts              92416612                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             88498373                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts              16993                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                   8049                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                338505                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          10255                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1220656                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       439058                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1659714                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             342448377                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              90703712                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3989861                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewLSQFullEvents                338656                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          10254                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1220664                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       439075                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1659739                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             342448688                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              90703769                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3989599                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                           865                       # number of nop insts executed
-system.cpu.iew.exec_refs                    175291126                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 31752707                       # Number of branches executed
-system.cpu.iew.exec_stores                   84587414                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.519479                       # Inst execution rate
-system.cpu.iew.wb_sent                      340943800                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     340685105                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 153662327                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 266738216                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    175291174                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 31752726                       # Number of branches executed
+system.cpu.iew.exec_stores                   84587405                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.519468                       # Inst execution rate
+system.cpu.iew.wb_sent                      340944051                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     340685332                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 153662647                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 266737544                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.511655                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.576079                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.511644                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.576082                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        23082519                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        23083260                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           22120                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts           1611397                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    221328864                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.481109                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.050764                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples    221327720                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.481117                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.050757                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     87530154     39.55%     39.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     70479011     31.84%     71.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     20814829      9.40%     80.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     13433176      6.07%     86.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      8801116      3.98%     90.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      4514131      2.04%     92.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      2986629      1.35%     94.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      2449420      1.11%     95.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     10320398      4.66%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     87528718     39.55%     39.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     70478843     31.84%     71.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     20814822      9.40%     80.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     13433890      6.07%     86.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      8801339      3.98%     90.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      4513701      2.04%     92.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      2986759      1.35%     94.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      2449542      1.11%     95.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     10320106      4.66%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    221328864                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    221327720                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            273037832                       # Number of instructions committed
 system.cpu.commit.committedOps              327812214                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -654,92 +654,92 @@ system.cpu.commit.op_class_0::MemWrite       82375617     25.13%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         327812214                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              10320398                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    561900676                       # The number of ROB reads
-system.cpu.rob.rob_writes                   705518580                       # The number of ROB writes
-system.cpu.timesIdled                           50864                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          318151                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              10320106                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    561900565                       # The number of ROB reads
+system.cpu.rob.rob_writes                   705520050                       # The number of ROB writes
+system.cpu.timesIdled                           50865                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          321187                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   273037220                       # Number of Instructions Simulated
 system.cpu.committedOps                     327811602                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.825427                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.825427                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.211495                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.211495                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                331331443                       # number of integer regfile reads
-system.cpu.int_regfile_writes               136939322                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 187108010                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                132178699                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                1297132712                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 80241070                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              1183128145                       # number of misc regfile reads
+system.cpu.cpi                               0.825434                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.825434                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.211485                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.211485                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                331332035                       # number of integer regfile reads
+system.cpu.int_regfile_writes               136939352                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 187107868                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                132178738                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                1297133606                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 80241640                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              1183127847                       # number of misc regfile reads
 system.cpu.misc_regfile_writes               34421755                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements           1533845                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.844014                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           163642665                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse           511.843427                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           163642817                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           1534357                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            106.652275                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          82317000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.844014                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999695                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999695                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.avg_refs            106.652374                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          82681000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.843427                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999694                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999694                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          310                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           90                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         336636785                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        336636785                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     82609327                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        82609327                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     80941037                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       80941037                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        70495                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         70495                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses         336637061                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        336637061                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     82609464                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        82609464                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     80941053                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       80941053                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        70494                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         70494                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        10909                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        10909                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     163550364                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        163550364                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    163620859                       # number of overall hits
-system.cpu.dcache.overall_hits::total       163620859                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2796866                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2796866                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1111662                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1111662                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     163550517                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        163550517                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    163621011                       # number of overall hits
+system.cpu.dcache.overall_hits::total       163621011                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2796868                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2796868                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1111646                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1111646                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data           18                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total           18                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            5                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            5                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      3908528                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3908528                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3908546                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3908546                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  22404027000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  22404027000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   8967503998                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   8967503998                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data      3908514                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3908514                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3908532                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3908532                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  22403262000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  22403262000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   8965991000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   8965991000                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       189000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       189000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  31371530998                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  31371530998                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  31371530998                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  31371530998                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     85406193                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     85406193                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data  31369253000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  31369253000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  31369253000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  31369253000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     85406332                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     85406332                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052699                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     82052699                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data        70513                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total        70513                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data        70512                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total        70512                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10914                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        10914                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    167458892                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    167458892                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    167529405                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    167529405                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    167459031                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    167459031                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    167529543                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    167529543                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032748                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.032748                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013548                       # miss rate for WriteReq accesses
@@ -750,38 +750,38 @@ system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000458
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000458                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.023340                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.023340                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.023331                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.023331                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  8010.404145                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  8010.404145                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  8066.754102                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  8066.754102                       # average WriteReq miss latency
+system.cpu.dcache.overall_miss_rate::cpu.data     0.023330                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.023330                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  8010.124897                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total  8010.124897                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  8065.509164                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  8065.509164                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        37800                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        37800                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  8026.431178                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total  8026.431178                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  8026.394214                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total  8026.394214                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data  8025.877098                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total  8025.877098                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data  8025.840136                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total  8025.840136                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      1059827                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      1060412                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          134751                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          134750                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     7.865077                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     7.869477                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       966339                       # number of writebacks
 system.cpu.dcache.writebacks::total            966339                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1483173                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      1483173                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       891007                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       891007                       # number of WriteReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1483175                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      1483175                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       890991                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       890991                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            5                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            5                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2374180                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2374180                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2374180                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2374180                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2374166                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2374166                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2374166                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2374166                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1313693                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total      1313693                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       220655                       # number of WriteReq MSHR misses
@@ -792,16 +792,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      1534348
 system.cpu.dcache.demand_mshr_misses::total      1534348                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      1534359                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      1534359                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10622731000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10622731000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1827670779                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1827670779                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10623648000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10623648000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1826747781                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1826747781                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       681000                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       681000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  12450401779                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  12450401779                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12451082779                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  12451082779                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  12450395781                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  12450395781                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12451076781                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  12451076781                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015382                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015382                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002689                       # mshr miss rate for WriteReq accesses
@@ -812,26 +812,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.009163
 system.cpu.dcache.demand_mshr_miss_rate::total     0.009163                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.009159                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.009159                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8086.159399                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8086.159399                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8282.933897                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8282.933897                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8086.857432                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8086.857432                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8278.750905                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8278.750905                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61909.090909                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61909.090909                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8114.457593                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  8114.457593                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8114.843253                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  8114.843253                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8114.453684                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  8114.453684                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8114.839344                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  8114.839344                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            715634                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.830268                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            88370349                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            716146                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            123.397113                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle         324802500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.830268                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999668                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999668                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            715635                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.829472                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            88370544                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            716147                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            123.397213                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle         326419500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.829472                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999667                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999667                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          130                       # Occupied blocks per task id
@@ -839,207 +839,207 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2          246
 system.cpu.icache.tags.age_task_id_blocks_1024::3           12                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4           69                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         178900425                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        178900425                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     88370349                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        88370349                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      88370349                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         88370349                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     88370349                       # number of overall hits
-system.cpu.icache.overall_hits::total        88370349                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       721790                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        721790                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       721790                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         721790                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       721790                       # number of overall misses
-system.cpu.icache.overall_misses::total        721790                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   5973224944                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   5973224944                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   5973224944                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   5973224944                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   5973224944                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   5973224944                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     89092139                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     89092139                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     89092139                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     89092139                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     89092139                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     89092139                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         178900820                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        178900820                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     88370544                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        88370544                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      88370544                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         88370544                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     88370544                       # number of overall hits
+system.cpu.icache.overall_hits::total        88370544                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       721792                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        721792                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       721792                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         721792                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       721792                       # number of overall misses
+system.cpu.icache.overall_misses::total        721792                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   5973239447                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   5973239447                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   5973239447                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   5973239447                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   5973239447                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   5973239447                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     89092336                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     89092336                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     89092336                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     89092336                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     89092336                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     89092336                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.008102                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.008102                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.008102                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.008102                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.008102                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.008102                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8275.571765                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  8275.571765                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  8275.571765                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  8275.571765                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  8275.571765                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  8275.571765                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        62134                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8275.568927                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  8275.568927                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  8275.568927                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  8275.568927                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  8275.568927                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  8275.568927                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        62302                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets           94                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              2178                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              2158                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    28.528007                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    28.870250                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets    31.333333                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         5643                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         5643                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         5643                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         5643                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         5643                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         5643                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       716147                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       716147                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       716147                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       716147                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       716147                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       716147                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   5549831453                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   5549831453                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   5549831453                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   5549831453                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   5549831453                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   5549831453                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         5644                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         5644                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         5644                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         5644                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         5644                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         5644                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       716148                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       716148                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       716148                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       716148                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       716148                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       716148                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   5551358955                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   5551358955                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   5551358955                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   5551358955                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   5551358955                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   5551358955                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.008038                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.008038                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.008038                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.008038                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.008038                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.008038                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7749.570204                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7749.570204                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7749.570204                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  7749.570204                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7749.570204                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  7749.570204                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7751.692325                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7751.692325                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7751.692325                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  7751.692325                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7751.692325                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  7751.692325                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued       404667                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified       404963                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit          238                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued       405270                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified       405390                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit          107                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage        28037                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.prefetcher.pfSpanPage        28146                       # number of prefetches not generated due to page crossing
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         5979.453401                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3840411                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             7285                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           527.166918                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         5987.985640                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3840429                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             7297                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           526.302453                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2575.206017                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2680.661219                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   617.502494                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   106.083671                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.157178                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.163615                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.037689                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.006475                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.364957                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          494                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks  2575.177185                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2680.633084                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   617.470420                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   114.704950                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.157176                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.163613                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.037687                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.007001                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.365478                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022          506                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_blocks::1024         6791                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::0           16                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::1           22                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::2          344                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4          112                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4          124                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           84                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          772                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          128                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          773                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          127                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         5749                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.030151                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.030884                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.414490                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         68225284                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        68225284                       # Number of data accesses
+system.cpu.l2cache.tags.tag_accesses         68225328                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        68225328                       # Number of data accesses
 system.cpu.l2cache.Writeback_hits::writebacks       966339                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total       966339                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       219856                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       219856                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       712305                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       712305                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1312647                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1312647                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       712305                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1532503                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2244808                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       712305                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1532503                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2244808                       # number of overall hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       219874                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       219874                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       712306                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total       712306                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1312645                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1312645                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       712306                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1532519                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2244825                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       712306                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1532519                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2244825                       # number of overall hits
 system.cpu.l2cache.UpgradeReq_misses::cpu.data            1                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total            1                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data          797                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total          797                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data          779                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total          779                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2936                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadCleanReq_misses::total         2936                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data         1057                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total         1057                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data         1059                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total         1059                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst         2936                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         1854                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          4790                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         1838                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          4774                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst         2936                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         1854                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         4790                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         1838                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         4774                       # number of overall misses
 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        23000                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::total        23000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     57082000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     57082000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    199290000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    199290000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     76381000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     76381000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    199290000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    133463000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    332753000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    199290000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    133463000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    332753000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     56035500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     56035500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    200811500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    200811500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     77311000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     77311000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    200811500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    133346500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    334158000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    200811500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    133346500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    334158000                       # number of overall miss cycles
 system.cpu.l2cache.Writeback_accesses::writebacks       966339                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total       966339                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data            2                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total            2                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       220653                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       220653                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       715241                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total       715241                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       715242                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total       715242                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1313704                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total      1313704                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       715241                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       715242                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data      1534357                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2249598                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       715241                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2249599                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       715242                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data      1534357                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2249598                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2249599                       # number of overall (read+write) accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.500000                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.500000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.003612                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.003612                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.003530                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.003530                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.004105                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.004105                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000805                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000805                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000806                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000806                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004105                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.001208                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.002129                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.001198                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.002122                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004105                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.001208                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.002129                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.001198                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.002122                       # miss rate for overall accesses
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        23000                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        23000                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71621.079046                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71621.079046                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67878.065395                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67878.065395                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 72262.062441                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72262.062441                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67878.065395                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71986.515642                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69468.267223                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67878.065395                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71986.515642                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69468.267223                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71932.605905                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71932.605905                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68396.287466                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68396.287466                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73003.777148                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73003.777148                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68396.287466                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72549.782372                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 69995.391705                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68396.287466                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72549.782372                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69995.391705                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1048,145 +1048,145 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data           57                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total           57                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data           48                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total           48                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           13                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total           13                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           33                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::total           33                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst           13                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           90                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total          103                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           81                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           94                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst           13                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           90                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total          103                       # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher        30350                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total        30350                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::cpu.data           81                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           94                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher        30427                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total        30427                       # number of HardPFReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            1                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total            1                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          740                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total          740                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          731                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total          731                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2923                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2923                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         1024                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total         1024                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         1026                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total         1026                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst         2923                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         1764                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         4687                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         1757                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         4680                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2923                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         1764                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher        30350                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        35037                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    188993302                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    188993302                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1757                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher        30427                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        35107                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    180653766                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    180653766                       # number of HardPFReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        17000                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        17000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     50613500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     50613500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    181139000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    181139000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     68370000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     68370000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    181139000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    118983500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    300122500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    181139000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    118983500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    188993302                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    489115802                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     49936000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     49936000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    182660500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    182660500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     69288000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     69288000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    182660500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    119224000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    301884500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    182660500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    119224000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    180653766                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    482538266                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.003354                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.003354                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.003313                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.003313                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004087                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004087                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000779                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000779                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000781                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000781                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004087                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.001150                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.002083                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.001145                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.002080                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004087                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.001150                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.001145                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.015575                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  6227.126919                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  6227.126919                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.015606                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  5937.284846                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  5937.284846                       # average HardPFReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        17000                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        17000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68396.621622                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68396.621622                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61970.236059                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61970.236059                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66767.578125                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66767.578125                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61970.236059                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67450.963719                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64032.963516                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61970.236059                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67450.963719                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  6227.126919                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13959.979507                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68311.901505                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68311.901505                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62490.762915                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62490.762915                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67532.163743                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67532.163743                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62490.762915                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67856.573705                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64505.235043                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62490.762915                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67856.573705                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  5937.284846                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13744.787820                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp       2029851                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2029852                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback       966339                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      1033895                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq        31761                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      1033896                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq        31809                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq            2                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp            2                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       220653                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       220653                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       716147                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       716148                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq      1313704                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2122577                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2122580                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4377763                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6500340                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45775424                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6500343                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45775488                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    160044544                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          205819968                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       32667                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4531746                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.007009                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.083423                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size::total          205820032                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       32715                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      4531796                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.007019                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.083485                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            4499985     99.30%     99.30% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              31761      0.70%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            4499987     99.30%     99.30% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              31809      0.70%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4531746                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     3216331500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        4531796                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     3216332500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          2.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1074485469                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1074486969                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          1.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2301553965                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2301554963                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               6571                       # Transaction distribution
+system.membus.trans_dist::ReadResp               6592                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq                1                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               1                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               740                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              740                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          6571                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14624                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  14624                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       467904                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  467904                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq               731                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              731                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          6592                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14648                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  14648                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       468672                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  468672                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              7312                       # Request fanout histogram
+system.membus.snoop_fanout::samples              7324                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    7312    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    7324    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                7312                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             9348857                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                7324                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             9437390                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           38261400                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           38347412                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
index 95f0885fc679b7462276cf49963b6fc0ecf8d121..85998f5be7f0c7d8576dde0a7731439b7f5c6e77 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.410927                       # Number of seconds simulated
-sim_ticks                                410926760000                       # Number of ticks simulated
-final_tick                               410926760000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.410670                       # Number of seconds simulated
+sim_ticks                                410669815000                       # Number of ticks simulated
+final_tick                               410669815000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  92513                       # Simulator instruction rate (inst/s)
-host_op_rate                                   113896                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               59339858                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 320156                       # Number of bytes of host memory used
-host_seconds                                  6924.97                       # Real time elapsed on the host
+host_inst_rate                                  94058                       # Simulator instruction rate (inst/s)
+host_op_rate                                   115798                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               60293323                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 320128                       # Number of bytes of host memory used
+host_seconds                                  6811.20                       # Real time elapsed on the host
 sim_insts                                   640649299                       # Number of instructions simulated
 sim_ops                                     788724958                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            227008                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           7012480                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher     12950080                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             20189568                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       227008                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          227008                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4245632                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           4245632                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3547                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             109570                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher       202345                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                315462                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66338                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                66338                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               552429                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             17065036                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     31514326                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                49131792                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          552429                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             552429                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          10331846                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               10331846                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          10331846                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              552429                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            17065036                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     31514326                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               59463638                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        315462                       # Number of read requests accepted
-system.physmem.writeReqs                        66338                       # Number of write requests accepted
-system.physmem.readBursts                      315462                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      66338                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 20169664                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     19904                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4239360                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  20189568                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4245632                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      311                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                      69                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs             16                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               19798                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               19540                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               19718                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               19803                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               19742                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               20227                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               19591                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               19445                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               19492                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               19431                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              19416                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              19789                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              19620                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              20020                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              19553                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              19966                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4272                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4105                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4143                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4154                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4243                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4228                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4173                       # Per bank write bursts
+system.physmem.bytes_read::cpu.inst            232448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           7026304                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher     12953152                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             20211904                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       232448                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          232448                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4244928                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           4244928                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3632                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             109786                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher       202393                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                315811                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           66327                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                66327                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               566022                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             17109375                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     31541524                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                49216921                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          566022                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             566022                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          10336596                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               10336596                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          10336596                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              566022                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            17109375                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     31541524                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               59553517                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        315811                       # Number of read requests accepted
+system.physmem.writeReqs                        66327                       # Number of write requests accepted
+system.physmem.readBursts                      315811                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      66327                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 20192576                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     19328                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4239424                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  20211904                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4244928                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      302                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                      58                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs             18                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               19865                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               19533                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               19787                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               19881                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               19767                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               20312                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               19558                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               19499                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               19473                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               19475                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              19453                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              19704                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              19596                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              20052                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              19574                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              19980                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                4265                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4106                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                4140                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                4153                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                4250                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4230                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4174                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               4151                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               4095                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               4093                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               4156                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    410926705500                       # Total gap between requests
+system.physmem.totGap                    410669760500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  315462                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  315811                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  66338                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    125674                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    115954                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     14051                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      6709                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      6515                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      7602                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      8811                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      9422                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      8719                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      4043                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     2949                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     2148                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1569                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      985                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  66327                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    122285                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    120755                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     14364                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      6701                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      6416                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      7563                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      8652                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      9282                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      8107                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      3822                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     2905                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     2145                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1570                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      942                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
@@ -148,48 +148,48 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      601                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      630                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                      952                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     1710                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     2550                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3275                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     3782                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4094                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4378                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4658                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4986                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5206                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5156                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4978                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4056                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      188                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      595                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      609                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                      987                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     1782                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     2648                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     3333                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     3801                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4170                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4413                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4689                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4948                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5154                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5054                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4960                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4217                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4099                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4053                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      133                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                      115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       48                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       88                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       75                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       72                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       48                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       47                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       41                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       39                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        5                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::57                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
@@ -197,118 +197,116 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       136743                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      178.487469                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     128.645908                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     198.261259                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          54158     39.61%     39.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        57478     42.03%     81.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        14696     10.75%     92.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1431      1.05%     93.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1373      1.00%     94.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1481      1.08%     95.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1196      0.87%     96.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1150      0.84%     97.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         3780      2.76%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         136743                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4027                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        66.735038                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       34.718214                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      464.978559                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511            3992     99.13%     99.13% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023           15      0.37%     99.50% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535            4      0.10%     99.60% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-2047            3      0.07%     99.68% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-2559            4      0.10%     99.78% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-3583            1      0.02%     99.80% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3584-4095            1      0.02%     99.83% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4608-5119            2      0.05%     99.88% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::5120-5631            1      0.02%     99.90% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::8192-8703            1      0.02%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::13824-14335            1      0.02%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14848-15359            2      0.05%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4027                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4027                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.448969                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.407245                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.299266                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3382     83.98%     83.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  3      0.07%     84.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                453     11.25%     95.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                103      2.56%     97.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 20      0.50%     98.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 19      0.47%     98.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 10      0.25%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 11      0.27%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  8      0.20%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  5      0.12%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  3      0.07%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  1      0.02%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  1      0.02%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  1      0.02%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  4      0.10%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                  1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  2      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4027                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     8985315314                       # Total ticks spent queuing
-system.physmem.totMemAccLat               14894396564                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1575755000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       28511.14                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples       136666                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      178.756150                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     128.878617                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     198.405742                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          53923     39.46%     39.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        57606     42.15%     81.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        14740     10.79%     92.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1412      1.03%     93.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1397      1.02%     94.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1387      1.01%     95.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1267      0.93%     96.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1142      0.84%     97.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         3792      2.77%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         136666                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4031                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        73.293227                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       34.720611                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      661.085009                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           4010     99.48%     99.48% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047           10      0.25%     99.73% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071            2      0.05%     99.78% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            2      0.05%     99.83% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::5120-6143            1      0.02%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::7168-8191            1      0.02%     99.88% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9216-10239            1      0.02%     99.90% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::11264-12287            1      0.02%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-15359            1      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::19456-20479            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::26624-27647            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            4031                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4031                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.432895                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.394232                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.238105                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3399     84.32%     84.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  3      0.07%     84.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                453     11.24%     95.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                 84      2.08%     97.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 29      0.72%     98.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 17      0.42%     98.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 10      0.25%     99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 13      0.32%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 10      0.25%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  2      0.05%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  3      0.07%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  2      0.05%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  1      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  3      0.07%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                  1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4031                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     8703208249                       # Total ticks spent queuing
+system.physmem.totMemAccLat               14619001999                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1577545000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       27584.66                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  47261.14                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          49.08                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  46334.66                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          49.17                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                          10.32                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       49.13                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       10.33                       # Average system write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       49.22                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       10.34                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.46                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.38                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.08                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.55                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.12                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     218304                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     26331                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   69.27                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  39.73                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1076287.86                       # Average gap between requests
-system.physmem.pageHitRate                      64.14                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  518260680                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  282781125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1231058400                       # Energy for read commands per rank (pJ)
+system.physmem.avgWrQLen                        25.17                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     218486                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     26585                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   69.25                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  40.12                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1074663.50                       # Average gap between requests
+system.physmem.pageHitRate                      64.19                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  519334200                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  283366875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1233694800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                216522720                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            26839254000                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            96516777600                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           161887922250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             287492576775                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              699.632177                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   268678979341                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     13721500000                       # Time in different power states
+system.physmem_0.refreshEnergy            26822471520                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            96824469870                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           161463849000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             287363708985                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              699.756123                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   267972811336                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     13712920000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    128519138159                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    128976939914                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  515334960                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  281184750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1226448600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                212712480                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            26839254000                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            96027774030                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           162316872750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             287419581570                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              699.454538                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   269400106911                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     13721500000                       # Time in different power states
+system.physmem_1.actEnergy                  513679320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  280281375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1226604600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                212718960                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            26822471520                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            96486689295                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           161760147750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             287302592820                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              699.607300                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   268468666587                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     13712920000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    127799659089                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    128482733413                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               233961600                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         161823435                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          15514478                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            121576875                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               108260850                       # Number of BTB hits
+system.cpu.branchPred.lookups               234660907                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         161885632                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          15514558                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            122787051                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               109471469                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             89.047239                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                25036809                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1300056                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             89.155549                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                25674321                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1300177                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -427,84 +425,84 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  673                       # Number of system calls
-system.cpu.numCycles                        821853521                       # number of cpu cycles simulated
+system.cpu.numCycles                        821339631                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           85352108                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1200709266                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   233961600                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          133297659                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     720636600                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                31063377                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 2846                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.icacheStallCycles           85359172                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1200831144                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   234660907                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          135145790                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     720108706                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                31063537                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 2772                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles            31                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles         3322                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 370706156                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                652600                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          821526595                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.826688                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.166658                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles         3327                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 371279487                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                652622                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          821005776                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.826136                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.165203                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                139803220     17.02%     17.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                223204281     27.17%     44.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 98088574     11.94%     56.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                360430520     43.87%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                139284134     16.97%     16.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                223266821     27.19%     44.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 99362992     12.10%     56.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                359091829     43.74%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            821526595                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.284676                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.460977                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                121268240                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             161448420                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 484660246                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              38631680                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               15518009                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             25181996                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 13829                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1248138563                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              39966565                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               15518009                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                178275276                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                80711720                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         210548                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 464319817                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              82491225                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1190650018                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              25545971                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents              24926226                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2267555                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               41530027                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                1673344                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          1225393242                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5812447453                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1358179782                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          40876479                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            821005776                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.285705                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.462040                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                121274951                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             160921163                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 484660075                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              38631496                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               15518091                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             25119096                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 13828                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1248135517                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              39967011                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               15518091                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                178281745                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                80150846                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         211317                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 464319561                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              82524216                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1190646555                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              25420306                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              24957441                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2267221                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               41531798                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                1705173                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          1225452951                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            5812557102                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1358174955                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          40876459                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             874778230                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                350615012                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               7270                       # count of serializing insts renamed
+system.cpu.rename.UndoneMaps                350674721                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               7267                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts           7257                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 108779302                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            366116842                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           236096763                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1776884                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          5334939                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1168558899                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts                 108777970                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            366242931                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           236095379                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1613389                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          5371796                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1168681315                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded               12359                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1017090766                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued          18380245                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       379846300                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1032153355                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                1017114082                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued          18565562                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       379968716                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1032836656                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved            205                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     821526595                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.238050                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.084805                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples     821005776                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.238863                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.084756                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           263868507     32.12%     32.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           227113166     27.65%     59.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           217783209     26.51%     86.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            96635677     11.76%     98.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            16126029      1.96%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           263349245     32.08%     32.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           227125536     27.66%     59.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           217733280     26.52%     86.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            96668881     11.77%     98.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            16128827      1.96%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                   7      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -512,44 +510,44 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       821526595                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       821005776                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                63875827     18.90%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                  18143      0.01%     18.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                63875016     18.90%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                  18146      0.01%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.90% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatCvt            636889      0.19%     19.09% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     19.09% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.09% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.09% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.09% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead              157407577     46.57%     65.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite             116033793     34.33%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead              157510134     46.60%     65.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite             115986364     34.31%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             456370958     44.87%     44.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              5195826      0.51%     45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             456370249     44.87%     44.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              5195831      0.51%     45.38% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     45.38% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     45.38% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     45.38% # Type of FU issued
@@ -573,88 +571,88 @@ system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     45.44% # Ty
 system.cpu.iq.FU_type_0::SimdFloatCmp         3187675      0.31%     45.76% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt         2550148      0.25%     46.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     46.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       11478994      1.13%     47.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       11478996      1.13%     47.14% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.14% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.14% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            322082825     31.67%     78.80% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           215586812     21.20%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            322123387     31.67%     78.81% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           215570268     21.19%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1017090766                       # Type of FU issued
-system.cpu.iq.rate                           1.237557                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   337972229                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.332293                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3150183586                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1504870139                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    934273978                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            61877015                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes           43565815                       # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total             1017114082                       # Type of FU issued
+system.cpu.iq.rate                           1.238360                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   338026549                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.332339                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         3149949023                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1505114950                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    934262178                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            61877028                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           43565833                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses     26152444                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1321252671                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                33810324                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          9960626                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses             1321330304                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                33810327                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          9960611                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    113875904                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads    114001993                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses         1099                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18399                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores    107116267                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18396                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    107114883                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2065816                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         20694                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2065819                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         19975                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               15518009                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                35327000                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 41213                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1168576814                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles               15518091                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                35326945                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 43224                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1168699230                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             366116842                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            236096763                       # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts             366242931                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            236095379                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts               6619                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                    114                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 44806                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18399                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       15437241                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3784654                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             19221895                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             974751722                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             303298002                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          42339044                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewIQFullEvents                     99                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 46833                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18396                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       15437302                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3784553                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             19221855                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             974739392                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             303297512                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          42374690                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                          5556                       # number of nop insts executed
-system.cpu.iew.exec_refs                    497764632                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                150613642                       # Number of branches executed
-system.cpu.iew.exec_stores                  194466630                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.186041                       # Inst execution rate
-system.cpu.iew.wb_sent                      963724701                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     960426422                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 536047355                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 893284415                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    497752889                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                150613606                       # Number of branches executed
+system.cpu.iew.exec_stores                  194455377                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.186768                       # Inst execution rate
+system.cpu.iew.wb_sent                      963712681                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     960414622                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 536046271                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 893280305                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.168610                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.600086                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.169327                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.600087                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       357420349                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       357416983                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           12154                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          15500799                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    770704967                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.023388                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.776993                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          15500881                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    770184473                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.024079                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.777435                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    432077450     56.06%     56.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    174390434     22.63%     78.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     72936884      9.46%     88.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     32898197      4.27%     92.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      8538905      1.11%     93.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     14258273      1.85%     95.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      7269904      0.94%     96.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      5974492      0.78%     97.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     22360428      2.90%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    431571304     56.03%     56.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    174376243     22.64%     78.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     72936565      9.47%     88.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     32893073      4.27%     92.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      8539337      1.11%     93.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     14258396      1.85%     95.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      7274917      0.94%     96.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      5974456      0.78%     97.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     22360182      2.90%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    770704967                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    770184473                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            640654411                       # Number of instructions committed
 system.cpu.commit.committedOps              788730070                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -700,80 +698,80 @@ system.cpu.commit.op_class_0::MemWrite      128980496     16.35%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         788730070                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              22360428                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1894486207                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2343126387                       # The number of ROB writes
-system.cpu.timesIdled                          647317                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          326926                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              22360182                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1893962593                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2343119332                       # The number of ROB writes
+system.cpu.timesIdled                          647411                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          333855                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   640649299                       # Number of Instructions Simulated
 system.cpu.committedOps                     788724958                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.282845                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.282845                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.779518                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.779518                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                995802121                       # number of integer regfile reads
-system.cpu.int_regfile_writes               567908278                       # number of integer regfile writes
+system.cpu.cpi                               1.282043                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.282043                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.780005                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.780005                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                995778090                       # number of integer regfile reads
+system.cpu.int_regfile_writes               567907785                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                  31889840                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                 22959495                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                3794438886                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                384898194                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               715817246                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                3794401386                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                384898061                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               715805814                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                6386808                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           2756184                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.933712                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           414215984                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2756696                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            150.258129                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         256316000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.933712                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999871                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999871                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2756185                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.933524                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           414216512                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2756697                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            150.258266                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         256787000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.933524                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999870                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999870                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          223                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          192                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4           56                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         839346446                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        839346446                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    286293586                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       286293586                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    127907704                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      127907704                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses         839346679                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        839346679                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    286293684                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       286293684                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    127908123                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      127908123                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data         3157                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total          3157                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data         5737                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total         5737                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     414201290                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        414201290                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    414204447                       # number of overall hits
-system.cpu.dcache.overall_hits::total       414204447                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      3034530                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       3034530                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1043773                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1043773                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     414201807                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        414201807                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    414204964                       # number of overall hits
+system.cpu.dcache.overall_hits::total       414204964                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      3034548                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       3034548                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1043354                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1043354                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data          646                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total          646                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      4078303                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4078303                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4078949                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4078949                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  35233063500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  35233063500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   9908998850                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9908998850                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data      4077902                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        4077902                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      4078548                       # number of overall misses
+system.cpu.dcache.overall_misses::total       4078548                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  35018337000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  35018337000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10025314350                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10025314350                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       188000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       188000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  45142062350                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  45142062350                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  45142062350                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  45142062350                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    289328116                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    289328116                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data  45043651350                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  45043651350                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  45043651350                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  45043651350                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    289328232                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    289328232                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data         3803                       # number of SoftPFReq accesses(hits+misses)
@@ -782,72 +780,72 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5740
 system.cpu.dcache.LoadLockedReq_accesses::total         5740                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    418279593                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    418279593                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    418283396                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    418283396                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    418279709                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    418279709                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    418283512                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    418283512                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.010488                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.010488                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.008094                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.008094                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.008091                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.008091                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.169866                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.169866                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000523                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000523                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009750                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009750                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009752                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009752                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11610.715168                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11610.715168                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  9493.442396                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  9493.442396                       # average WriteReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.009749                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009749                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.009751                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009751                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11539.885677                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11539.885677                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  9608.737159                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  9608.737159                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62666.666667                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62666.666667                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 11068.834844                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 11068.834844                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 11067.081827                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 11067.081827                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 11045.790544                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 11045.790544                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 11044.041004                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 11044.041004                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       326278                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       356457                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets            4869                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets            4730                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    67.011296                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    75.360888                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       735190                       # number of writebacks
-system.cpu.dcache.writebacks::total            735190                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       999322                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       999322                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       322910                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       322910                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks       735102                       # number of writebacks
+system.cpu.dcache.writebacks::total            735102                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       999338                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       999338                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       322490                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       322490                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1322232                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1322232                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1322232                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1322232                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2035208                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      2035208                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       720863                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       720863                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      1321828                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1321828                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1321828                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1321828                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2035210                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      2035210                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       720864                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       720864                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          641                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total          641                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2756071                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2756071                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2756712                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2756712                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24098858500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24098858500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5945182850                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5945182850                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      6199500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      6199500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  30044041350                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  30044041350                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  30050240850                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  30050240850                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      2756074                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2756074                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2756715                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2756715                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23819094000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  23819094000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5959479350                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5959479350                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      6004500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      6004500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29778573350                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  29778573350                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29784577850                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  29784577850                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007034                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007034                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005590                       # mshr miss rate for WriteReq accesses
@@ -858,231 +856,231 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006589
 system.cpu.dcache.demand_mshr_miss_rate::total     0.006589                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006591                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.006591                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11840.980627                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11840.980627                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8247.313082                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8247.313082                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  9671.606864                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  9671.606864                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10901.040412                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 10901.040412                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10900.754540                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 10900.754540                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11703.506763                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11703.506763                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8267.134092                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8267.134092                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  9367.394696                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  9367.394696                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10804.707475                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 10804.707475                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10804.373267                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 10804.373267                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           5169094                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.159465                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           365531814                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           5169604                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             70.707894                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle         246618500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.159465                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.998358                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.998358                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           5169482                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.670586                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           366104789                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           5169992                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             70.813415                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle         247000500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.670586                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.997403                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.997403                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          119                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          327                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          326                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         746581864                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        746581864                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    365531869                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       365531869                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     365531869                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        365531869                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    365531869                       # number of overall hits
-system.cpu.icache.overall_hits::total       365531869                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      5174253                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       5174253                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      5174253                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        5174253                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      5174253                       # number of overall misses
-system.cpu.icache.overall_misses::total       5174253                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  41642635922                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  41642635922                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  41642635922                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  41642635922                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  41642635922                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  41642635922                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    370706122                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    370706122                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    370706122                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    370706122                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    370706122                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    370706122                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013958                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.013958                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.013958                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.013958                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.013958                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.013958                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8048.047887                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  8048.047887                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  8048.047887                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  8048.047887                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  8048.047887                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  8048.047887                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        80330                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          136                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              3828                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         747728920                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        747728920                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    366104823                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       366104823                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     366104823                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        366104823                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    366104823                       # number of overall hits
+system.cpu.icache.overall_hits::total       366104823                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      5174632                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       5174632                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      5174632                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        5174632                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      5174632                       # number of overall misses
+system.cpu.icache.overall_misses::total       5174632                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  41647292422                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  41647292422                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  41647292422                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  41647292422                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  41647292422                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  41647292422                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    371279455                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    371279455                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    371279455                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    371279455                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    371279455                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    371279455                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013937                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.013937                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.013937                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.013937                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.013937                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.013937                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8048.358303                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  8048.358303                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  8048.358303                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  8048.358303                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  8048.358303                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  8048.358303                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        80051                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          126                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              3834                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    20.984848                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    27.200000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    20.879238                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    25.200000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4632                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         4632                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         4632                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         4632                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         4632                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         4632                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      5169621                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      5169621                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      5169621                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      5169621                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      5169621                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      5169621                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  39011263436                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  39011263436                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  39011263436                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  39011263436                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  39011263436                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  39011263436                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013945                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013945                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013945                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.013945                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013945                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.013945                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7546.252121                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7546.252121                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7546.252121                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  7546.252121                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7546.252121                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  7546.252121                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4621                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         4621                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         4621                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         4621                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         4621                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         4621                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      5170011                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      5170011                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      5170011                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      5170011                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      5170011                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      5170011                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  39018363435                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  39018363435                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  39018363435                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  39018363435                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  39018363435                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  39018363435                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013925                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013925                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013925                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.013925                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013925                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.013925                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7547.056174                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7547.056174                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7547.056174                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  7547.056174                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7547.056174                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  7547.056174                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued      1349196                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified      1355261                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit         5306                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued      1350243                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified      1354972                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit         4137                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage      4789987                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements           299157                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        16361.680261                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           14361629                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           315521                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            45.517189                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      13425317000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   727.702373                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   130.736374                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  8790.707540                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  6712.533973                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.044415                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007980                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.536542                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.409701                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.998638                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022         6576                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         9788                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1           12                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2          152                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3         1456                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4         4956                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          167                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          226                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2112                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         7189                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.401367                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.597412                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        244356801                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       244356801                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks       735190                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       735190                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       718237                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       718237                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      5166046                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      5166046                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1926561                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1926561                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      5166046                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2644798                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7810844                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      5166046                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2644798                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7810844                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data           16                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total           16                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         2610                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         2610                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3560                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3560                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       109288                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       109288                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3560                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       111898                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        115458                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3560                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       111898                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       115458                       # number of overall misses
+system.cpu.l2cache.prefetcher.pfSpanPage      4790004                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements           299528                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        16361.547684                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           14361788                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           315892                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            45.464235                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      13446572000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks   726.373597                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   128.641683                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  8786.659313                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  6719.873092                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.044334                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007852                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.536295                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.410149                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.998630                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022         6547                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         9817                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1           15                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2          156                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3         1466                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4         4910                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          166                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          236                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2098                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         7222                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.399597                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.599182                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        244366339                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       244366339                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks       735102                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       735102                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       718398                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       718398                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      5166353                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      5166353                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1926489                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1926489                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst      5166353                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2644887                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7811240                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst      5166353                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2644887                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7811240                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data           18                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           18                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         2448                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         2448                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3641                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3641                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       109362                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       109362                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3641                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       111810                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        115451                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3641                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       111810                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       115451                       # number of overall misses
 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        23000                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::total        23000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    191923500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    191923500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    262140500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    262140500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   8522681500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   8522681500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    262140500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   8714605000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   8976745500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    262140500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   8714605000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   8976745500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks       735190                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       735190                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           16                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           16                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       720847                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       720847                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      5169606                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      5169606                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      2035849                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      2035849                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst      5169606                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2756696                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      7926302                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      5169606                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2756696                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      7926302                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    205155000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    205155000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    266848500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    266848500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   8243205000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   8243205000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    266848500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   8448360000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   8715208500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    266848500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   8448360000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   8715208500                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks       735102                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       735102                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           18                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           18                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       720846                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       720846                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      5169994                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total      5169994                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      2035851                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      2035851                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst      5169994                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2756697                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      7926691                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      5169994                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2756697                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      7926691                       # number of overall (read+write) accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.003621                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.003621                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.000689                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.000689                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.053682                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.053682                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.000689                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.040591                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.014566                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.000689                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.040591                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.014566                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  1437.500000                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  1437.500000                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73533.908046                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73533.908046                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73634.971910                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73634.971910                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77983.689884                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77983.689884                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73634.971910                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77879.899551                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77749.012628                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73634.971910                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77879.899551                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77749.012628                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.003396                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.003396                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.000704                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.000704                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.053718                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.053718                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.000704                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.040559                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.014565                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.000704                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.040559                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.014565                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  1277.777778                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  1277.777778                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83805.147059                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83805.147059                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73289.892887                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73289.892887                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75375.404620                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75375.404620                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73289.892887                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75559.967803                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75488.376021                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73289.892887                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75559.967803                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75488.376021                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1091,153 +1089,153 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        66338                       # number of writebacks
-system.cpu.l2cache.writebacks::total            66338                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1216                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total         1216                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           13                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total           13                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data         1112                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total         1112                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           13                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data         2328                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total         2341                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           13                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data         2328                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total         2341                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         8918                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total         8918                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       202421                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total       202421                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           16                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           16                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1394                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1394                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3547                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3547                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       108176                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       108176                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3547                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       109570                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       113117                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3547                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       109570                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       202421                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       315538                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  17045778133                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  17045778133                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       268500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       268500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    123342500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    123342500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    239801000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    239801000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   7820358000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   7820358000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    239801000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7943700500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   8183501500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    239801000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7943700500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  17045778133                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  25229279633                       # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks        66327                       # number of writebacks
+system.cpu.l2cache.writebacks::total            66327                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1069                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total         1069                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            9                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            9                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          955                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total          955                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            9                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data         2024                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total         2033                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            9                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data         2024                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total         2033                       # number of overall MSHR hits
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         8960                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         8960                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       202470                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total       202470                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           18                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           18                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1379                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1379                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3632                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3632                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       108407                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       108407                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3632                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       109786                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       113418                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3632                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       109786                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       202470                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       315888                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  16906807287                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  16906807287                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       302000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       302000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    142927500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    142927500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    244477000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    244477000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   7547443000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   7547443000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    244477000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7690370500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   7934847500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    244477000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7690370500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  16906807287                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  24841654787                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001934                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001934                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.000686                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.000686                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.053136                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.053136                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.000686                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.039747                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.014271                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.000686                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.039747                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001913                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001913                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.000703                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.000703                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.053249                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.053249                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.000703                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.039825                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.014308                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.000703                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.039825                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.039809                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84209.534253                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84209.534253                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16781.250000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16781.250000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88480.989957                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88480.989957                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67606.709896                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67606.709896                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72292.911552                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72292.911552                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67606.709896                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72498.863740                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72345.460894                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67606.709896                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72498.863740                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84209.534253                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79956.390777                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.039851                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83502.777137                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 83502.777137                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16777.777778                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16777.777778                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 103645.757796                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 103645.757796                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67311.949339                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67311.949339                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69621.362089                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69621.362089                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67311.949339                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70048.735722                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69961.095241                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67311.949339                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70048.735722                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83502.777137                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78640.704259                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp       7205469                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       801528                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      6778838                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       266094                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           16                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           16                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       720847                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       720847                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      5169621                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      2035849                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     15507443                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7626416                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          23133859                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    330854720                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    223480704                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          554335424                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      565266                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     16416862                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.034431                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.182334                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp       7205861                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       801429                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      6779490                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       246291                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           18                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           18                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       720846                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       720846                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      5170011                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      2035851                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     15508607                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7626218                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          23134825                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    330879552                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    223475136                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          554354688                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      545836                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     16398212                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.033285                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.179381                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           15851611     96.56%     96.56% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             565251      3.44%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           15852393     96.67%     96.67% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             545819      3.33%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       16416862                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     8660995500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       16398212                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     8661298500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          2.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    7754456946                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    7755038952                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          1.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    4135063976                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    4135066975                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             314068                       # Transaction distribution
-system.membus.trans_dist::Writeback             66338                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           232219                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq               16                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              16                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1394                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1394                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        314068                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       929513                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 929513                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     24435200                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                24435200                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp             314432                       # Transaction distribution
+system.membus.trans_dist::Writeback             66327                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           232586                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq               18                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              18                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1379                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1379                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        314432                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       930571                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 930571                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     24456832                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                24456832                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            614035                       # Request fanout histogram
+system.membus.snoop_fanout::samples            614742                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  614035    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  614742    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              614035                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           967133123                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              614742                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           978145707                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1648308021                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1654146686                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
index 54ac67971e6ebdf7d88ad48d69ed729242f66205..c156cc0a5015351172be801cb55ed331cad930c1 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.033295                       # Number of seconds simulated
-sim_ticks                                 33294994000                       # Number of ticks simulated
-final_tick                                33294994000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.033333                       # Number of seconds simulated
+sim_ticks                                 33333078000                       # Number of ticks simulated
+final_tick                                33333078000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 125667                       # Simulator instruction rate (inst/s)
-host_op_rate                                   160714                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               59007684                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 325068                       # Number of bytes of host memory used
-host_seconds                                   564.25                       # Real time elapsed on the host
+host_inst_rate                                 125008                       # Simulator instruction rate (inst/s)
+host_op_rate                                   159871                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               58765299                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 325044                       # Number of bytes of host memory used
+host_seconds                                   567.22                       # Real time elapsed on the host
 sim_insts                                    70907630                       # Number of instructions simulated
 sim_ops                                      90682585                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            579648                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           2508288                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher      6196352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9284288                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       579648                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          579648                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6263808                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6263808                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               9057                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              39192                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher        96818                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                145067                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           97872                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                97872                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             17409464                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             75335289                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher    186104614                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               278849367                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        17409464                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           17409464                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         188130624                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              188130624                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         188130624                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            17409464                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            75335289                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher    186104614                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              466979991                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        145067                       # Number of read requests accepted
-system.physmem.writeReqs                        97872                       # Number of write requests accepted
-system.physmem.readBursts                      145067                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      97872                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  9276928                       # Total number of bytes read from DRAM
+system.physmem.bytes_read::cpu.inst            591360                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           2521216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher      6195328                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              9307904                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       591360                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          591360                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6264192                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6264192                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               9240                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              39394                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher        96802                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                145436                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           97878                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                97878                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             17740936                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             75637059                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher    185861264                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               279239259                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        17740936                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           17740936                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         187927200                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              187927200                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         187927200                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            17740936                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            75637059                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher    185861264                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              467166458                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        145436                       # Number of read requests accepted
+system.physmem.writeReqs                        97878                       # Number of write requests accepted
+system.physmem.readBursts                      145436                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      97878                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  9300544                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                      7360                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6262080                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   9284288                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6263808                       # Total written bytes from the system interface side
+system.physmem.bytesWritten                   6263104                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   9307904                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6264192                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                      115                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              6                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9133                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                9402                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                9189                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                9501                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                9688                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9749                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9050                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                9017                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                9142                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                8554                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               8859                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               8689                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               8621                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               8707                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               8654                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               8997                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5994                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6239                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6113                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6223                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6099                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6360                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6100                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5988                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5999                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6164                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6223                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               5911                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6098                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6094                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6156                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6084                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                9151                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                9416                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                9264                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                9524                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                9728                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9774                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9086                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                9016                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                9170                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                8620                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               8843                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               8715                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               8697                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               8672                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               8700                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               8945                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6002                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6227                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6156                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6165                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6066                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6338                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6039                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6021                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                6032                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6183                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6239                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               5928                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6101                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6124                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6211                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6029                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     33294791000                       # Total gap between requests
+system.physmem.totGap                     33332792500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  145067                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  145436                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  97872                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     42425                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     52688                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     16531                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      9335                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      6069                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      5279                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      4636                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4301                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3567                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        90                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  97878                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     41531                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     55128                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     14558                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     10364                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      5987                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      5214                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      4599                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4263                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3539                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        86                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       42                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                        6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
@@ -148,30 +148,30 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1878                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     2564                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3428                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4425                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5268                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5691                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5944                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6288                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6608                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7072                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7612                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8290                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     9213                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7674                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6888                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6385                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1148                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1184                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     1918                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     2582                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     3353                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4290                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5332                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5723                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5988                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6224                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6557                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7007                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7623                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8324                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     9140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7906                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6877                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6327                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                      206                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
@@ -197,102 +197,102 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        88605                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      175.366717                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     110.599846                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     238.987527                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          52022     58.71%     58.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        22627     25.54%     84.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4475      5.05%     89.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1626      1.84%     91.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1127      1.27%     92.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          853      0.96%     93.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          741      0.84%     94.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          771      0.87%     95.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4363      4.92%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          88605                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples        88939                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      174.992388                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     110.439382                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     239.025071                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          52267     58.77%     58.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        22760     25.59%     84.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4436      4.99%     89.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1732      1.95%     91.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1066      1.20%     92.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          777      0.87%     93.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          661      0.74%     94.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          818      0.92%     95.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4422      4.97%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          88939                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples          5911                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        24.519032                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       21.016952                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      186.911555                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        24.584503                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       21.105941                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      187.238550                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::0-511            5910     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::14336-14847            1      0.02%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::total            5911                       # Reads before turning the bus around for writes
 system.physmem.wrPerTurnAround::samples          5911                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.553037                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.510340                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.264183                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               4718     79.82%     79.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 30      0.51%     80.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                754     12.76%     93.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                178      3.01%     96.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 93      1.57%     97.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 63      1.07%     98.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 39      0.66%     99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 18      0.30%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 13      0.22%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  4      0.07%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.555744                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.512900                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.266741                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               4704     79.58%     79.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 36      0.61%     80.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                781     13.21%     93.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                157      2.66%     96.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 88      1.49%     97.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 64      1.08%     98.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 47      0.80%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 14      0.24%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 17      0.29%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  2      0.03%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::26                  1      0.02%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total            5911                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     7210112096                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9927962096                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    724760000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       49741.38                       # Average queueing delay per DRAM burst
+system.physmem.totQLat                     7028707749                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9753476499                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    726605000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       48366.77                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  68491.38                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         278.63                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         188.08                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      278.85                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      188.13                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  67116.77                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         279.02                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         187.89                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      279.24                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      187.93                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           3.65                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       2.18                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      1.47                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.60                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.54                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     117862                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     36326                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.31                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  37.12                       # Row buffer hit rate for writes
-system.physmem.avgGap                       137050.00                       # Average gap between requests
-system.physmem.pageHitRate                      63.50                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  341636400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  186408750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 582823800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                318271680                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             2174602560                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            11786161320                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy             9637821000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              25027725510                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              751.712810                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    15936534744                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1111760000                       # Time in different power states
+system.physmem.avgRdQLen                         1.59                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.82                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     118079                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     36164                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.25                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  36.95                       # Row buffer hit rate for writes
+system.physmem.avgGap                       136994.96                       # Average gap between requests
+system.physmem.pageHitRate                      63.42                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  343934640                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  187662750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 584680200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                317610720                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             2177145360                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            11782825965                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             9664105500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              25057965135                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              751.742046                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    15979863754                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1112800000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     16245984006                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     16240286246                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  328217400                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  179086875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 547723800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                315763920                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             2174602560                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            11208088125                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            10144902750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              24898385430                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              747.828055                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    16783464024                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1111760000                       # Time in different power states
+system.physmem_1.actEnergy                  328444200                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  179210625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 548823600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                316528560                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             2177145360                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            11298113640                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            10089291750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              24937557735                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              748.129809                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    16691408912                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1112800000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     15399360476                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     15528741088                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                17206050                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11517760                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            648066                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9347785                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7673761                       # Number of BTB hits
+system.cpu.branchPred.lookups                17206633                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11518078                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            648316                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9346074                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7675410                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             82.091758                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1873139                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             101558                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             82.124430                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1873047                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             101552                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -411,129 +411,129 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                         66589989                       # number of cpu cycles simulated
+system.cpu.numCycles                         66666157                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles            5006781                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       88183966                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    17206050                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9546900                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      60089478                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1322083                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 6754                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.icacheStallCycles            5010938                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       88191821                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    17206633                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9548457                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      60137734                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1322663                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 6978                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles            23                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles        13752                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  22762089                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 69210                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           65777829                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.696584                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.296287                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles        13644                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  22767110                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 69105                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           65830648                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.695372                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.296604                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 20002417     30.41%     30.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  8264821     12.56%     42.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  9199012     13.98%     56.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 28311579     43.04%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 20050738     30.46%     30.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  8265796     12.56%     43.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  9200690     13.98%     56.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 28313424     43.01%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             65777829                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.258388                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.324283                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                  8581179                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              19502182                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  31574906                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               5627602                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 491960                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3179377                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                170933                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              101404474                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3045182                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 491960                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 13335070                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 5313056                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         801397                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  32234531                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              13601815                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               99199856                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                982546                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               3844821                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  62523                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                4317608                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                5297882                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           103921297                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             457696388                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        115410759                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total             65830648                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.258101                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.322887                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                  8588438                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              19545167                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  31574635                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               5630215                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 492193                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3180012                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                171001                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              101409826                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3046686                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 492193                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 13345278                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 5337889                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         804170                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  32233077                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              13618041                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               99203464                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                983266                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               3848076                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  66970                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                4316860                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                5302934                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           103925476                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             457709098                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        115412648                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups               550                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              93629226                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 10292071                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              18659                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          18651                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12693629                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             24321623                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            21992796                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1398027                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2340833                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   98163899                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               34521                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  94893533                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            694347                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         7515835                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     20236855                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            735                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      65777829                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.442637                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.149664                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 10296250                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              18661                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          18653                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12703257                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             24321959                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21992794                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1408685                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2344134                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   98166936                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               34525                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  94895750                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            693672                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         7518876                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     20249831                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            739                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      65830648                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.441513                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.149732                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            17511633     26.62%     26.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            17428256     26.50%     53.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            17102675     26.00%     79.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            11682123     17.76%     96.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             2052152      3.12%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 990      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            17559708     26.67%     26.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            17428340     26.47%     53.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            17111473     25.99%     79.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            11681013     17.74%     96.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             2049145      3.11%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 969      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        65777829                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        65830648                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 6715699     22.40%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     38      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               11201748     37.36%     59.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              12068794     40.25%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 6713649     22.39%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     39      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     22.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               11199453     37.36%     59.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              12066123     40.25%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              49496640     52.16%     52.16% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                89875      0.09%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              49496629     52.16%     52.16% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                89874      0.09%     52.25% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.25% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                  31      0.00%     52.25% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.25% # Type of FU issued
@@ -561,84 +561,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     52.25% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.25% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.25% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             24065423     25.36%     77.62% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21241557     22.38%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             24067515     25.36%     77.62% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            21241694     22.38%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               94893533                       # Type of FU issued
-system.cpu.iq.rate                           1.425042                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    29986279                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.315999                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          286245314                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         105725496                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     93465397                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total               94895750                       # Type of FU issued
+system.cpu.iq.rate                           1.423447                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    29979264                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.315918                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          286294877                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         105731606                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     93465380                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                 207                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                248                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           57                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              124879694                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses              124874896                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                     118                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1364211                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads          1362273                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1455361                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1455697                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses         2068                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        11748                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1437058                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        11776                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1437056                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       140354                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        182528                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       140882                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        184054                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 491960                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  620291                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                463716                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            98208276                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                 492193                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  620956                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                467696                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            98211315                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              24321623                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             21992796                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              18601                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   1628                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                459155                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          11748                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         302696                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       221540                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               524236                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              93976140                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              23758122                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            917393                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              24321959                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21992794                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              18605                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   1621                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                463138                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          11776                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         302825                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       221559                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               524384                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              93978064                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              23759823                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            917686                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          9856                       # number of nop insts executed
-system.cpu.iew.exec_refs                     44743070                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14251776                       # Number of branches executed
-system.cpu.iew.exec_stores                   20984948                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.411265                       # Inst execution rate
-system.cpu.iew.wb_sent                       93586994                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      93465454                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  44981756                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  76565949                       # num instructions consuming a value
+system.cpu.iew.exec_nop                          9854                       # number of nop insts executed
+system.cpu.iew.exec_refs                     44744798                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14251807                       # Number of branches executed
+system.cpu.iew.exec_stores                   20984975                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.409682                       # Inst execution rate
+system.cpu.iew.wb_sent                       93587077                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      93465437                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  44977935                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  76555853                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.403596                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.587490                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.401992                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.587518                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         6535729                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts         6538600                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            478985                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     64719651                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.401246                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.164864                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            479178                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     64771963                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.400114                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.164673                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     31116285     48.08%     48.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     16809912     25.97%     74.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4342534      6.71%     80.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4161990      6.43%     87.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1938865      3.00%     90.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1263903      1.95%     92.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       739138      1.14%     93.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       578808      0.89%     94.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      3768216      5.82%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     31176340     48.13%     48.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     16804620     25.94%     74.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4339366      6.70%     80.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4157771      6.42%     87.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1944331      3.00%     90.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1263277      1.95%     92.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       736800      1.14%     93.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       578701      0.89%     94.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      3770757      5.82%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     64719651                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     64771963                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             70913182                       # Number of instructions committed
 system.cpu.commit.committedOps               90688137                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -684,386 +684,386 @@ system.cpu.commit.op_class_0::MemWrite       20555738     22.67%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          90688137                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               3768216                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    158150002                       # The number of ROB reads
-system.cpu.rob.rob_writes                   195507605                       # The number of ROB writes
-system.cpu.timesIdled                           23773                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          812160                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               3770757                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    158202644                       # The number of ROB reads
+system.cpu.rob.rob_writes                   195513856                       # The number of ROB writes
+system.cpu.timesIdled                           23729                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          835509                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    70907630                       # Number of Instructions Simulated
 system.cpu.committedOps                      90682585                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.939109                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.939109                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.064839                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.064839                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                102273698                       # number of integer regfile reads
-system.cpu.int_regfile_writes                56793498                       # number of integer regfile writes
+system.cpu.cpi                               0.940183                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.940183                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.063623                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.063623                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                102275291                       # number of integer regfile reads
+system.cpu.int_regfile_writes                56793629                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        36                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                       21                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 346096996                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 38804962                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                44209976                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                 346102642                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 38804681                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                44209969                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            485041                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           510.740827                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40418511                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            485553                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             83.242223                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         152851500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   510.740827                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997541                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997541                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            485047                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           510.741433                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40420740                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            485559                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             83.245785                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         153056500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   510.741433                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997542                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997542                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          454                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          84611501                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         84611501                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     21495962                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21495962                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18831064                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18831064                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        60188                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         60188                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        15352                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        15352                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses          84615723                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         84615723                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     21498446                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21498446                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18830779                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18830779                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        60221                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         60221                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        15346                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        15346                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      40327026                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         40327026                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     40387214                       # number of overall hits
-system.cpu.dcache.overall_hits::total        40387214                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       556411                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        556411                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1018837                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1018837                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data        68667                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total        68667                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data          574                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total          574                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1575248                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1575248                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1643915                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1643915                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   8968261000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   8968261000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  14556255401                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  14556255401                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      4964500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total      4964500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  23524516401                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  23524516401                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  23524516401                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  23524516401                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22052373                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22052373                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data      40329225                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         40329225                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     40389446                       # number of overall hits
+system.cpu.dcache.overall_hits::total        40389446                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       556041                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        556041                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1019122                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1019122                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data        68628                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total        68628                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data          580                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total          580                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1575163                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1575163                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1643791                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1643791                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   8960046000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   8960046000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  14598887903                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  14598887903                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      5237000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total      5237000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  23558933903                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  23558933903                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  23558933903                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  23558933903                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22054487                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22054487                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       128855                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       128855                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       128849                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       128849                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15926                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        15926                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     41902274                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     41902274                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42031129                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42031129                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025231                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.025231                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.051327                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.051327                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.532901                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.532901                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.036042                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.036042                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.037593                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037593                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.039112                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.039112                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16118.051225                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16118.051225                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14287.128757                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 14287.128757                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  8648.954704                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  8648.954704                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14933.849401                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14933.849401                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14310.056421                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14310.056421                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs           45                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      3094334                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 8                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          130016                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.625000                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    23.799640                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     41904388                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     41904388                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42033237                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42033237                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025212                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.025212                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.051341                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.051341                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.532623                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.532623                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.036418                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.036418                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.037589                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.037589                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.039107                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.039107                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16114.002385                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16114.002385                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14324.965905                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 14324.965905                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  9029.310345                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  9029.310345                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14956.505392                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14956.505392                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14332.073787                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14332.073787                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs           55                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      3099418                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 6                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          130265                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.166667                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    23.793175                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       256956                       # number of writebacks
-system.cpu.dcache.writebacks::total            256956                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       256971                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       256971                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       870307                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       870307                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          574                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total          574                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1127278                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1127278                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1127278                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1127278                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       299440                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       299440                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       261117                       # number of writebacks
+system.cpu.dcache.writebacks::total            261117                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       256598                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       256598                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       870592                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       870592                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          580                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total          580                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1127190                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1127190                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1127190                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1127190                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       299443                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       299443                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       148530                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total       148530                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        37596                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total        37596                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       447970                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       447970                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       485566                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       485566                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3182608500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   3182608500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2345597960                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2345597960                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   2017960000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   2017960000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5528206460                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   5528206460                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7546166460                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   7546166460                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013579                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013579                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        37597                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total        37597                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       447973                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       447973                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       485570                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       485570                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3193306500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3193306500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2352659965                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2352659965                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   2013580000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   2013580000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5545966465                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   5545966465                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7559546465                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   7559546465                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013577                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013577                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.007483                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.007483                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.291770                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.291770                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.010691                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.010691                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.011553                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.011553                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10628.534932                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10628.534932                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15792.082138                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15792.082138                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53674.859028                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53674.859028                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12340.572940                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12340.572940                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15540.969631                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 15540.969631                       # average overall mshr miss latency
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.291791                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.291791                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.010690                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.010690                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.011552                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.011552                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10664.154781                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10664.154781                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15839.628122                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15839.628122                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53556.932734                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53556.932734                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12380.135555                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 12380.135555                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15568.396863                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 15568.396863                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            322718                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.301604                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            22427944                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            323227                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             69.387594                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle        1102167500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.301604                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.996683                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.996683                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
+system.cpu.icache.tags.replacements            322838                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.295109                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            22432857                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            323350                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             69.376394                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle        1105263500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.295109                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.996670                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.996670                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           59                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2            7                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          347                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           57                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          353                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4            7                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          45847164                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         45847164                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     22427950                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        22427950                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      22427950                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         22427950                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     22427950                       # number of overall hits
-system.cpu.icache.overall_hits::total        22427950                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       334012                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        334012                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       334012                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         334012                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       334012                       # number of overall misses
-system.cpu.icache.overall_misses::total        334012                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   3359547390                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   3359547390                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   3359547390                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   3359547390                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   3359547390                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   3359547390                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     22761962                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     22761962                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     22761962                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     22761962                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     22761962                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     22761962                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014674                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.014674                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.014674                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.014674                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.014674                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.014674                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10058.163749                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 10058.163749                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 10058.163749                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 10058.163749                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 10058.163749                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 10058.163749                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs       273191                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          314                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs             16668                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    16.390149                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          157                       # average number of cycles each access was blocked
+system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          45857337                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         45857337                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     22432857                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        22432857                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      22432857                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         22432857                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     22432857                       # number of overall hits
+system.cpu.icache.overall_hits::total        22432857                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       334131                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        334131                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       334131                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         334131                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       334131                       # number of overall misses
+system.cpu.icache.overall_misses::total        334131                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   3372669901                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   3372669901                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   3372669901                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   3372669901                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   3372669901                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   3372669901                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     22766988                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     22766988                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     22766988                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     22766988                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     22766988                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     22766988                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014676                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.014676                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.014676                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.014676                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.014676                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.014676                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10093.855108                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 10093.855108                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 10093.855108                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 10093.855108                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 10093.855108                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 10093.855108                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs       274760                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          147                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs             16673                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    16.479338                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets           49                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        10772                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        10772                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        10772                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        10772                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        10772                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        10772                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       323240                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       323240                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       323240                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       323240                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       323240                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       323240                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   3075719938                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   3075719938                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   3075719938                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   3075719938                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   3075719938                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   3075719938                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014201                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014201                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014201                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.014201                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014201                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.014201                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9515.282570                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  9515.282570                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9515.282570                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  9515.282570                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9515.282570                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  9515.282570                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        10770                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        10770                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        10770                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        10770                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        10770                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        10770                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       323361                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       323361                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       323361                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       323361                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       323361                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       323361                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   3089767447                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   3089767447                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   3089767447                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   3089767447                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   3089767447                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   3089767447                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014203                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014203                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014203                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.014203                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014203                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.014203                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9555.164188                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  9555.164188                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9555.164188                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  9555.164188                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9555.164188                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  9555.164188                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued       823311                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified       826037                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit         2394                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued       824514                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified       825954                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit         1262                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage        78819                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements           129183                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        16078.827633                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1332410                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           145465                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             9.159660                       # Average number of references to valid blocks.
+system.cpu.l2cache.prefetcher.pfSpanPage        78678                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements           129552                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        16077.997606                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1332384                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           145834                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             9.136306                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 12584.053825                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1451.251559                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1933.402514                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   110.119734                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.768070                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.088577                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.118006                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.006721                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.981374                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 12589.252408                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1431.737238                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1938.355630                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   118.652331                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.768387                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.087386                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.118308                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.007242                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.981323                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1022           37                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        16245                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2            7                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3           17                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4            5                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          156                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2635                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12009                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          573                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          872                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2            3                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3           22                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4            4                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2643                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12025                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          539                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          883                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1022     0.002258                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.991516                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         24881143                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        24881143                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks       256956                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       256956                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data            7                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            7                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       137103                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       137103                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       314121                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       314121                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       305949                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       305949                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       314121                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       443052                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          757173                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       314121                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       443052                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         757173                       # number of overall hits
+system.cpu.l2cache.tags.tag_accesses         24885703                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        24885703                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks       261117                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       261117                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data            5                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total            5                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       137140                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       137140                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       314068                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total       314068                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       305844                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       305844                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       314068                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       442984                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          757052                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       314068                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       442984                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         757052                       # number of overall hits
 system.cpu.l2cache.UpgradeReq_misses::cpu.data            6                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total            6                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data        11464                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        11464                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         9103                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         9103                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        31037                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        31037                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         9103                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        42501                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         51604                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         9103                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        42501                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        51604                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1228965000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   1228965000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    707735000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    707735000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2684182500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   2684182500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    707735000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   3913147500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   4620882500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    707735000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   3913147500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   4620882500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks       256956                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       256956                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           13                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           13                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       148567                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       148567                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       323224                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total       323224                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       336986                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       336986                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       323224                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       485553                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       808777                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       323224                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       485553                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       808777                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.461538                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.461538                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.077164                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.077164                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.028163                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.028163                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.092102                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.092102                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.028163                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.087531                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.063805                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.028163                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.087531                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.063805                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 107202.110956                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 107202.110956                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77747.445897                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77747.445897                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86483.310243                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86483.310243                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77747.445897                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92071.892426                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 89545.044958                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77747.445897                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92071.892426                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 89545.044958                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_misses::cpu.data        11428                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        11428                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         9278                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         9278                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        31147                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        31147                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         9278                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        42575                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         51853                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         9278                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        42575                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        51853                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1235483500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   1235483500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    721965000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    721965000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2691191000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   2691191000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    721965000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   3926674500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   4648639500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    721965000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   3926674500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   4648639500                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks       261117                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       261117                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           11                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           11                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       148568                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       148568                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       323346                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total       323346                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       336991                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       336991                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       323346                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       485559                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       808905                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       323346                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       485559                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       808905                       # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.545455                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.545455                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.076921                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.076921                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.028694                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.028694                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.092427                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.092427                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.028694                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.087682                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.064103                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.028694                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.087682                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.064103                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 108110.211761                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 108110.211761                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77814.723001                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77814.723001                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86402.895945                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86402.895945                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77814.723001                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92229.583089                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 89650.348099                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77814.723001                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92229.583089                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 89650.348099                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1072,153 +1072,153 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        97872                       # number of writebacks
-system.cpu.l2cache.writebacks::total            97872                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3181                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total         3181                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           46                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total           46                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          128                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total          128                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           46                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data         3309                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total         3355                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           46                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data         3309                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total         3355                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         3506                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total         3506                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       112459                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total       112459                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks        97878                       # number of writebacks
+system.cpu.l2cache.writebacks::total            97878                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3042                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total         3042                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           38                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total           38                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          139                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total          139                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           38                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data         3181                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total         3219                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           38                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data         3181                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total         3219                       # number of overall MSHR hits
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         3552                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         3552                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       112510                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total       112510                       # number of HardPFReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            6                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total            6                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         8283                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         8283                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         9057                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         9057                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        30909                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        30909                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         9057                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        39192                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        48249                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         9057                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        39192                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       112459                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       160708                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  10889744040                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  10889744040                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       101500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       101500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    639425500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    639425500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    650223000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    650223000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2490483000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2490483000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    650223000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3129908500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   3780131500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    650223000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3129908500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  10889744040                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  14669875540                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         8386                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         8386                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         9240                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         9240                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        31008                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        31008                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         9240                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        39394                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        48634                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         9240                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        39394                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       112510                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       161144                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  10641572084                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  10641572084                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       100500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       100500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    677751000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    677751000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    663843000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    663843000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2494831000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2494831000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    663843000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3172582000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   3836425000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    663843000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3172582000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  10641572084                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  14477997084                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.461538                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.461538                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.055753                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.055753                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.028021                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.028021                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.091722                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.091722                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.028021                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.080716                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.059657                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.028021                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.080716                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.545455                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.545455                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.056446                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.056446                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.028576                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.028576                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.092014                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.092014                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.028576                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.081131                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.060123                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.028576                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.081131                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.198705                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96833.015054                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 96833.015054                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16916.666667                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16916.666667                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77197.331885                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77197.331885                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71792.315336                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71792.315336                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80574.686984                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80574.686984                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71792.315336                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79860.902735                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78346.318058                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71792.315336                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79860.902735                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96833.015054                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91282.795754                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.199213                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94583.344449                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 94583.344449                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        16750                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        16750                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80819.341760                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80819.341760                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71844.480519                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71844.480519                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80457.656089                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80457.656089                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71844.480519                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80534.649947                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78883.599951                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71844.480519                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80534.649947                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94583.344449                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89845.089386                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp        660226                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       354828                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       502259                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       152780                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           13                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           13                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       148567                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       148567                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       323240                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       336986                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       938639                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1406861                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2345500                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     20686336                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     47520576                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           68206912                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      281979                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1898528                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.148517                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.355611                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp        660352                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       358995                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       498597                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       141207                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           11                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           11                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       148568                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       148568                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       323361                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       336991                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       938997                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1406890                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2345887                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     20694144                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     47787264                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           68481408                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      270774                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1887575                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.143443                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.350524                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            1616565     85.15%     85.15% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             281963     14.85%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            1616816     85.66%     85.66% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             270759     14.34%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1898528                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     1065238500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1887575                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     1069525000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          3.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     485020678                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     485192198                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          1.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     728403365                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     728416355                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             136784                       # Transaction distribution
-system.membus.trans_dist::Writeback             97872                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            30200                       # Transaction distribution
+system.membus.trans_dist::ReadResp             137050                       # Transaction distribution
+system.membus.trans_dist::Writeback             97878                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            30539                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq                6                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               6                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              8283                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             8283                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        136784                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       418218                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 418218                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15548096                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                15548096                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq              8386                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             8386                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        137050                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       419301                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 419301                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15572096                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                15572096                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            273145                       # Request fanout histogram
+system.membus.snoop_fanout::samples            273859                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  273145    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  273859    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              273145                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           717072511                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              273859                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           740935905                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          756625908                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          757820949                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              2.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
index 493c10cfc404f6e2391127b1486c05a83cdbeb40..d6d64bb1da4ddd7c8a3c1af12208cfd20f581f35 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.770277                       # Number of seconds simulated
-sim_ticks                                770277033000                       # Number of ticks simulated
-final_tick                               770277033000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.770368                       # Number of seconds simulated
+sim_ticks                                770368138000                       # Number of ticks simulated
+final_tick                               770368138000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 139677                       # Simulator instruction rate (inst/s)
-host_op_rate                                   150481                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               69657391                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 313196                       # Number of bytes of host memory used
-host_seconds                                 11058.08                       # Real time elapsed on the host
+host_inst_rate                                 139680                       # Simulator instruction rate (inst/s)
+host_op_rate                                   150484                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               69667014                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 312136                       # Number of bytes of host memory used
+host_seconds                                 11057.86                       # Real time elapsed on the host
 sim_insts                                  1544563024                       # Number of instructions simulated
 sim_ops                                    1664032416                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             66048                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         238802560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher     63353600                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            302222208                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        66048                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           66048                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    104930816                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         104930816                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               1032                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            3731290                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher       989900                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               4722222                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1639544                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1639544                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                85746                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            310021654                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     82247811                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               392355211                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           85746                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              85746                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         136224776                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              136224776                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         136224776                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               85746                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           310021654                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     82247811                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              528579987                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       4722222                       # Number of read requests accepted
-system.physmem.writeReqs                      1639544                       # Number of write requests accepted
-system.physmem.readBursts                     4722222                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1639544                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                301770432                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    451776                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 104928448                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 302222208                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              104930816                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     7059                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                      16                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bytes_read::cpu.inst             65792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         238160448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher     63905024                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            302131264                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        65792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           65792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    104870272                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         104870272                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               1028                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            3721257                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher       998516                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               4720801                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1638598                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1638598                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                85403                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            309151477                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     82953877                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               392190758                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           85403                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              85403                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         136130074                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              136130074                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         136130074                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               85403                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           309151477                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     82953877                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              528320833                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       4720801                       # Number of read requests accepted
+system.physmem.writeReqs                      1638598                       # Number of write requests accepted
+system.physmem.readBursts                     4720801                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1638598                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                301683008                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                    448256                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 104867648                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 302131264                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              104870272                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     7004                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                      12                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              297173                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              295012                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              289245                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              293018                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              289731                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              289594                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              284433                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              281274                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              297880                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              304149                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             295533                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             302217                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             302962                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             302377                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             297334                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             293231                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              104274                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              102166                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               99582                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              100201                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               99226                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               98958                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              102876                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              104542                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              105498                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              104632                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             102325                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             102766                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             102939                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             102535                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             104418                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             102569                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              296472                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              294660                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              288575                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              292960                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              290749                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              289530                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              284828                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              280913                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              297084                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              304004                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             295272                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             301446                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             303554                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             302544                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             297853                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             293353                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              103842                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              101847                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               99335                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              100097                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               99287                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               99035                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              102669                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              104576                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              105230                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              104522                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             102176                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             103126                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             103102                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             102725                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             104361                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             102627                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    770276886500                       # Total gap between requests
+system.physmem.totGap                    770367991500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 4722222                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 4720801                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1639544                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   2779707                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                   1048806                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    331545                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    232118                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    150885                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     83926                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     38903                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     23907                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     18114                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      4239                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1660                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      740                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      412                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      195                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1638598                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   2785137                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                   1045602                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    327608                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    232677                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    151173                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                     83865                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                     38451                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     23803                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     18009                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      4245                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     1721                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      821                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      446                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      231                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
@@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    23226                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    24914                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    60170                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    75550                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    85536                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    93678                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                   100036                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   103937                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   105744                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   106378                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   106329                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   106819                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   108389                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   111286                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   114103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                   105493                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                   102233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                   101372                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     2580                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1027                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      427                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    23398                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    25057                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    60199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    75747                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    85433                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    93667                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    99999                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                   103866                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                   105492                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                   106217                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                   106151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                   106693                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                   108356                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                   111353                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                   114123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                   105280                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                   101866                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                   101152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     2626                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1015                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      458                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      215                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       27                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        3                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
@@ -197,121 +197,115 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      4293402                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean       94.726038                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      78.887603                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     101.441683                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        3419558     79.65%     79.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       676188     15.75%     95.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        96097      2.24%     97.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        35320      0.82%     98.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        22691      0.53%     98.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        12222      0.28%     99.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         7184      0.17%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         5103      0.12%     99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        19039      0.44%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        4293402                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         98787                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        47.730481                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       32.341812                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       98.609970                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-127           94999     96.17%     96.17% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::128-255          1343      1.36%     97.52% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-383           771      0.78%     98.31% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::384-511           397      0.40%     98.71% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-639           383      0.39%     99.10% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::640-767           367      0.37%     99.47% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::768-895           255      0.26%     99.72% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::896-1023          139      0.14%     99.87% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1151           71      0.07%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1152-1279           36      0.04%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1280-1407           14      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1408-1535            4      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-1663            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-2175            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2176-2303            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3328-3455            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3456-3583            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3840-3967            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3968-4095            2      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           98787                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         98787                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.596384                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.562558                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.102794                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              72931     73.83%     73.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1712      1.73%     75.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              18497     18.72%     94.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               3886      3.93%     98.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20               1013      1.03%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                377      0.38%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                169      0.17%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 93      0.09%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 49      0.05%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 46      0.05%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 12      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.bytesPerActivate::samples      4291005                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean       94.744514                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      78.906714                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     101.391830                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        3416666     79.62%     79.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       676199     15.76%     95.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        96816      2.26%     97.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        35217      0.82%     98.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        22960      0.54%     98.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        11971      0.28%     99.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         7013      0.16%     99.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         5097      0.12%     99.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        19066      0.44%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        4291005                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         98697                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        47.759952                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       32.369236                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       98.446894                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-255           96231     97.50%     97.50% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::256-511          1192      1.21%     98.71% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-767           746      0.76%     99.47% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::768-1023          392      0.40%     99.86% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1279          102      0.10%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1280-1535           22      0.02%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-1791            3      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1792-2047            3      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2304-2559            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-3327            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3584-3839            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4352-4607            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           98697                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         98697                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.601893                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.567781                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.107607                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              72640     73.60%     73.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1756      1.78%     75.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              18593     18.84%     94.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               3904      3.96%     98.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20               1031      1.04%     99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                392      0.40%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                184      0.19%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 91      0.09%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 55      0.06%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 31      0.03%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 17      0.02%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::27                  1      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::28                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           98787                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   131372718643                       # Total ticks spent queuing
-system.physmem.totMemAccLat              219782024893                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  23575815000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       27861.76                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::30                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           98697                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   131099404549                       # Total ticks spent queuing
+system.physmem.totMemAccLat              219483098299                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  23568985000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       27811.85                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  46611.76                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         391.77                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         136.22                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      392.36                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      136.22                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  46561.85                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         391.61                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         136.13                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      392.19                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      136.13                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           4.12                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       3.06                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      1.06                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.44                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.97                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1708262                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    352995                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        25.03                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1707890                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    353447                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   36.23                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  21.53                       # Row buffer hit rate for writes
-system.physmem.avgGap                       121079.10                       # Average gap between requests
-system.physmem.pageHitRate                      32.44                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                16098316920                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 8783803875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy               18090555600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               5260230720                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            50310315120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           409970854125                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           102538812000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             611052888360                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              793.296379                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   168045428834                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     25721020000                       # Time in different power states
+system.physmem.writeRowHitRate                  21.57                       # Row buffer hit rate for writes
+system.physmem.avgGap                       121138.49                       # Average gap between requests
+system.physmem.pageHitRate                      32.45                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                16077957840                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 8772695250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy               18085189200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               5253161040                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            50316417840                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           410294660580                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           102310835250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             611110917000                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              793.275483                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   167665323859                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     25724140000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    576504578166                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    576975365641                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                16359303240                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 8926207125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy               18686249400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               5363152560                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            50310315120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           411485095035                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           101210530500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             612340852980                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              794.968472                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   165832482361                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     25721020000                       # Time in different power states
+system.physmem_1.actEnergy                16361828280                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 8927584875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy               18681803400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               5364480960                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            50316417840                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           411044339970                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           101653218750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             612349674075                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              794.883504                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   166565047661                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     25724140000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    578718185889                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    578076556839                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               286281176                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         223407845                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          14631280                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            158010784                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               150352507                       # Number of BTB hits
+system.cpu.branchPred.lookups               286273758                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         223402774                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          14629982                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            157694112                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               150348271                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             95.153320                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                16641956                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 64                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             95.341715                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                16640713                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 63                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -430,128 +424,128 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       1540554067                       # number of cpu cycles simulated
+system.cpu.numCycles                       1540736277                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           13926810                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     2067510841                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   286281176                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          166994463                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                    1511903145                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                29287205                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  183                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles          944                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 656946227                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   957                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1540474684                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.437849                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.228901                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           13925194                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     2067435227                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   286273758                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          166988984                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                    1512088964                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                29284609                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  664                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.IcacheWaitRetryStallCycles         1031                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 656921798                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   960                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1540658157                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.437628                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.228937                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                458056876     29.73%     29.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                465435106     30.21%     59.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                101413024      6.58%     66.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                515569678     33.47%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                458280922     29.75%     29.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                465413379     30.21%     59.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                101412163      6.58%     66.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                515551693     33.46%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1540474684                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.185830                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.342057                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 74648924                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             543079640                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 849978540                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              58124682                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               14642898                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             42203677                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   755                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             2037193143                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              52473156                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               14642898                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                139724503                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               462464867                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          13004                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 837848817                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              85780595                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1976362381                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              26752450                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents              45148759                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 125663                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1475660                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               24911172                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          1985832580                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            9128057886                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       2432844380                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               133                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1540658157                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.185803                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.341849                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 74641640                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             543291473                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 849963258                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              58120186                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               14641600                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             42202380                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   756                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             2037144212                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              52474408                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               14641600                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                139712786                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               462567620                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          14938                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 837837029                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              85884184                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1976322026                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              26747258                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              45146985                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 125259                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1471751                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               25027790                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          1985779948                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            9127891240                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       2432801848                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               139                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1674898945                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                310933635                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                310881003                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                157                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            149                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 111445716                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            542550479                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           199301883                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          26937332                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         29252722                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1947933921                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.tempSerializingInsts            151                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 111429534                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            542545285                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           199304809                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          26862690                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         28866621                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1947900293                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                 216                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1857470724                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued          13498979                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       283901721                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    647143115                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                1857514523                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued          13512332                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       283868093                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    647012526                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             46                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1540474684                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.205778                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.150877                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples    1540658157                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.205663                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.150942                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           587582159     38.14%     38.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           326005186     21.16%     59.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           378227465     24.55%     83.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           219635075     14.26%     98.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            29018612      1.88%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                6187      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           587771265     38.15%     38.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           326011747     21.16%     59.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           378176386     24.55%     83.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           219651217     14.26%     98.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            29041357      1.88%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                6185      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1540474684                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1540658157                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu               166090735     41.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   2011      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead              191466761     47.26%     88.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              47541933     11.74%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu               166072420     40.95%     40.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   2002      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead              191493456     47.22%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              47936528     11.82%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1138243565     61.28%     61.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               801032      0.04%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1138226056     61.28%     61.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               801017      0.04%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.32% # Type of FU issued
@@ -573,90 +567,90 @@ system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.32% # Ty
 system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              29      0.00%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              30      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMisc             22      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            532113978     28.65%     89.97% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           186312098     10.03%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            532163815     28.65%     89.97% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           186323583     10.03%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1857470724                       # Type of FU issued
-system.cpu.iq.rate                           1.205716                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   405101440                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.218093                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         5674016313                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2231848584                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1805694743                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 238                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                230                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           70                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2262572030                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     134                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         17810782                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1857514523                       # Type of FU issued
+system.cpu.iq.rate                           1.205602                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   405504406                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.218305                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5674703700                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2231781287                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1805692489                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 241                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                242                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           71                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2263018794                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     135                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         17823551                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     84244145                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        66602                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        13196                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     24454838                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     84238951                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        66626                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        13177                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     24457764                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      4507141                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       4884537                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      4548930                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       4887285                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               14642898                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                25317454                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1284847                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1947934221                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles               14641600                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                25334604                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1297189                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1947900591                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             542550479                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            199301883                       # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts             542545285                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            199304809                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                154                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 159143                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               1124751                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          13196                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        7700546                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      8704736                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             16405282                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1827804607                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             516933891                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          29666117                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewIQFullEvents                 159299                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               1136868                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          13177                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        7700706                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      8703944                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             16404650                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1827845280                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             516985272                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          29669243                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                            84                       # number of nop insts executed
-system.cpu.iew.exec_refs                    698685293                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                229544445                       # Number of branches executed
-system.cpu.iew.exec_stores                  181751402                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.186459                       # Inst execution rate
-system.cpu.iew.wb_sent                     1808724876                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1805694813                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1169261823                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1689660637                       # num instructions consuming a value
+system.cpu.iew.exec_nop                            82                       # number of nop insts executed
+system.cpu.iew.exec_refs                    698740184                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                229542491                       # Number of branches executed
+system.cpu.iew.exec_stores                  181754912                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.186345                       # Inst execution rate
+system.cpu.iew.wb_sent                     1808718850                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1805692560                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1169243952                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1689620594                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.172107                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.692010                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.171967                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.692016                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       258006259                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       257974948                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             170                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          14630576                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1500991330                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.108622                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.025694                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          14629278                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1501179372                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.108483                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.025812                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    920697347     61.34%     61.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    250635150     16.70%     78.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    110066020      7.33%     85.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     55280178      3.68%     89.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     29318113      1.95%     91.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     34079049      2.27%     93.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     24716376      1.65%     94.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     18134019      1.21%     96.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     58065078      3.87%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    920919616     61.35%     61.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    250623048     16.70%     78.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    110074231      7.33%     85.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     55314266      3.68%     89.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     29240414      1.95%     91.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     34051194      2.27%     93.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     24724968      1.65%     94.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     18102388      1.21%     96.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     58129247      3.87%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1500991330                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1501179372                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           1544563042                       # Number of instructions committed
 system.cpu.commit.committedOps             1664032434                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -702,76 +696,76 @@ system.cpu.commit.op_class_0::MemWrite      174847045     10.51%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1664032434                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              58065078                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   3364964346                       # The number of ROB reads
-system.cpu.rob.rob_writes                  3883565961                       # The number of ROB writes
-system.cpu.timesIdled                             839                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           79383                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              58129247                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   3365056908                       # The number of ROB reads
+system.cpu.rob.rob_writes                  3883498749                       # The number of ROB writes
+system.cpu.timesIdled                             826                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           78120                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1544563024                       # Number of Instructions Simulated
 system.cpu.committedOps                    1664032416                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.997404                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.997404                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.002602                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.002602                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2175788919                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1261560913                       # number of integer regfile writes
+system.cpu.cpi                               0.997522                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.997522                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.002484                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.002484                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2175832090                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1261554579                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        42                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       52                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                6965670330                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                551865131                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               675839076                       # number of misc regfile reads
+system.cpu.fp_regfile_writes                       53                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                6965806989                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                551858746                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               675847493                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    124                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements          17004565                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.965160                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           638055083                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          17005077                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             37.521446                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          77552500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.965160                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999932                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999932                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements          17004655                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.964606                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           638048144                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          17005167                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             37.520840                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          78823500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.964606                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999931                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999931                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          415                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           97                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          419                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           93                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1335687503                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1335687503                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    469335942                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       469335942                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    168719023                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      168719023                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses        1335675523                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1335675523                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    469328921                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       469328921                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    168719105                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      168719105                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           57                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           57                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     638054965                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        638054965                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    638054965                       # number of overall hits
-system.cpu.dcache.overall_hits::total       638054965                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     17419100                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      17419100                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3867024                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3867024                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     638048026                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        638048026                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    638048026                       # number of overall hits
+system.cpu.dcache.overall_hits::total       638048026                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     17420086                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      17420086                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3866942                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3866942                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            2                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            2                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            4                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            4                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data     21286124                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       21286124                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     21286126                       # number of overall misses
-system.cpu.dcache.overall_misses::total      21286126                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 415512136500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 415512136500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 149273741664                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 149273741664                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       290000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       290000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 564785878164                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 564785878164                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 564785878164                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 564785878164                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    486755042                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    486755042                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data     21287028                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       21287028                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     21287030                       # number of overall misses
+system.cpu.dcache.overall_misses::total      21287030                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 415615381500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 415615381500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 149888945711                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 149888945711                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       398000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       398000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 565504327211                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 565504327211                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 565504327211                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 565504327211                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    486749007                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    486749007                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data            2                       # number of SoftPFReq accesses(hits+misses)
@@ -780,74 +774,74 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61
 system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    659341089                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    659341089                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    659341091                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    659341091                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.035786                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.035786                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    659335054                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    659335054                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    659335056                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    659335056                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.035789                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.035789                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.022406                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.022406                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data            1                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total            1                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.065574                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.065574                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.032284                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.032284                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.032284                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.032284                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23853.823475                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 23853.823475                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38601.710686                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38601.710686                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        72500                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        72500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 26533.054029                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 26533.054029                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 26533.051536                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 26533.051536                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     20783046                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      3318451                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            945637                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           67068                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.977827                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    49.478902                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.032286                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.032286                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.032286                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.032286                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23858.400096                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 23858.400096                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38761.622417                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38761.622417                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        99500                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        99500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26565.677802                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 26565.677802                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26565.675306                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26565.675306                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     20779473                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      3451346                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            944816                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           67198                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.993143                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    51.360844                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      4838877                       # number of writebacks
-system.cpu.dcache.writebacks::total           4838877                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3151642                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      3151642                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1129406                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1129406                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      4837348                       # number of writebacks
+system.cpu.dcache.writebacks::total           4837348                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3152457                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      3152457                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1129405                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1129405                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            4                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            4                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      4281048                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      4281048                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      4281048                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      4281048                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data     14267458                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total     14267458                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2737618                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2737618                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      4281862                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      4281862                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      4281862                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      4281862                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data     14267629                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total     14267629                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2737537                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2737537                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data     17005076                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total     17005076                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data     17005077                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total     17005077                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335579712500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 335579712500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116324734517                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 116324734517                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data     17005166                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total     17005166                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data     17005167                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total     17005167                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335438494000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 335438494000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116411117573                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 116411117573                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        68000                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        68000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451904447017                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 451904447017                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451904515017                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 451904515017                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.029311                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.029311                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451849611573                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 451849611573                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451849679573                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 451849679573                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.029312                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.029312                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015862                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015862                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SoftPFReq accesses
@@ -856,358 +850,361 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025791
 system.cpu.dcache.demand_mshr_miss_rate::total     0.025791                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025791                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.025791                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23520.637839                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23520.637839                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42491.222120                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42491.222120                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23510.458115                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23510.458115                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42524.034405                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42524.034405                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        68000                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        68000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26574.679644                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26574.679644                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26574.682080                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26574.682080                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26571.314363                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26571.314363                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26571.316799                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26571.316799                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements               585                       # number of replacements
-system.cpu.icache.tags.tagsinuse           445.973645                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           656944607                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              1073                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          612250.332712                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements               582                       # number of replacements
+system.cpu.icache.tags.tagsinuse           445.815002                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           656920172                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              1070                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          613944.085981                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   445.973645                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.871042                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.871042                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   445.815002                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.870732                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.870732                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          488                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           15                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          442                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.953125                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        1313893525                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       1313893525                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    656944607                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       656944607                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     656944607                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        656944607                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    656944607                       # number of overall hits
-system.cpu.icache.overall_hits::total       656944607                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1619                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1619                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1619                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1619                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1619                       # number of overall misses
-system.cpu.icache.overall_misses::total          1619                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    105131986                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    105131986                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    105131986                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    105131986                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    105131986                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    105131986                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    656946226                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    656946226                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    656946226                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    656946226                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    656946226                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    656946226                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses        1313844660                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       1313844660                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    656920172                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       656920172                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     656920172                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        656920172                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    656920172                       # number of overall hits
+system.cpu.icache.overall_hits::total       656920172                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1623                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1623                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1623                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1623                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1623                       # number of overall misses
+system.cpu.icache.overall_misses::total          1623                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    104193985                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    104193985                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    104193985                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    104193985                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    104193985                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    104193985                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    656921795                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    656921795                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    656921795                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    656921795                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    656921795                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    656921795                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64936.371834                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 64936.371834                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 64936.371834                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 64936.371834                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 64936.371834                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 64936.371834                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        17916                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          510                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               192                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               8                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    93.312500                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    63.750000                       # average number of cycles each access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64198.388786                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 64198.388786                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 64198.388786                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 64198.388786                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 64198.388786                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 64198.388786                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        17135                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          748                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               190                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets              11                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    90.184211                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets           68                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          546                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          546                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          546                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          546                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          546                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          546                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1073                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         1073                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         1073                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         1073                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         1073                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         1073                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     76698989                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     76698989                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     76698989                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     76698989                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     76698989                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     76698989                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          553                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          553                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          553                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          553                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          553                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          553                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1070                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1070                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1070                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1070                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1070                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1070                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     75689488                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     75689488                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     75689488                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     75689488                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     75689488                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     75689488                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71480.884436                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71480.884436                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71480.884436                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 71480.884436                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71480.884436                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 71480.884436                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70737.839252                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70737.839252                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70737.839252                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 70737.839252                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70737.839252                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 70737.839252                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued     10956462                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified     11638997                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit       427337                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued     11618797                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified     11638031                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit        14266                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
-system.cpu.l2cache.prefetcher.pfRemovedFull            2                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage      4654603                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements          4714185                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        16129.978160                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           27368962                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          4730113                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             5.786112                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      29467370500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  5231.697931                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    18.454317                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  7577.410769                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  3302.415144                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.319318                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001126                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.462488                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.201563                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.984496                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          757                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15171                       # Occupied blocks per task id
+system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
+system.cpu.l2cache.prefetcher.pfSpanPage      4656553                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements          4712696                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        16129.917520                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           27373018                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          4728623                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             5.788793                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      29478535500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks  5230.477637                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    18.698420                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  7539.676601                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  3341.064863                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.319243                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001141                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.460185                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.203922                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.984492                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022          811                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15116                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::0            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1          554                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3          202                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          498                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2399                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1267                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         9187                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1820                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.046204                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.925964                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        551303538                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       551303538                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      4838877                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      4838877                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1752165                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1752165                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           41                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total           41                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data     11480053                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total     11480053                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           41                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data     13232218                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        13232259                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           41                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data     13232218                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       13232259                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       985500                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       985500                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1032                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         1032                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data      2787359                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total      2787359                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         1032                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      3772859                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       3773891                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         1032                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      3772859                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      3773891                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  99776080498                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  99776080498                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     75349500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     75349500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 238464802000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 238464802000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     75349500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 338240882498                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 338316231998                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     75349500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 338240882498                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 338316231998                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      4838877                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      4838877                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      2737665                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      2737665                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         1073                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         1073                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data     14267412                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total     14267412                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         1073                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data     17005077                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total     17006150                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         1073                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data     17005077                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     17006150                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.359978                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.359978                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.961789                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.961789                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.195365                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.195365                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.961789                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.221867                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.221913                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.961789                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.221867                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.221913                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101244.120242                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101244.120242                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73013.081395                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73013.081395                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85552.238517                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85552.238517                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73013.081395                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89651.079592                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 89646.529801                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73013.081395                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89651.079592                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 89646.529801                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs           42                       # number of cycles access was blocked
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1          615                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3          195                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          503                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2303                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1194                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         9259                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1857                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.049500                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.922607                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        551304223                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       551304223                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      4837348                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      4837348                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1752512                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1752512                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           42                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total           42                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data     11483403                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total     11483403                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           42                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data     13235915                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total        13235957                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           42                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data     13235915                       # number of overall hits
+system.cpu.l2cache.overall_hits::total       13235957                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       985072                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       985072                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1028                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         1028                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data      2784180                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total      2784180                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         1028                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      3769252                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       3770280                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         1028                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      3769252                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      3770280                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  99860242499                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  99860242499                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     74336500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     74336500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 238301833000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 238301833000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     74336500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 338162075499                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 338236411999                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     74336500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 338162075499                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 338236411999                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks      4837348                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      4837348                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      2737584                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      2737584                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         1070                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         1070                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data     14267583                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total     14267583                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         1070                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data     17005167                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total     17006237                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         1070                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data     17005167                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total     17006237                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.359833                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.359833                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.960748                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.960748                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.195140                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.195140                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.960748                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.221653                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.221700                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.960748                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.221653                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.221700                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101373.546806                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101373.546806                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72311.770428                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72311.770428                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85591.388847                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85591.388847                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72311.770428                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89715.963671                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 89711.218265                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72311.770428                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89715.963671                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 89711.218265                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs          552                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                2                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                3                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs           21                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          184                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1639544                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1639544                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3899                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total         3899                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data        38390                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total        38390                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data        42289                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total        42289                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data        42289                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total        42289                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks       100257                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total       100257                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       993873                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total       993873                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       981601                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       981601                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1032                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1032                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      2748969                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total      2748969                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         1032                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      3730570                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      3731602                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         1032                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      3730570                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       993873                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      4725475                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  72684245482                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  72684245482                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  93518423498                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  93518423498                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     69157500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     69157500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 219665951000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 219665951000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     69157500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 313184374498                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 313253531998                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     69157500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 313184374498                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  72684245482                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 385937777480                       # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks      1638598                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1638598                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3903                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total         3903                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data        44598                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total        44598                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data        48501                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total        48501                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data        48501                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total        48501                       # number of overall MSHR hits
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks       100273                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total       100273                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher      1001612                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total      1001612                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       981169                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       981169                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1028                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1028                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      2739582                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total      2739582                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1028                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      3720751                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      3721779                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1028                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      3720751                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher      1001612                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      4723391                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  72748405464                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  72748405464                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  93609887499                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  93609887499                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     68168500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     68168500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 219013270500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 219013270500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     68168500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 312623157999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 312691326499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     68168500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 312623157999                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  72748405464                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 385439731963                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.358554                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.358554                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.961789                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.961789                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.192675                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.192675                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.961789                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.219380                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.219427                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.961789                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.219380                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.358407                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.358407                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.960748                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.960748                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.192014                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.192014                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.960748                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.218801                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.218848                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.960748                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.218801                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.277869                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 73132.327251                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 73132.327251                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95271.320524                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95271.320524                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67013.081395                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67013.081395                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79908.486054                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79908.486054                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67013.081395                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83950.810331                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83946.126087                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67013.081395                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83950.810331                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 73132.327251                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81671.742519                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.277745                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72631.323770                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 72631.323770                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95406.487057                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95406.487057                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66311.770428                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66311.770428                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79944.046391                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79944.046391                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66311.770428                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84021.520924                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84016.629278                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66311.770428                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84021.520924                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72631.323770                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81602.334417                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp      14268485                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      6478421                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict     15219349                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq      1327311                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      2737665                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      2737665                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         1073                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq     14267412                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2727                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     50993158                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          50995885                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        68672                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1398013056                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         1398081728                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     6041496                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     40052798                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.150838                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.357891                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp      14268653                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      6475946                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict     15220389                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq      1280497                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2737584                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2737584                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         1070                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq     14267583                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2718                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     50993396                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          50996114                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        68480                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1397921024                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         1397989504                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     5993194                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     40004669                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.149812                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.356887                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           34011302     84.92%     84.92% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2            6041496     15.08%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           34011476     85.02%     85.02% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2            5993193     14.98%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       40052798                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    21844528998                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       40004669                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    21843087497                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          2.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1609500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy         1500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       1605000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   25507619991                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   25507754991                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          3.3                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp            3740347                       # Transaction distribution
-system.membus.trans_dist::Writeback           1639544                       # Transaction distribution
-system.membus.trans_dist::CleanEvict          3065371                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            981875                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           981875                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       3740347                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port     14149359                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               14149359                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    407153024                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               407153024                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp            3739456                       # Transaction distribution
+system.membus.trans_dist::Writeback           1638598                       # Transaction distribution
+system.membus.trans_dist::CleanEvict          3064906                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            981345                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           981345                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       3739456                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port     14145106                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               14145106                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    407001536                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               407001536                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           9427137                       # Request fanout histogram
+system.membus.snoop_fanout::samples           9424305                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 9427137    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 9424305    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             9427137                       # Request fanout histogram
-system.membus.reqLayer0.occupancy         17268043532                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             9424305                       # Request fanout histogram
+system.membus.reqLayer0.occupancy         17323735553                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        25679820043                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        25676323677                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              3.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
index b441da851b8453f5e3e528e71bf999c85a960e30..b0d8b3c343dd53c49b65f9fa0ec7eacd66a915be 100644 (file)
@@ -1,61 +1,61 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.085019                       # Number of seconds simulated
-sim_ticks                                 85018904000                       # Number of ticks simulated
-final_tick                                85018904000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.085022                       # Number of seconds simulated
+sim_ticks                                 85021523000                       # Number of ticks simulated
+final_tick                                85021523000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 135768                       # Simulator instruction rate (inst/s)
-host_op_rate                                   143122                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               66991355                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 315704                       # Number of bytes of host memory used
-host_seconds                                  1269.10                       # Real time elapsed on the host
+host_inst_rate                                 136979                       # Simulator instruction rate (inst/s)
+host_op_rate                                   144399                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               67591393                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 315696                       # Number of bytes of host memory used
+host_seconds                                  1257.88                       # Real time elapsed on the host
 sim_insts                                   172303022                       # Number of instructions simulated
 sim_ops                                     181635954                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            126976                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             47872                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher        71296                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               246144                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             47808                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher        71104                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               245888                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst       126976                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          126976                       # Number of instructions bytes read from this memory
 system.physmem.num_reads::cpu.inst               1984                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                748                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher         1114                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  3846                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1493503                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               563075                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher       838590                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2895168                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1493503                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1493503                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1493503                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              563075                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher       838590                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2895168                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          3846                       # Number of read requests accepted
+system.physmem.num_reads::cpu.data                747                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher         1111                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  3842                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1493457                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               562305                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher       836306                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2892068                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1493457                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1493457                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1493457                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              562305                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher       836306                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2892068                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          3842                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        3846                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        3842                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   246144                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   245888                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    246144                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    245888                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 309                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 220                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 142                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 309                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 300                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 134                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 310                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                 307                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 302                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 262                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 237                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 232                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 252                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 219                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                291                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                292                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                194                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                193                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                211                       # Per bank write bursts
@@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     85018760500                       # Total gap between requests
+system.physmem.totGap                     85021379500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    3846                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    3842                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -94,16 +94,16 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      2523                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       883                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       167                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        84                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        61                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      2526                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       886                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       160                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        87                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        59                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                        37                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                        31                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        29                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                        29                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        28                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
@@ -190,78 +190,78 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          777                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      316.211068                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     199.877402                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     303.919917                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            237     30.50%     30.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          193     24.84%     55.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           84     10.81%     66.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           88     11.33%     77.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           35      4.50%     81.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           40      5.15%     87.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           20      2.57%     89.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           13      1.67%     91.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           67      8.62%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            777                       # Bytes accessed per row activation
-system.physmem.totQLat                       39111678                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 111224178                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     19230000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10169.44                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          770                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      317.174026                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     198.484323                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     309.262764                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            239     31.04%     31.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          194     25.19%     56.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           82     10.65%     66.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           86     11.17%     78.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           28      3.64%     81.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           38      4.94%     86.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           15      1.95%     88.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           16      2.08%     90.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           72      9.35%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            770                       # Bytes accessed per row activation
+system.physmem.totQLat                       41378240                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 113415740                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     19210000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10769.97                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28919.44                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.90                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29519.97                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.89                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.90                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.89                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         2.71                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.89                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       3067                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       3065                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.75                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   79.78                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     22105761.96                       # Average gap between requests
-system.physmem.pageHitRate                      79.75                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    2744280                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    1497375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  16231800                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     22129458.49                       # Average gap between requests
+system.physmem.pageHitRate                      79.78                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    2766960                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    1509750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  16169400                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy             5552966640                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2336092560                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            48961790250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              56871322905                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.930183                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    81450773508                       # Time in different power states
+system.physmem_0.actBackEnergy             2338310430                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            48959844750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              56871567930                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.933066                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    81449206260                       # Time in different power states
 system.physmem_0.memoryStateTime::REF      2838940000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       728623992                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       731844740                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3129840                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    1707750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  13712400                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    3039120                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    1658250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  13579800                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy             5552966640                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2289194100                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            49002929250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              56863639980                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.839816                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    81519548908                       # Time in different power states
+system.physmem_1.actBackEnergy             2293221150                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            48999396750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              56863861710                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.842424                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    81513735655                       # Time in different power states
 system.physmem_1.memoryStateTime::REF      2838940000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       659848592                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       665661845                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                85912123                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          68393040                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6015536                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             40101118                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                39014565                       # Number of BTB hits
+system.cpu.branchPred.lookups                85912132                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          68393043                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6015535                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             40101121                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                39014567                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.290467                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 3703089                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             97.290465                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 3703090                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect              81902                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -381,95 +381,95 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        170037809                       # number of cpu cycles simulated
+system.cpu.numCycles                        170043047                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles            5613511                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      349250633                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    85912123                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           42717654                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     158261511                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                12044973                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 1577                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.icacheStallCycles            5613517                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      349250630                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    85912132                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           42717657                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     158263984                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                12044969                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 1615                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingQuiesceStallCycles           23                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles         2368                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  78950648                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 18008                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          169901476                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.150563                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.047122                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles         2395                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  78950646                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 18010                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          169904018                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.150531                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.047148                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 17358895     10.22%     10.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 30204196     17.78%     27.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 31835534     18.74%     46.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 90502851     53.27%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 17361437     10.22%     10.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 30204201     17.78%     28.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 31835536     18.74%     46.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 90502844     53.27%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            169901476                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.505253                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.053959                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 17563828                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              17110473                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 122657456                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               6722156                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                5847563                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             11134699                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                190129                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              306600036                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              27639970                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                5847563                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 37745979                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 8468798                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         579877                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 108923634                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               8335625                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              278650711                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              13412582                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               3051453                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 842711                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                2185712                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                  35165                       # Number of times rename has blocked due to SQ full
+system.cpu.fetch.rateDist::total            169904018                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.505238                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.053895                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 17563904                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              17112948                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 122657441                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               6722163                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                5847562                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             11134700                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                190128                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              306600022                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              27639979                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                5847562                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 37746058                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 8470500                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         579781                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 108923622                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               8336495                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              278650706                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              13412569                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               3051463                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 842712                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                2185705                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                  36039                       # Number of times rename has blocked due to SQ full
 system.cpu.rename.FullRegisterEvents            26489                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           483080894                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1196921588                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        297573906                       # Number of integer rename lookups
+system.cpu.rename.RenamedOperands           483080897                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1196921555                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        297573893                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups           3006747                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             292976929                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                190103965                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                190103968                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts              23523                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts          23430                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13336347                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             34142095                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            14476543                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           2549376                       # Number of conflicting loads.
+system.cpu.rename.skidInsts                  13336341                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             34142087                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            14476532                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           2549378                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores          1793123                       # Number of conflicting stores.
 system.cpu.iq.iqInstsAdded                  264810332                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded               45855                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 214902718                       # Number of instructions issued
+system.cpu.iq.iqInstsIssued                 214902707                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued           5190620                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedInstsExamined        83220233                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    219925398                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined    219925371                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved            639                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     169901476                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.264867                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.017460                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples     169904018                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.264848                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.017464                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            52832101     31.10%     31.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            36093158     21.24%     52.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            65784259     38.72%     91.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            13574357      7.99%     99.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             1570220      0.92%     99.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               47195      0.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            52834646     31.10%     31.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            36093194     21.24%     52.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            65784220     38.72%     91.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            13574325      7.99%     99.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             1570253      0.92%     99.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               47194      0.03%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                 186      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       169901476                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       169904018                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                35605011     66.11%     66.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                35605027     66.11%     66.11% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                 152712      0.28%     66.40% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     66.40% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     66.40% # attempts to use FU when none available
@@ -494,16 +494,16 @@ system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.40% # at
 system.cpu.iq.fu_full::SimdFloatCmp             35741      0.07%     66.46% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatCvt               239      0.00%     66.47% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatDiv               201      0.00%     66.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc             1037      0.00%     66.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc             1038      0.00%     66.47% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMult            34404      0.06%     66.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             4      0.00%     66.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               14078469     26.14%     92.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               3945889      7.33%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               14078476     26.14%     92.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3945873      7.33%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             167344164     77.87%     77.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             167344168     77.87%     77.87% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult               918970      0.43%     78.30% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.30% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.30% # Type of FU issued
@@ -532,84 +532,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc         460547      0.21%     78.75% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult         206694      0.10%     78.85% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc        71623      0.03%     78.88% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt            319      0.00%     78.88% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             32006921     14.89%     93.78% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            13373534      6.22%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             32006913     14.89%     93.78% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            13373527      6.22%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              214902718                       # Type of FU issued
-system.cpu.iq.rate                           1.263853                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    53854775                       # FU busy when requested
+system.cpu.iq.FU_type_0::total              214902707                       # Type of FU issued
+system.cpu.iq.rate                           1.263814                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    53854783                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.250601                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          654798543                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads          654801069                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_writes         346070765                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    204597394                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             3953764                       # Number of floating instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses    204597399                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             3953766                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes            2012584                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses      1806443                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              266623027                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 2134466                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1601141                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses              266623022                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 2134468                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1601145                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      6245951                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         7537                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads      6245943                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         7536                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation         7067                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1831909                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores      1831898                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads        25713                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           804                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked           795                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                5847563                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 5681873                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 37049                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewSquashCycles                5847562                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 5681846                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 37059                       # Number of cycles IEW is unblocking
 system.cpu.iew.iewDispatchedInsts           264872174                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              34142095                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             14476543                       # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts              34142087                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             14476532                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts              23447                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                   3919                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 29963                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 29973                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents           7067                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect        3232804                       # Number of branches that were predicted taken incorrectly
 system.cpu.iew.predictedNotTakenIncorrect      3246682                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.branchMispredicts              6479486                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             207521850                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              30720954                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           7380868                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts             207521845                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              30720947                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           7380862                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                         15987                       # number of nop insts executed
-system.cpu.iew.exec_refs                     43860782                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 44934590                       # Number of branches executed
-system.cpu.iew.exec_stores                   13139828                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.220445                       # Inst execution rate
-system.cpu.iew.wb_sent                      206738830                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     206403837                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 129472700                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 221699640                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     43860767                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 44934593                       # Number of branches executed
+system.cpu.iew.exec_stores                   13139820                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.220408                       # Inst execution rate
+system.cpu.iew.wb_sent                      206738836                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     206403842                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 129472696                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 221699614                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.213870                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.584000                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.213833                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.584001                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        69532932                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        69532937                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           45216                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts           5840613                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    158460459                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.146345                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.646701                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples    158463001                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.146327                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.646694                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     73681032     46.50%     46.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     41276330     26.05%     72.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     22553900     14.23%     86.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      9626912      6.08%     92.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     73683575     46.50%     46.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     41276323     26.05%     72.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     22553918     14.23%     86.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      9626893      6.08%     92.85% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::4      3550160      2.24%     95.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2147757      1.36%     96.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1281176      0.81%     97.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2147765      1.36%     96.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1281178      0.81%     97.26% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::7       986541      0.62%     97.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      3356651      2.12%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      3356648      2.12%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    158460459                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    158463001                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            172317410                       # Number of instructions committed
 system.cpu.commit.committedOps              181650342                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -655,34 +655,34 @@ system.cpu.commit.op_class_0::MemWrite       12644634      6.96%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         181650342                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               3356651                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    406281881                       # The number of ROB reads
-system.cpu.rob.rob_writes                   513821502                       # The number of ROB writes
-system.cpu.timesIdled                            3434                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          136333                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               3356648                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    406284431                       # The number of ROB reads
+system.cpu.rob.rob_writes                   513821512                       # The number of ROB writes
+system.cpu.timesIdled                            3435                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          139029                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   172303022                       # Number of Instructions Simulated
 system.cpu.committedOps                     181635954                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.986853                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.986853                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.013322                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.013322                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                218956398                       # number of integer regfile reads
-system.cpu.int_regfile_writes               114512064                       # number of integer regfile writes
+system.cpu.cpi                               0.986884                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.986884                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.013291                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.013291                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                218956389                       # number of integer regfile reads
+system.cpu.int_regfile_writes               114512069                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                   2904391                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                  2441624                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 709567727                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                229536120                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                59314176                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                 709567724                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                229536137                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                59314172                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                 820036                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements             72863                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.419653                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            41115439                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs             73375                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            560.346698                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         504093500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.419653                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.998867                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.998867                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements             72862                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.418427                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            41115433                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs             73374                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            560.354254                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         506092500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.418427                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.998864                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.998864                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          162                       # Occupied blocks per task id
@@ -690,46 +690,46 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2          229
 system.cpu.dcache.tags.age_task_id_blocks_1024::3           42                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4           22                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          82529747                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         82529747                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     28729201                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        28729201                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     12341321                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       12341321                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          82529738                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         82529738                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     28729196                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        28729196                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     12341320                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       12341320                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          361                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total           361                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        22149                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        22149                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      41070522                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         41070522                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     41070883                       # number of overall hits
-system.cpu.dcache.overall_hits::total        41070883                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        89405                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         89405                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        22966                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        22966                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      41070516                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         41070516                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     41070877                       # number of overall hits
+system.cpu.dcache.overall_hits::total        41070877                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        89406                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         89406                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        22967                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        22967                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data          117                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total          117                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data          259                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total          259                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data       112371                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         112371                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       112488                       # number of overall misses
-system.cpu.dcache.overall_misses::total        112488                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    853901000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    853901000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    240852499                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    240852499                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data       112373                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         112373                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       112490                       # number of overall misses
+system.cpu.dcache.overall_misses::total        112490                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    857195000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    857195000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    240069999                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    240069999                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      2309500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total      2309500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   1094753499                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   1094753499                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   1094753499                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   1094753499                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     28818606                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     28818606                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data   1097264999                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   1097264999                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   1097264999                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   1097264999                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     28818602                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     28818602                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data          478                       # number of SoftPFReq accesses(hits+misses)
@@ -738,14 +738,14 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22408
 system.cpu.dcache.LoadLockedReq_accesses::total        22408                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     41182893                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     41182893                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     41183371                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     41183371                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     41182889                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     41182889                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     41183367                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     41183367                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003102                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.003102                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001857                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.001857                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001858                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.001858                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.244770                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.244770                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.011558                       # miss rate for LoadLockedReq accesses
@@ -754,56 +754,56 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002729
 system.cpu.dcache.demand_miss_rate::total     0.002729                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002731                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002731                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9550.931156                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  9550.931156                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10487.350823                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 10487.350823                       # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9587.667494                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total  9587.667494                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10452.823573                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 10452.823573                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  8916.988417                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  8916.988417                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  9742.313399                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total  9742.313399                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  9732.180313                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total  9732.180313                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data  9764.489682                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total  9764.489682                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data  9754.333710                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total  9754.333710                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs          166                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        10552                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        10364                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             865                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             866                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs           83                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    12.198844                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    11.967667                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks        64850                       # number of writebacks
 system.cpu.dcache.writebacks::total             64850                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        24706                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        24706                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        14404                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        14404                       # number of WriteReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        24708                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        24708                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        14405                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        14405                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          259                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total          259                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        39110                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        39110                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        39110                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        39110                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        64699                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        64699                       # number of ReadReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data        39113                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        39113                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        39113                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        39113                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        64698                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        64698                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         8562                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total         8562                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          114                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total          114                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data        73261                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total        73261                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data        73375                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total        73375                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    558347000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    558347000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     85131499                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     85131499                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data        73260                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total        73260                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data        73374                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total        73374                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    560329500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    560329500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     85295999                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     85295999                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       970000                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       970000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    643478499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    643478499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    644448499                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    644448499                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    645625499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    645625499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    646595499                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    646595499                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002245                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002245                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000692                       # mshr miss rate for WriteReq accesses
@@ -814,221 +814,222 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001779
 system.cpu.dcache.demand_mshr_miss_rate::total     0.001779                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001782                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.001782                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8629.917000                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8629.917000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  9942.945457                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  9942.945457                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8660.692757                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8660.692757                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  9962.158257                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  9962.158257                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8508.771930                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8508.771930                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8783.370402                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  8783.370402                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8782.943768                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  8782.943768                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8812.796874                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  8812.796874                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8812.324515                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  8812.324515                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             54433                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.604366                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            78892637                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           510.603635                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            78892635                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             54945                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1435.847429                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       84263927500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.604366                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.997274                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.997274                       # Average percentage of cache occupancy
+system.cpu.icache.tags.avg_refs           1435.847393                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       84266921500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.603635                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.997273                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.997273                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          274                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          275                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4           48                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         157956201                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        157956201                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     78892637                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        78892637                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      78892637                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         78892637                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     78892637                       # number of overall hits
-system.cpu.icache.overall_hits::total        78892637                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        57991                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         57991                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        57991                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          57991                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        57991                       # number of overall misses
-system.cpu.icache.overall_misses::total         57991                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    602655456                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    602655456                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    602655456                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    602655456                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    602655456                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    602655456                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     78950628                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     78950628                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     78950628                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     78950628                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     78950628                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     78950628                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         157956195                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        157956195                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     78892635                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        78892635                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      78892635                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         78892635                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     78892635                       # number of overall hits
+system.cpu.icache.overall_hits::total        78892635                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        57990                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         57990                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        57990                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          57990                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        57990                       # number of overall misses
+system.cpu.icache.overall_misses::total         57990                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    602731956                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    602731956                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    602731956                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    602731956                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    602731956                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    602731956                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     78950625                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     78950625                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     78950625                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     78950625                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     78950625                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     78950625                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000735                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000735                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000735                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000735                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000735                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000735                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10392.223897                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 10392.223897                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 10392.223897                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 10392.223897                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 10392.223897                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 10392.223897                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        58612                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10393.722297                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 10393.722297                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 10393.722297                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 10393.722297                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 10393.722297                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 10393.722297                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        59431                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets           27                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              2849                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              2848                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    20.572833                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    20.867626                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets    13.500000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3046                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         3046                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         3046                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         3046                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         3046                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         3046                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3045                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         3045                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         3045                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         3045                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         3045                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         3045                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        54945                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total        54945                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst        54945                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total        54945                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        54945                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        54945                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    535420965                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    535420965                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    535420965                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    535420965                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    535420965                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    535420965                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    536017965                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    536017965                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    536017965                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    536017965                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    536017965                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    536017965                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000696                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000696                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000696                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000696                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000696                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000696                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9744.671308                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  9744.671308                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9744.671308                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  9744.671308                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9744.671308                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  9744.671308                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9755.536719                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  9755.536719                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9755.536719                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  9755.536719                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9755.536719                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  9755.536719                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued         9365                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified         9365                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued         9423                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified         9423                       # number of prefetch candidates identified
 system.cpu.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage         1339                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.prefetcher.pfSpanPage         1377                       # number of prefetches not generated due to page crossing
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2660.276616                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             230314                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3583                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            64.279654                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2658.566262                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             230317                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3579                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            64.352333                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   701.934591                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1376.049531                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   421.061183                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   161.231311                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.042843                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks   701.921035                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1376.043878                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   421.064959                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   159.536389                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.042842                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.083987                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.025700                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.009841                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.162370                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          261                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         3322                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1           19                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2           87                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4          155                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.009737                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.162266                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022          256                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3323                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::0            2                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1           20                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2           86                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4          148                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          171                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          754                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3           37                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2295                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.015930                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.202759                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          3933865                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         3933865                       # Number of data accesses
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.015625                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.202820                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          3933845                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         3933845                       # Number of data accesses
 system.cpu.l2cache.Writeback_hits::writebacks        64850                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total        64850                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         8397                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         8397                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        52956                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        52956                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data        64220                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total        64220                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        52956                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        72617                       # number of demand (read+write) hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         8400                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         8400                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        52955                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        52955                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data        64218                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total        64218                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        52955                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        72618                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total          125573                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        52956                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        72617                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst        52955                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        72618                       # number of overall hits
 system.cpu.l2cache.overall_hits::total         125573                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data          237                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total          237                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1989                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         1989                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          521                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          521                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         1989                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          758                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          2747                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         1989                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          758                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         2747                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     18014000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     18014000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    135911500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    135911500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     37126500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     37126500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    135911500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     55140500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    191052000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    135911500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     55140500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    191052000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_misses::cpu.data          234                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total          234                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1990                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         1990                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          522                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          522                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         1990                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          756                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          2746                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         1990                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          756                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         2746                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     18159000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     18159000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    136514500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    136514500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     39124000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     39124000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    136514500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     57283000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    193797500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    136514500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     57283000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    193797500                       # number of overall miss cycles
 system.cpu.l2cache.Writeback_accesses::writebacks        64850                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total        64850                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         8634                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         8634                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        54945                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::total        54945                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        64741                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total        64741                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        64740                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total        64740                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst        54945                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data        73375                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       128320                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data        73374                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       128319                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst        54945                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data        73375                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       128320                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.027450                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.027450                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.036200                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.036200                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.008047                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.008047                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.036200                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.010330                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.021407                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.036200                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.010330                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.021407                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76008.438819                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76008.438819                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68331.573655                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68331.573655                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 71260.076775                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 71260.076775                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68331.573655                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72744.722955                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69549.326538                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68331.573655                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72744.722955                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69549.326538                       # average overall miss latency
+system.cpu.l2cache.overall_accesses::cpu.data        73374                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       128319                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.027102                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.027102                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.036218                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.036218                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.008063                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.008063                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.036218                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.010303                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.021400                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.036218                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.010303                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.021400                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77602.564103                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77602.564103                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68600.251256                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68600.251256                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 74950.191571                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 74950.191571                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68600.251256                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75771.164021                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70574.471959                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68600.251256                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75771.164021                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70574.471959                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1037,133 +1038,133 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data            2                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total            2                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            5                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data            1                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total            1                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            6                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            6                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            8                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::total            8                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           10                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            6                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data            9                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total           15                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           10                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            6                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data            9                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           15                       # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher         1818                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total         1818                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          235                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total          235                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher         1827                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total         1827                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          233                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total          233                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1984                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1984                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          513                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          513                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          514                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          514                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst         1984                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          748                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         2732                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          747                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         2731                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         1984                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          748                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher         1818                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         4550                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher     70301588                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total     70301588                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     16173000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     16173000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    123686500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    123686500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     33594500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     33594500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    123686500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     49767500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    173454000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    123686500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     49767500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher     70301588                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    243755588                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.data          747                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher         1827                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         4558                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher     69341141                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total     69341141                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     16554000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     16554000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    124261000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    124261000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     35586000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     35586000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    124261000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     52140000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    176401000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    124261000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     52140000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher     69341141                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    245742141                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.027218                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.027218                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.026986                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.026986                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.036109                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.036109                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.007924                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.007924                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.007939                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.007939                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.036109                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.010194                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.021291                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.010181                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.021283                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.036109                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.010194                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.010181                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.035458                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38669.740374                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 38669.740374                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68821.276596                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68821.276596                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62341.985887                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62341.985887                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65486.354776                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65486.354776                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62341.985887                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66534.090909                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63489.751098                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62341.985887                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66534.090909                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38669.740374                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53572.656703                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.035521                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37953.552819                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 37953.552819                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71047.210300                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71047.210300                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62631.552419                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62631.552419                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69233.463035                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69233.463035                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62631.552419                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69799.196787                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64592.090809                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62631.552419                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69799.196787                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37953.552819                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53914.467091                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp        119686                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        119685                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback        64850                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict        51933                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq         2160                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq         2169                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         8634                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         8634                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq        54945                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq        64741                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       155973                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       217450                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            373423                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        64740                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       155974                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       217447                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            373421                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3516480                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8846400                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           12362880                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                        2160                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       257776                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.008379                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.091155                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8846336                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           12362816                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                        2169                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       257783                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.008414                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.091342                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             255616     99.16%     99.16% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2               2160      0.84%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             255614     99.16%     99.16% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2               2169      0.84%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         257776                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      192658000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         257783                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      192657000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      82430973                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      82431971                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     110066991                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     110065491                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               3611                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               235                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              235                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          3611                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7692                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   7692                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       246144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  246144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp               3609                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               233                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              233                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          3609                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7684                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   7684                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       245888                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  245888                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              3846                       # Request fanout histogram
+system.membus.snoop_fanout::samples              3842                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    3846    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    3842    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                3846                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             5081597                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                3842                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             4994667                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           20277583                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           20261553                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
index eec67c0c4f63985e384675d8c512eea5dcc2fae0..d1669be2b6ea1508e31aa9d3b2896c6d411a5e60 100644 (file)
@@ -4,11 +4,11 @@ sim_seconds                                  2.802895                       # Nu
 sim_ticks                                2802894699500                       # Number of ticks simulated
 final_tick                               2802894699500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1243628                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1515342                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            23740372608                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 632596                       # Number of bytes of host memory used
-host_seconds                                   118.06                       # Real time elapsed on the host
+host_inst_rate                                1692608                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2062417                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            32311218818                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 579900                       # Number of bytes of host memory used
+host_seconds                                    86.75                       # Real time elapsed on the host
 sim_insts                                   146828240                       # Number of instructions simulated
 sim_ops                                     178908039                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -1387,7 +1387,7 @@ system.membus.trans_dist::ReadResp              75378                       # Tr
 system.membus.trans_dist::WriteReq              30846                       # Transaction distribution
 system.membus.trans_dist::WriteResp             30846                       # Transaction distribution
 system.membus.trans_dist::Writeback            132426                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            15436                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            15452                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq            60361                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq          40917                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp           15653                       # Transaction distribution
@@ -1399,11 +1399,11 @@ system.membus.trans_dist::InvalidateResp        36224                       # Tr
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107876                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13474                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       666939                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       788323                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       666955                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       788339                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109394                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       109394                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 897717                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 897733                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162766                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        26948                       # Cumulative packet size per connected master and slave (bytes)
@@ -1413,17 +1413,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2332288
 system.membus.pkt_size_system.iocache.mem_side::total      2332288                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                20456418                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            587643                       # Request fanout histogram
+system.membus.snoop_fanout::samples            587659                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  587643    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  587659    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              587643                       # Request fanout histogram
+system.membus.snoop_fanout::total              587659                       # Request fanout histogram
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
index b0093ef47bd52a8a6e4ff309e1a4d301b99c6189..3792a44c99b1821e3112387eebb59495e05fb423 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.868721                       # Number of seconds simulated
-sim_ticks                                2868720569000                       # Number of ticks simulated
-final_tick                               2868720569000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.868749                       # Number of seconds simulated
+sim_ticks                                2868748596000                       # Number of ticks simulated
+final_tick                               2868748596000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 718623                       # Simulator instruction rate (inst/s)
-host_op_rate                                   869205                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            15661016649                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 645712                       # Number of bytes of host memory used
-host_seconds                                   183.18                       # Real time elapsed on the host
-sim_insts                                   131634295                       # Number of instructions simulated
-sim_ops                                     159217322                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 811357                       # Simulator instruction rate (inst/s)
+host_op_rate                                   981408                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            17699889488                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 595428                       # Number of bytes of host memory used
+host_seconds                                   162.08                       # Real time elapsed on the host
+sim_insts                                   131502488                       # Number of instructions simulated
+sim_ops                                     159063828                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker          448                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1149540                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1292388                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      8590592                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           151892                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           585104                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher       399936                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1184036                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1278116                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8584576                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           111060                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           568976                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       412800                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12171052                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1149540                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       151892                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1301432                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8736704                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12141100                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1184036                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       111060                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1295096                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8715904                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8754268                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8733468                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker            7                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             26415                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             20713                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       134228                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2528                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              9162                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher         6249                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             26954                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             20490                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       134134                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1890                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              8910                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher         6450                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                199320                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          136511                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                198852                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          136186                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               140902                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               140577                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker           156                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            45                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              400715                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              450510                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      2994573                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker            22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               52948                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              203960                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       139413                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              412736                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              445531                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      2992446                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               38714                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              198336                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       143895                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              335                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4242676                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         400715                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          52948                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             453663                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3045505                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4232194                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         412736                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          38714                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             451450                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3038225                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6109                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3051628                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3045505                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3044348                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3038225                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker          156                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           45                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             400715                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             456619                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      2994573                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              52948                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             203974                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       139413                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             412736                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             451639                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      2992446                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              38714                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             198350                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       143895                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             335                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7294304                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        199320                       # Number of read requests accepted
-system.physmem.writeReqs                       140902                       # Number of write requests accepted
-system.physmem.readBursts                      199320                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     140902                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12746944                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9536                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8766656                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12171052                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8754268                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      149                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                7276541                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        198852                       # Number of read requests accepted
+system.physmem.writeReqs                       140577                       # Number of write requests accepted
+system.physmem.readBursts                      198852                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     140577                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12717568                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8960                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8745536                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12141100                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8733468                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      140                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          49030                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               12070                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               11831                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12274                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               12388                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               20676                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               12594                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12033                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               12197                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               12580                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               12376                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11749                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11049                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11595                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11646                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10943                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11170                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8793                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8761                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9161                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8988                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8395                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                9123                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8851                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8630                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                9078                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8912                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8485                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8089                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8403                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8019                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7666                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7625                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          48892                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               12039                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11932                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               12219                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12193                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               20606                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12429                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12151                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               12313                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               12521                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               12643                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11981                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11107                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11212                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11639                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10708                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11019                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8788                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8813                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9145                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8891                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8356                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8969                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8864                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8722                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                9036                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                9148                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8611                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               8177                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8063                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7981                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7509                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7576                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          43                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2868720108500                       # Total gap between requests
+system.physmem.numWrRetry                          39                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2868748135500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                    9731                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  189561                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  189093                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 136511                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    138723                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     15961                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     10493                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      8947                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      7139                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      5591                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      4693                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      3946                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3444                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        97                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       69                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       37                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 136186                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    138565                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     16001                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     10431                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      8838                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      7035                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      5529                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      4705                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      3918                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3439                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       106                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       73                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       39                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::12                       18                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
@@ -184,156 +180,158 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2740                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3251                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4887                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5950                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6428                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6725                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6970                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8417                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8666                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     9995                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9375                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9280                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8482                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8751                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10022                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7549                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7221                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      312                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      261                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      257                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      214                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      148                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      188                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      131                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        88863                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      242.097791                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     137.224347                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     303.120448                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          46751     52.61%     52.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        18086     20.35%     72.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6032      6.79%     79.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3695      4.16%     83.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2426      2.73%     86.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1553      1.75%     88.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1048      1.18%     89.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          926      1.04%     90.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8346      9.39%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          88863                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6835                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        29.139722                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      544.203282                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6833     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2660                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4817                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5889                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6298                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6719                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6977                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     8373                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8663                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     9929                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9268                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8525                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8846                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    10151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7567                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7217                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      252                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      188                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      177                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      245                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      148                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      158                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      160                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      115                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       96                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       79                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       75                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       49                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       51                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      133                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        88033                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      243.806754                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     138.095781                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     304.392225                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          45989     52.24%     52.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        18103     20.56%     72.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5912      6.72%     79.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3673      4.17%     83.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2470      2.81%     86.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1565      1.78%     88.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          995      1.13%     89.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          958      1.09%     90.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8368      9.51%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          88033                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6795                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        29.243709                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      545.811163                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6793     99.97%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::43008-45055            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6835                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6835                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.040819                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.588322                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       11.942463                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5790     84.71%     84.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             288      4.21%     88.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             181      2.65%     91.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              61      0.89%     92.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              66      0.97%     93.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             161      2.36%     95.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              22      0.32%     96.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              10      0.15%     96.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              10      0.15%     96.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               9      0.13%     96.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               9      0.13%     96.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              11      0.16%     96.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             163      2.38%     99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               7      0.10%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               5      0.07%     99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               8      0.12%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               6      0.09%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.01%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               3      0.04%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.01%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.01%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            13      0.19%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             2      0.03%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             4      0.06%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6835                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4713712824                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8448169074                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    995855000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       23666.66                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6795                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6795                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.110228                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.616765                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.492638                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5748     84.59%     84.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             291      4.28%     88.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             178      2.62%     91.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              60      0.88%     92.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              79      1.16%     93.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             156      2.30%     95.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              28      0.41%     96.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               7      0.10%     96.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              12      0.18%     96.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               7      0.10%     96.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               9      0.13%     96.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               7      0.10%     96.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             161      2.37%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               3      0.04%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               4      0.06%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              11      0.16%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               3      0.04%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.01%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.03%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.01%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.01%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.04%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            11      0.16%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.01%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             4      0.06%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             5      0.07%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6795                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4722732900                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8448582900                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    993560000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       23766.72                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  42416.66                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.44                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.06                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.24                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.05                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  42516.72                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.43                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.05                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.23                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.04                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.08                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        27.14                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     166377                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     80909                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.53                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  59.06                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8431906.54                       # Average gap between requests
-system.physmem.pageHitRate                      73.56                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  348886440                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  190364625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 827283600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                458148960                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           187370795040                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            84523956795                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1647087865500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1920807300960                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.569582                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2739939393002                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     95792840000                       # Time in different power states
+system.physmem.avgRdQLen                         1.10                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        22.76                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     166188                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     81139                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.63                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  59.36                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8451688.38                       # Average gap between requests
+system.physmem.pageHitRate                      73.74                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  346580640                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  189106500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 825871800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                457151040                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           187372320720                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            84248156880                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1647343810500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1920782998080                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.555658                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2740372132788                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     95793620000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     32988240498                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     32582747712                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  322917840                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  176195250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 726242400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                429474960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           187370795040                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            83768933655                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1647750166500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1920544725645                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.478051                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2741046257852                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     95792840000                       # Time in different power states
+system.physmem_1.actEnergy                  318948840                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  174029625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 724074000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                428334480                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           187372320720                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            83576818575                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1647932703750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1920527229990                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.466501                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2741353761866                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     95793620000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     31880394648                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     31595469384                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
@@ -389,57 +387,57 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                     7828                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort                7828                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1457                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         6371                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples         7828                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0           7828    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total         7828                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples         6434                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 10362.060926                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean  9317.145265                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  5859.670820                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383         6278     97.58%     97.58% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767          144      2.24%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151            7      0.11%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-98303            4      0.06%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::212992-229375            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total         6434                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks                     7824                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort                7824                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1442                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         6382                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples         7824                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0           7824    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total         7824                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples         6430                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 10325.194401                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean  9252.413387                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  6597.669693                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767         6417     99.80%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535            7      0.11%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-98303            2      0.03%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-131071            3      0.05%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::294912-327679            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total         6430                       # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walksPending::samples   1109412500                       # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::0     1109412500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::total   1109412500                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         5016     77.96%     77.96% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1418     22.04%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         6434                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         7828                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K         5027     78.18%     78.18% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1403     21.82%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         6430                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         7824                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         7828                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6434                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         7824                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6430                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6434                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        14262                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6430                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        14254                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    22804186                       # DTB read hits
-system.cpu0.dtb.read_misses                      6713                       # DTB read misses
-system.cpu0.dtb.write_hits                   17553531                       # DTB write hits
-system.cpu0.dtb.write_misses                     1115                       # DTB write misses
+system.cpu0.dtb.read_hits                    25236580                       # DTB read hits
+system.cpu0.dtb.read_misses                      6707                       # DTB read misses
+system.cpu0.dtb.write_hits                   18793560                       # DTB write hits
+system.cpu0.dtb.write_misses                     1117                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3455                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    3444                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1817                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  1747                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.dtb.perms_faults                      282                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                22810899                       # DTB read accesses
-system.cpu0.dtb.write_accesses               17554646                       # DTB write accesses
+system.cpu0.dtb.read_accesses                25243287                       # DTB read accesses
+system.cpu0.dtb.write_accesses               18794677                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         40357717                       # DTB hits
-system.cpu0.dtb.misses                           7828                       # DTB misses
-system.cpu0.dtb.accesses                     40365545                       # DTB accesses
+system.cpu0.dtb.hits                         44030140                       # DTB hits
+system.cpu0.dtb.misses                           7824                       # DTB misses
+system.cpu0.dtb.accesses                     44037964                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -477,15 +475,14 @@ system.cpu0.itb.walker.walkWaitTime::samples         3348
 system.cpu0.itb.walker.walkWaitTime::0           3348    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.itb.walker.walkWaitTime::total         3348                       # Table walker wait (enqueue to first request) latency
 system.cpu0.itb.walker.walkCompletionTime::samples         2332                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 10683.319039                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean  9538.524469                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  5751.182189                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191          887     38.04%     38.04% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383         1322     56.69%     94.73% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575           85      3.64%     98.37% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-32767           28      1.20%     99.57% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-40959            7      0.30%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::40960-49151            1      0.04%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 10655.874786                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean  9465.333686                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  5846.917058                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191          920     39.45%     39.45% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383         1284     55.06%     94.51% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575           84      3.60%     98.11% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-32767           34      1.46%     99.57% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-40959            8      0.34%     99.91% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::90112-98303            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::114688-122879            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::total         2332                       # Table walker service (enqueue to completion) latency
@@ -502,7 +499,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2332                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2332                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin::total         5680                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   108563333                       # ITB inst hits
+system.cpu0.itb.inst_hits                   119342617                       # ITB inst hits
 system.cpu0.itb.inst_misses                      3348                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
@@ -519,172 +516,172 @@ system.cpu0.itb.domain_faults                       0                       # Nu
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               108566681                       # ITB inst accesses
-system.cpu0.itb.hits                        108563333                       # DTB hits
+system.cpu0.itb.inst_accesses               119345965                       # ITB inst accesses
+system.cpu0.itb.hits                        119342617                       # DTB hits
 system.cpu0.itb.misses                           3348                       # DTB misses
-system.cpu0.itb.accesses                    108566681                       # DTB accesses
-system.cpu0.numCycles                      5737441138                       # number of cpu cycles simulated
+system.cpu0.itb.accesses                    119345965                       # DTB accesses
+system.cpu0.numCycles                      5737497192                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  105480509                       # Number of instructions committed
-system.cpu0.committedOps                    127164191                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            112285314                       # Number of integer alu accesses
+system.cpu0.committedInsts                  115654281                       # Number of instructions committed
+system.cpu0.committedOps                    139770289                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            123734710                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                  9820                       # Number of float alu accesses
-system.cpu0.num_func_calls                   10414111                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     14574473                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   112285314                       # number of integer instructions
+system.cpu0.num_func_calls                   12768418                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     15718242                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   123734710                       # number of integer instructions
 system.cpu0.num_fp_insts                         9820                       # number of float instructions
-system.cpu0.num_int_register_reads          205015592                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          77505457                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          227859200                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          85998639                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                7560                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes               2264                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           459494635                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           48916829                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     41493426                       # number of memory refs
-system.cpu0.num_load_insts                   23055800                       # Number of load instructions
-system.cpu0.num_store_insts                  18437626                       # Number of store instructions
-system.cpu0.num_idle_cycles              5489199817.904087                       # Number of idle cycles
-system.cpu0.num_busy_cycles              248241320.095913                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.043267                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.956733                       # Percentage of idle cycles
-system.cpu0.Branches                         25703635                       # Number of branches fetched
+system.cpu0.num_cc_register_reads           506429091                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           52352971                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     45168124                       # number of memory refs
+system.cpu0.num_load_insts                   25488908                       # Number of load instructions
+system.cpu0.num_store_insts                  19679216                       # Number of store instructions
+system.cpu0.num_idle_cycles              5463941135.084096                       # Number of idle cycles
+system.cpu0.num_busy_cycles              273556056.915905                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.047679                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.952321                       # Percentage of idle cycles
+system.cpu0.Branches                         29223626                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                 2273      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 88750967     68.09%     68.09% # Class of executed instruction
-system.cpu0.op_class::IntMult                   92819      0.07%     68.16% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              8217      0.01%     68.17% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.17% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.17% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.17% # Class of executed instruction
-system.cpu0.op_class::MemRead                23055800     17.69%     85.86% # Class of executed instruction
-system.cpu0.op_class::MemWrite               18437626     14.14%    100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 98271812     68.45%     68.45% # Class of executed instruction
+system.cpu0.op_class::IntMult                  109732      0.08%     68.53% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              8207      0.01%     68.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.54% # Class of executed instruction
+system.cpu0.op_class::MemRead                25488908     17.75%     86.29% # Class of executed instruction
+system.cpu0.op_class::MemWrite               19679216     13.71%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 130347702                       # Class of executed instruction
+system.cpu0.op_class::total                 143560148                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    1862                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements           694931                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          494.123274                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           39503506                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           695443                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            56.803370                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       1135131000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   494.123274                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.965085                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.965085                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                    1875                       # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements           696532                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          491.305468                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           43154174                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           697044                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            61.910258                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       1135377000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   491.305468                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.959581                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.959581                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          319                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           89                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          308                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           97                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         81393420                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        81393420                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     21551304                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       21551304                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     16831338                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      16831338                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       318322                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       318322                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       365658                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       365658                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       362750                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       362750                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     38382642                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        38382642                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     38700964                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       38700964                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       398253                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       398253                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       324071                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       324071                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       128299                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       128299                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21791                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        21791                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        19751                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        19751                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       722324                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        722324                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       850623                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       850623                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5056802000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   5056802000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5106772500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   5106772500                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    332740500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    332740500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    437773500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    437773500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1801500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1801500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  10163574500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  10163574500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  10163574500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  10163574500                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     21949557                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     21949557                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     17155409                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     17155409                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       446621                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       446621                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       387449                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       387449                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       382501                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       382501                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     39104966                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     39104966                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     39551587                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     39551587                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.018144                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.018144                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018890                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.018890                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.287266                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.287266                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056242                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056242                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051636                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051636                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.018471                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.018471                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.021507                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.021507                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12697.461162                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 12697.461162                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15758.190335                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 15758.190335                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15269.629664                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15269.629664                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22164.624576                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22164.624576                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         88699037                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        88699037                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     23972048                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       23972048                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     18061887                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      18061887                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       318120                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       318120                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       365603                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       365603                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       362648                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       362648                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     42033935                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        42033935                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     42352055                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       42352055                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       398676                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       398676                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       324664                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       324664                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       128643                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       128643                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21706                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        21706                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        19707                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        19707                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       723340                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        723340                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       851983                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       851983                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5067389500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   5067389500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5162627000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   5162627000                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    330228000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    330228000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    435506500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    435506500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1585500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1585500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  10230016500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  10230016500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  10230016500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  10230016500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     24370724                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     24370724                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     18386551                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     18386551                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       446763                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       446763                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       387309                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       387309                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       382355                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       382355                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     42757275                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     42757275                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     43204038                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     43204038                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.016359                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.016359                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017658                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.017658                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.287945                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.287945                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056043                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056043                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051541                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051541                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.016917                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.016917                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.019720                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.019720                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12710.545656                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 12710.545656                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15901.445802                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 15901.445802                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15213.673639                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15213.673639                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22099.076470                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22099.076470                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14070.658735                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 14070.658735                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11948.389004                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 11948.389004                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14142.749606                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 14142.749606                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12007.301202                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 12007.301202                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -693,147 +690,147 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       507088                       # number of writebacks
-system.cpu0.dcache.writebacks::total           507088                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25317                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        25317                       # number of ReadReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15125                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15125                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data        25317                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total        25317                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data        25317                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total        25317                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       372936                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       372936                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       324071                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       324071                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       100997                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       100997                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6666                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6666                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        19751                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        19751                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       697007                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       697007                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       798004                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       798004                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        21110                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        21110                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        19686                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        19686                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        40796                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        40796                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4291277500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4291277500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4782701500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4782701500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1606991500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1606991500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    101428000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    101428000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    418075500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    418075500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1748500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1748500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9073979000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   9073979000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10680970500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  10680970500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4433767500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4433767500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3394597500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3394597500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7828365000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7828365000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016991                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016991                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018890                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018890                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.226136                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.226136                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017205                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.017205                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051636                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051636                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.017824                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.017824                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.020176                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.020176                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11506.739762                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11506.739762                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14758.190335                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14758.190335                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15911.279543                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15911.279543                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15215.721572                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15215.721572                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21167.307984                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21167.307984                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       508357                       # number of writebacks
+system.cpu0.dcache.writebacks::total           508357                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25412                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        25412                       # number of ReadReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15099                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15099                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data        25412                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total        25412                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data        25412                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total        25412                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       373264                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       373264                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       324664                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       324664                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       101205                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       101205                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6607                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6607                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        19707                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        19707                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       697928                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       697928                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       799133                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       799133                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        32335                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        32335                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28719                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28719                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        61054                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        61054                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4299217000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4299217000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4837963000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4837963000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1611370000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1611370000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    100016000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    100016000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    415846500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    415846500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1538500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1538500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9137180000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   9137180000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10748550000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  10748550000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6362298500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6362298500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   4936759500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4936759500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11299058000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11299058000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.015316                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.015316                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017658                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017658                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.226530                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.226530                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017059                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.017059                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051541                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051541                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016323                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.016323                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018497                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.018497                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11517.898860                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11517.898860                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14901.445802                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14901.445802                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15921.841806                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15921.841806                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15137.884062                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15137.884062                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21101.461410                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21101.461410                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13018.490489                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13018.490489                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13384.607721                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13384.607721                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210031.620085                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210031.620085                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172437.138068                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172437.138068                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 191890.503971                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191890.503971                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13091.866210                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13091.866210                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13450.264224                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13450.264224                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196761.976187                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196761.976187                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171898.725582                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171898.725582                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 185066.629541                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 185066.629541                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1106064                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.455953                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          107456748                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1106576                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            97.107427                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      13496677000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.455953                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998937                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998937                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          1105972                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.454897                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          118236124                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1106484                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs           106.857509                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      13516114000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.454897                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998935                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998935                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          208                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          206                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          214                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        218233251                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       218233251                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    107456748                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      107456748                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    107456748                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       107456748                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    107456748                       # number of overall hits
-system.cpu0.icache.overall_hits::total      107456748                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1106585                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1106585                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1106585                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1106585                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1106585                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1106585                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10879255500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  10879255500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  10879255500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  10879255500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  10879255500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  10879255500                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    108563333                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    108563333                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    108563333                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    108563333                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    108563333                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    108563333                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.010193                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.010193                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.010193                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.010193                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.010193                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.010193                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9831.378069                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9831.378069                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9831.378069                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  9831.378069                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9831.378069                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  9831.378069                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        239791727                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       239791727                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    118236124                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      118236124                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    118236124                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       118236124                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    118236124                       # number of overall hits
+system.cpu0.icache.overall_hits::total      118236124                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1106493                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1106493                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1106493                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1106493                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1106493                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1106493                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10938029500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  10938029500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  10938029500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  10938029500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  10938029500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  10938029500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    119342617                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    119342617                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    119342617                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    119342617                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    119342617                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    119342617                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.009272                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.009272                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.009272                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.009272                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.009272                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.009272                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9885.312876                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9885.312876                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9885.312876                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9885.312876                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9885.312876                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9885.312876                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -842,448 +839,448 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1106585                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1106585                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1106585                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1106585                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1106585                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1106585                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1106493                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1106493                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      1106493                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1106493                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      1106493                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1106493                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10325963000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  10325963000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10325963000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  10325963000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10325963000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  10325963000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10384783000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  10384783000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10384783000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  10384783000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10384783000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  10384783000                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    800795500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    800795500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    800795500                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total    800795500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.010193                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010193                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.010193                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.010193                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.010193                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.010193                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9331.378069                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9331.378069                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9331.378069                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  9331.378069                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9331.378069                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  9331.378069                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.009272                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009272                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.009272                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.009272                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.009272                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.009272                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9385.312876                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9385.312876                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9385.312876                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  9385.312876                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9385.312876                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  9385.312876                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88760.308136                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88760.308136                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88760.308136                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88760.308136                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      1850657                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      1850711                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit           45                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      1841098                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      1841106                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit            7                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       237577                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements          266648                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16090.167348                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           3241094                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          282873                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs           11.457771                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle    2844827650500                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  7840.907632                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     1.369036                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.138555                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4562.781634                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1957.525775                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1727.444715                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.478571                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000084                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000008                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.278490                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.119478                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.105435                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.982066                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1088                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023            7                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15130                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           11                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          286                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          359                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          432                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
+system.cpu0.l2cache.prefetcher.pfSpanPage       237750                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements          269395                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16110.328705                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           3241181                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          285612                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs           11.348196                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks  7729.941983                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     2.543117                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.104661                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4692.501202                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1977.796502                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1707.441239                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.471798                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000155                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000006                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.286408                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.120715                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.104214                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.983296                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1097                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023            6                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15114                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            9                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          275                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          382                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          431                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          118                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3231                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7855                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3884                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.066406                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000427                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.923462                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        60109727                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       60109727                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker         8002                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         3594                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total         11596                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks       507087                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total       507087                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28350                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total        28350                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1666                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total         1666                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       228036                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       228036                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1059903                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      1059903                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       386161                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total       386161                       # number of ReadSharedReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker         8002                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker         3594                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      1059903                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       614197                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        1685696                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker         8002                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker         3594                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      1059903                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       614197                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       1685696                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          229                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          110                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total          339                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        26033                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        26033                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        18081                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        18081                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            4                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            4                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data        41652                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total        41652                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        46682                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total        46682                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data        94438                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total        94438                       # number of ReadSharedReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          229                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker          110                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst        46682                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data       136090                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total       183111                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          229                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker          110                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst        46682                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data       136090                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total       183111                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker      5419000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2507000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total      7926000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    480959500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total    480959500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    368223000                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    368223000                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1666996                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1666996                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   1951085500                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total   1951085500                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   2317097000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total   2317097000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   2767769000                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total   2767769000                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker      5419000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2507000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst   2317097000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data   4718854500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total   7043877500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker      5419000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2507000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst   2317097000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data   4718854500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total   7043877500                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker         8231                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         3704                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total        11935                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks       507087                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total       507087                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        54383                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total        54383                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        19747                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total        19747                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            4                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            4                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       269688                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total       269688                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1106585                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      1106585                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       480599                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total       480599                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker         8231                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         3704                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      1106585                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data       750287                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total      1868807                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker         8231                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         3704                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      1106585                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data       750287                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total      1868807                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.027822                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.029698                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.028404                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.478697                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.478697                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.915633                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.915633                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          102                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3320                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7689                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3966                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.066956                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000366                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.922485                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        60150726                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses       60150726                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker         7925                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         3539                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total         11464                       # number of ReadReq hits
+system.cpu0.l2cache.Writeback_hits::writebacks       508356                       # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total       508356                       # number of Writeback hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28387                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total        28387                       # number of UpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1736                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::total         1736                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       229125                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       229125                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1058458                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      1058458                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       386565                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total       386565                       # number of ReadSharedReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker         7925                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker         3539                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      1058458                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data       615690                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total        1685612                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker         7925                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker         3539                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      1058458                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data       615690                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total       1685612                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          220                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          114                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total          334                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        25774                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total        25774                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        17960                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total        17960                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data           11                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total           11                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data        41378                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total        41378                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        48035                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total        48035                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data        94511                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total        94511                       # number of ReadSharedReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          220                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker          114                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst        48035                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data       135889                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total       184258                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          220                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker          114                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst        48035                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data       135889                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total       184258                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker      5406500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2600000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total      8006500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    476714500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total    476714500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    365472000                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    365472000                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1464493                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1464493                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2004346000                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total   2004346000                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   2385304000                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total   2385304000                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   2775342500                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total   2775342500                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker      5406500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2600000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst   2385304000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data   4779688500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total   7172999000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker      5406500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2600000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst   2385304000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data   4779688500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total   7172999000                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker         8145                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         3653                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total        11798                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::writebacks       508356                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total       508356                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        54161                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total        54161                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        19696                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total        19696                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data           11                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total           11                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       270503                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total       270503                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1106493                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      1106493                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       481076                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total       481076                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker         8145                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         3653                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      1106493                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data       751579                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total      1869870                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker         8145                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         3653                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      1106493                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data       751579                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      1869870                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.027010                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.031207                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.028310                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.475877                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.475877                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.911860                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.911860                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.154445                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.154445                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.042186                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.042186                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.196501                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.196501                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.027822                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.029698                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.042186                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.181384                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.097983                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.027822                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.029698                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.042186                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.181384                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.097983                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23663.755459                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22790.909091                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 23380.530973                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18474.993278                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18474.993278                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20365.189978                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20365.189978                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       416749                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       416749                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 46842.540574                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 46842.540574                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 49635.769676                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 49635.769676                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29307.789237                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29307.789237                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23663.755459                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22790.909091                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49635.769676                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34674.513190                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 38467.800951                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23663.755459                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22790.909091                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49635.769676                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34674.513190                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 38467.800951                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.152967                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.152967                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.043412                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.043412                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.196458                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.196458                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.027010                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.031207                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.043412                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.180805                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.098541                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.027010                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.031207                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.043412                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.180805                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.098541                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker        24575                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22807.017544                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 23971.556886                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18495.945526                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18495.945526                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20349.220490                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20349.220490                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 133135.727273                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 133135.727273                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48439.895597                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48439.895597                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 49657.624649                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 49657.624649                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29365.285522                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29365.285522                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker        24575                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22807.017544                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49657.624649                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35173.476146                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 38929.104842                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker        24575                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22807.017544                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49657.624649                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35173.476146                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 38929.104842                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs           52                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           26                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       195259                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          195259                       # number of writebacks
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1202                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         1202                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data           29                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total           29                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         1231                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         1231                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         1231                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         1231                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          229                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          110                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total          339                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks         8231                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::total         8231                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       244881                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       244881                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        26033                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        26033                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        18081                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        18081                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            4                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        40450                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        40450                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        46682                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        46682                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data        94409                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total        94409                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          229                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          110                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        46682                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data       134859                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total       181880                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          229                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          110                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        46682                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data       134859                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       244881                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total       426761                       # number of overall MSHR misses
+system.cpu0.l2cache.writebacks::writebacks       196326                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          196326                       # number of writebacks
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1152                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         1152                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data           31                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total           31                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         1183                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total         1183                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         1183                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total         1183                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          220                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          114                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total          334                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks         8437                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::total         8437                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       245004                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       245004                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        25774                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        25774                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        17960                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        17960                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data           11                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total           11                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        40226                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total        40226                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        48035                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        48035                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data        94480                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total        94480                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          220                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          114                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        48035                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data       134706                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total       183075                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          220                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          114                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        48035                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data       134706                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       245004                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total       428079                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        21110                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        30132                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        19686                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        19686                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        32335                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        41357                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28719                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28719                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        40796                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        49818                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      4045000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1847000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total      5892000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  13903852400                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  13903852400                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    522651500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    522651500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    269507500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    269507500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1348996                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1348996                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1589383000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1589383000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2037005000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2037005000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2197124000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2197124000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      4045000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1847000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2037005000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   3786507000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total   5829404000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      4045000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1847000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2037005000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   3786507000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  13903852400                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  19733256400                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        61054                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        70076                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      4086500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1916000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total      6002500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  13739930078                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  13739930078                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    517996000                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    517996000                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    267528500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    267528500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1182493                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1182493                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1648080000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1648080000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2097094000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2097094000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2203041000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2203041000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      4086500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1916000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2097094000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   3851121000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total   5954217500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      4086500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1916000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2097094000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   3851121000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  13739930078                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  19694147578                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    733130500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4264886500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4998017000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3246952500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3246952500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6103617500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6836748000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   4721367000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4721367000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    733130500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   7511839000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   8244969500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.027822                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.029698                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.028404                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  10824984500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11558115000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.027010                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.031207                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.028310                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.478697                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.478697                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.915633                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.915633                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.475877                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.475877                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.911860                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.911860                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.149988                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.149988                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.042186                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.042186                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.196440                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.196440                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.027822                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.029698                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.042186                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.179743                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.097324                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.027822                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.029698                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.042186                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.179743                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.148708                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.148708                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.043412                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.043412                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.196393                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.196393                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.027010                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.031207                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.043412                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.179231                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.097908                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.027010                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.031207                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.043412                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.179231                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.228360                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 17663.755459                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16790.909091                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 17380.530973                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56777.995843                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56777.995843                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20076.499059                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20076.499059                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14905.563852                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14905.563852                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       337249                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       337249                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39292.533993                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39292.533993                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43635.769676                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43635.769676                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23272.399877                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23272.399877                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 17663.755459                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16790.909091                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43635.769676                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28077.525415                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32050.824720                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 17663.755459                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16790.909091                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43635.769676                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28077.525415                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56777.995843                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46239.596402                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.228935                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        18575                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16807.017544                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 17971.556886                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56080.431658                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56080.431658                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20097.617754                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20097.617754                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14895.796214                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14895.796214                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 107499.363636                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 107499.363636                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40970.516581                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40970.516581                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43657.624649                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43657.624649                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23317.538103                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23317.538103                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker        18575                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16807.017544                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43657.624649                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28589.082892                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32523.378397                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker        18575                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16807.017544                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43657.624649                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28589.082892                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56080.431658                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46005.871762                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81260.308136                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 202031.572714                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165870.735431                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164937.138068                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164937.138068                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188761.945261                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165310.539933                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164398.725582                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164398.725582                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81260.308136                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 184131.753113                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 165501.816612                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 177301.806597                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 164936.854273                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq         64679                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      1685922                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        30913                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        19686                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback       869596                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict      1383128                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       312557                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        88259                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42246                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       111569                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           44                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           93                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       298532                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       285304                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1106585                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq       579491                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadReq         64646                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      1697156                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        30874                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        28719                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback       871288                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      1384656                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       292494                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        87584                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42065                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       111017                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           56                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           92                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       299003                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       286103                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1106493                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       579158                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3316089                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2519725                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        10102                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        22430                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          5868346                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     70857528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     84663704                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        14816                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        32924                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         155568972                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    1147635                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      4840235                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       1.218671                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.413345                       # Request fanout histogram
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3315880                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2563217                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        10051                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        22351                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          5911499                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     70851640                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     84881644                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        14612                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        32580                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         155780476                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    1106596                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      4822448                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       1.211081                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.408076                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1           3781818     78.13%     78.13% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2           1058417     21.87%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1           3804521     78.89%     78.89% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2           1017927     21.11%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       4840235                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    2418139995                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       4822448                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    2435282990                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    114234000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    113496000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   1668899500                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   1668761500                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1193519480                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1211060981                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.cpu0.toL2Bus.respLayer2.occupancy      6398000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     14203990                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     14212986                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -1314,58 +1311,60 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                     3364                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort                3364                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          665                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         2699                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples         3364                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0           3364    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total         3364                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         2594                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 10057.247494                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean  9203.479719                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  5035.039152                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191         1036     39.94%     39.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383         1440     55.51%     95.45% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575           55      2.12%     97.57% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-32767           56      2.16%     99.73% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::40960-49151            6      0.23%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::90112-98303            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         2594                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   1650887468                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     1650887468    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   1650887468                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         1937     74.67%     74.67% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          657     25.33%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         2594                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         3364                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks                     3357                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort                3357                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          663                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         2694                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples         3357                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0           3357    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total         3357                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         2587                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean  9934.866641                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean  9080.760096                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  4767.740714                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-4095           19      0.73%      0.73% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::4096-8191         1032     39.89%     40.63% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-12287         1082     41.82%     82.45% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::12288-16383          330     12.76%     95.21% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::20480-24575           64      2.47%     97.68% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-28671           39      1.51%     99.19% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::28672-32767           16      0.62%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::40960-45055            5      0.19%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         2587                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples   1655632468                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     1655632468    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total   1655632468                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         1932     74.68%     74.68% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          655     25.32%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         2587                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         3357                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         3364                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2594                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         3357                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2587                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2594                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total         5958                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2587                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total         5944                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     6310579                       # DTB read hits
-system.cpu1.dtb.read_misses                      2859                       # DTB read misses
-system.cpu1.dtb.write_hits                    4631996                       # DTB write hits
-system.cpu1.dtb.write_misses                      505                       # DTB write misses
+system.cpu1.dtb.read_hits                     3844486                       # DTB read hits
+system.cpu1.dtb.read_misses                      2847                       # DTB read misses
+system.cpu1.dtb.write_hits                    3369243                       # DTB write hits
+system.cpu1.dtb.write_misses                      510                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    2036                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    2034                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   323                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   293                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.dtb.perms_faults                      163                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 6313438                       # DTB read accesses
-system.cpu1.dtb.write_accesses                4632501                       # DTB write accesses
+system.cpu1.dtb.read_accesses                 3847333                       # DTB read accesses
+system.cpu1.dtb.write_accesses                3369753                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         10942575                       # DTB hits
-system.cpu1.dtb.misses                           3364                       # DTB misses
-system.cpu1.dtb.accesses                     10945939                       # DTB accesses
+system.cpu1.dtb.hits                          7213729                       # DTB hits
+system.cpu1.dtb.misses                           3357                       # DTB misses
+system.cpu1.dtb.accesses                      7217086                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1403,22 +1402,23 @@ system.cpu1.itb.walker.walkWaitTime::samples         1746
 system.cpu1.itb.walker.walkWaitTime::0           1746    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.itb.walker.walkWaitTime::total         1746                       # Table walker wait (enqueue to first request) latency
 system.cpu1.itb.walker.walkCompletionTime::samples         1107                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 10738.482385                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean  9680.648713                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  5669.589944                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191          351     31.71%     31.71% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287          484     43.72%     75.43% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383          202     18.25%     93.68% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479           20      1.81%     95.48% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::20480-24575            1      0.09%     95.57% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671           23      2.08%     97.65% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767           15      1.36%     99.01% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 10678.410117                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean  9623.001262                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  5682.967955                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191          356     32.16%     32.16% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287          499     45.08%     77.24% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383          181     16.35%     93.59% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479           17      1.54%     95.12% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575            1      0.09%     95.21% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671           30      2.71%     97.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767           12      1.08%     99.01% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::32768-36863            5      0.45%     99.46% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-45055            6      0.54%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-45055            5      0.45%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::45056-49151            1      0.09%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::total         1107                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples   1650350468                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     1650350468    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total   1650350468                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::samples   1655094468                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     1655094468    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total   1655094468                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walkPageSizes::4K          939     84.82%     84.82% # Table walker page sizes translated
 system.cpu1.itb.walker.walkPageSizes::1M          168     15.18%    100.00% # Table walker page sizes translated
 system.cpu1.itb.walker.walkPageSizes::total         1107                       # Table walker page sizes translated
@@ -1429,7 +1429,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1107                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1107                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin::total         2853                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    27093131                       # ITB inst hits
+system.cpu1.itb.inst_hits                    16180944                       # ITB inst hits
 system.cpu1.itb.inst_misses                      1746                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
@@ -1446,171 +1446,171 @@ system.cpu1.itb.domain_faults                       0                       # Nu
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                27094877                       # ITB inst accesses
-system.cpu1.itb.hits                         27093131                       # DTB hits
+system.cpu1.itb.inst_accesses                16182690                       # ITB inst accesses
+system.cpu1.itb.hits                         16180944                       # DTB hits
 system.cpu1.itb.misses                           1746                       # DTB misses
-system.cpu1.itb.accesses                     27094877                       # DTB accesses
-system.cpu1.numCycles                      5736521358                       # number of cpu cycles simulated
+system.cpu1.itb.accesses                     16182690                       # DTB accesses
+system.cpu1.numCycles                      5736568944                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   26153786                       # Number of instructions committed
-system.cpu1.committedOps                     32053131                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             28968286                       # Number of integer alu accesses
+system.cpu1.committedInsts                   15848207                       # Number of instructions committed
+system.cpu1.committedOps                     19293539                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             17383760                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                  1857                       # Number of float alu accesses
-system.cpu1.num_func_calls                    3299674                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      2947168                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    28968286                       # number of integer instructions
+system.cpu1.num_func_calls                     938177                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      1786282                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    17383760                       # number of integer instructions
 system.cpu1.num_fp_insts                         1857                       # number of float instructions
-system.cpu1.num_int_register_reads           54552282                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          20759353                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads           31469136                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          12170371                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                1341                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                516                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           117965505                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes            9826508                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     11178844                       # number of memory refs
-system.cpu1.num_load_insts                    6422284                       # Number of load instructions
-system.cpu1.num_store_insts                   4756560                       # Number of store instructions
-system.cpu1.num_idle_cycles              5660914446.273914                       # Number of idle cycles
-system.cpu1.num_busy_cycles              75606911.726086                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.013180                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.986820                       # Percentage of idle cycles
-system.cpu1.Branches                          6348758                       # Number of branches fetched
+system.cpu1.num_cc_register_reads            70461385                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes            6330901                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      7446495                       # number of memory refs
+system.cpu1.num_load_insts                    3955836                       # Number of load instructions
+system.cpu1.num_store_insts                   3490659                       # Number of store instructions
+system.cpu1.num_idle_cycles              5686521745.715384                       # Number of idle cycles
+system.cpu1.num_busy_cycles              50047198.284615                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.008724                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.991276                       # Percentage of idle cycles
+system.cpu1.Branches                          2803460                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                   66      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 21763864     65.97%     65.97% # Class of executed instruction
-system.cpu1.op_class::IntMult                   43243      0.13%     66.10% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     66.10% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc              3315      0.01%     66.11% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     66.11% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     66.11% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     66.11% # Class of executed instruction
-system.cpu1.op_class::MemRead                 6422284     19.47%     85.58% # Class of executed instruction
-system.cpu1.op_class::MemWrite                4756560     14.42%    100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 12144730     61.90%     61.90% # Class of executed instruction
+system.cpu1.op_class::IntMult                   26187      0.13%     62.03% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     62.03% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              3277      0.02%     62.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     62.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     62.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     62.05% # Class of executed instruction
+system.cpu1.op_class::MemRead                 3955836     20.16%     82.21% # Class of executed instruction
+system.cpu1.op_class::MemWrite                3490659     17.79%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  32989332                       # Class of executed instruction
+system.cpu1.op_class::total                  19620755                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2773                       # number of quiesce instructions executed
-system.cpu1.dcache.tags.replacements           185916                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          465.807736                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           10656106                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           186281                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            57.204471                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     104850302500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   465.807736                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.909781                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.909781                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          365                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          299                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3           66                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.712891                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         22064450                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        22064450                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      5988472                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        5988472                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      4434786                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       4434786                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        48931                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        48931                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        78766                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        78766                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        70801                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        70801                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     10423258                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        10423258                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     10472189                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       10472189                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       133050                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       133050                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data        91601                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        91601                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30372                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        30372                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17242                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        17242                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23381                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23381                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       224651                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        224651                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       255023                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       255023                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1943965500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   1943965500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2376775500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   2376775500                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    323304000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    323304000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    547906000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    547906000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2312500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2312500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   4320741000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   4320741000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   4320741000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   4320741000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      6121522                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      6121522                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      4526387                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      4526387                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        79303                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total        79303                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        96008                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        96008                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94182                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        94182                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     10647909                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     10647909                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     10727212                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     10727212                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.021735                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.021735                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.020237                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.020237                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.382987                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.382987                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.179589                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.179589                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.248253                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.248253                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.021098                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.021098                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.023773                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.023773                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14610.789177                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14610.789177                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25947.047521                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 25947.047521                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18750.956966                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18750.956966                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23433.813780                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23433.813780                       # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce                    2725                       # number of quiesce instructions executed
+system.cpu1.dcache.tags.replacements           186869                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          468.718276                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            6945303                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           187221                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            37.096816                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     104852682500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   468.718276                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.915465                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.915465                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          352                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          283                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           69                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.687500                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         14648138                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        14648138                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      3533706                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        3533706                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      3181686                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       3181686                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        48716                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        48716                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        78610                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        78610                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        70554                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        70554                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      6715392                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         6715392                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      6764108                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        6764108                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       133537                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       133537                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data        91347                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total        91347                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30388                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        30388                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17048                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        17048                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23285                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23285                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       224884                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        224884                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       255272                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       255272                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1938354000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   1938354000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2351393500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   2351393500                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    319800000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    319800000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    544967000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    544967000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2548000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2548000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   4289747500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   4289747500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   4289747500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   4289747500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      3667243                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      3667243                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      3273033                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      3273033                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        79104                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        79104                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        95658                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        95658                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        93839                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        93839                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      6940276                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      6940276                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      7019380                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      7019380                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.036413                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.036413                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.027909                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.027909                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.384153                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.384153                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.178218                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.178218                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.248138                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.248138                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.032403                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.032403                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.036367                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.036367                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14515.482600                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14515.482600                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25741.332501                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 25741.332501                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18758.798686                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18758.798686                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23404.208718                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23404.208718                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19233.126049                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 19233.126049                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16942.554201                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 16942.554201                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19075.378862                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 19075.378862                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16804.614294                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 16804.614294                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1619,147 +1619,147 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       116022                       # number of writebacks
-system.cpu1.dcache.writebacks::total           116022                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          266                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total          266                       # number of ReadReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12054                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12054                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data          266                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total          266                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data          266                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total          266                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       132784                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       132784                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        91601                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        91601                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        29597                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        29597                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5188                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5188                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23381                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23381                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       224385                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       224385                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       253982                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       253982                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        13773                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        13773                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        11227                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        11227                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        25000                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        25000                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1804303500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1804303500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2285174500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2285174500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    494107000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    494107000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     90251000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     90251000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    524565000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    524565000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2272500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2272500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4089478000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   4089478000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4583585000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   4583585000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2232716000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2232716000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1768357000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   1768357000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   4001073000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   4001073000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.021691                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.021691                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.020237                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.020237                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.373214                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.373214                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.054037                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.054037                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.248253                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.248253                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.021073                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.021073                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.023676                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.023676                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13588.259881                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13588.259881                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24947.047521                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24947.047521                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16694.496064                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16694.496064                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17396.106399                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17396.106399                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22435.524571                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22435.524571                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       116740                       # number of writebacks
+system.cpu1.dcache.writebacks::total           116740                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          267                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total          267                       # number of ReadReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        11810                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        11810                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data          267                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total          267                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data          267                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total          267                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       133270                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       133270                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        91347                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        91347                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        29613                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        29613                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5238                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5238                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23285                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23285                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       224617                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       224617                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       254230                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       254230                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         2508                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         2508                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2155                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2155                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         4663                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total         4663                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1799290500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1799290500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2260046500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2260046500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    487726000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    487726000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     90112000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     90112000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    521727000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    521727000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2503000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2503000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4059337000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4059337000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4547063000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   4547063000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    302228000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    302228000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    224553500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    224553500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    526781500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    526781500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036341                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036341                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027909                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027909                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.374355                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.374355                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.054758                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.054758                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.248138                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.248138                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.032364                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.032364                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.036218                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.036218                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13501.091769                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13501.091769                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24741.332501                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24741.332501                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16469.996285                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16469.996285                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17203.512791                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17203.512791                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22406.141293                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22406.141293                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18225.273525                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18225.273525                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18046.889150                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18046.889150                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162108.182676                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162108.182676                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157509.307918                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 157509.307918                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 160042.920000                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 160042.920000                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18072.260782                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18072.260782                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17885.627188                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17885.627188                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 120505.582137                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 120505.582137                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 104201.160093                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 104201.160093                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 112970.512546                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 112970.512546                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           505537                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          498.573002                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           26587077                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           506049                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            52.538543                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      84702248000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.573002                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973775                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.973775                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements           501529                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          498.573325                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           15678898                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           502041                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            31.230314                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      84707327000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.573325                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973776                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.973776                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          392                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3          117                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          387                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3          122                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::4            3                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         54692301                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        54692301                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     26587077                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       26587077                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     26587077                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        26587077                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     26587077                       # number of overall hits
-system.cpu1.icache.overall_hits::total       26587077                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       506049                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       506049                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       506049                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        506049                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       506049                       # number of overall misses
-system.cpu1.icache.overall_misses::total       506049                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4455517000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   4455517000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   4455517000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   4455517000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   4455517000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   4455517000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     27093126                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     27093126                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     27093126                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     27093126                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     27093126                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     27093126                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.018678                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.018678                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.018678                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.018678                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.018678                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.018678                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8804.516954                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  8804.516954                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8804.516954                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  8804.516954                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8804.516954                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  8804.516954                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         32863919                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        32863919                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     15678898                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       15678898                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     15678898                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        15678898                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     15678898                       # number of overall hits
+system.cpu1.icache.overall_hits::total       15678898                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       502041                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       502041                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       502041                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        502041                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       502041                       # number of overall misses
+system.cpu1.icache.overall_misses::total       502041                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4374235500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   4374235500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   4374235500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   4374235500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   4374235500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   4374235500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     16180939                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     16180939                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     16180939                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     16180939                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     16180939                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     16180939                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.031027                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.031027                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.031027                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.031027                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.031027                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.031027                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8712.904922                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  8712.904922                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8712.904922                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  8712.904922                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8712.904922                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  8712.904922                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1768,237 +1768,237 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       506049                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       506049                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       506049                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       506049                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       506049                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       506049                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       502041                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       502041                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       502041                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       502041                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       502041                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       502041                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          177                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          177                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4202492500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   4202492500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4202492500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   4202492500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4202492500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   4202492500                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     15340000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     15340000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     15340000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total     15340000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.018678                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.018678                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.018678                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.018678                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.018678                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.018678                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8304.516954                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8304.516954                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8304.516954                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  8304.516954                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8304.516954                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  8304.516954                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86666.666667                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86666.666667                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86666.666667                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86666.666667                       # average overall mshr uncacheable latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4123215000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   4123215000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4123215000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   4123215000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4123215000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   4123215000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     15225000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     15225000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     15225000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total     15225000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.031027                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.031027                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.031027                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.031027                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.031027                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.031027                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8212.904922                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8212.904922                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8212.904922                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8212.904922                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8212.904922                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8212.904922                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86016.949153                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86016.949153                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86016.949153                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86016.949153                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued       199458                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified       199458                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       199800                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       199800                       # number of prefetch candidates identified
 system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage        58862                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements           46506                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15029.734126                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs           1265349                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           61182                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           20.681720                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage        61752                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements           45885                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       14962.501141                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           1260771                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           60629                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           20.794851                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  8657.593794                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     3.281679                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.079815                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3148.961374                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2173.187241                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1044.630222                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.528418                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000200                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_blocks::writebacks  8945.992983                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     3.872865                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.082863                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  2870.067957                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2148.313714                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   992.170760                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.546020                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000236                       # Average percentage of cache occupancy
 system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000127                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.192197                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.132641                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.063759                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.917342                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1197                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           19                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13460                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            6                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           35                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         1156                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.175175                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.131123                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.060557                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.913239                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1179                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           17                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13548                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            2                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           28                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         1149                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           13                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          274                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1596                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        11590                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.073059                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001160                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.821533                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        23794594                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       23794594                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         3091                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1709                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total          4800                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks       116022                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total       116022                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1472                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total         1472                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data          842                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total          842                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        27319                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        27319                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       492294                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total       492294                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        99296                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total        99296                       # number of ReadSharedReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         3091                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1709                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       492294                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data       126615                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total         623709                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         3091                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1709                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst       492294                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data       126615                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total        623709                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          314                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          266                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total          580                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28095                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        28095                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22537                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        22537                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           12                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          290                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1569                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        11689                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.071960                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001038                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.826904                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        23682241                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       23682241                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         3041                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1687                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total          4728                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks       116740                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total       116740                       # number of Writeback hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1450                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total         1450                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data          871                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total          871                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data        27883                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total        27883                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       488673                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total       488673                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data       100414                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total       100414                       # number of ReadSharedReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         3041                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1687                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst       488673                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data       128297                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total         621698                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         3041                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1687                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst       488673                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data       128297                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total        621698                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          323                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          278                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total          601                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        27681                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total        27681                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22412                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total        22412                       # number of SCUpgradeReq misses
 system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            2                       # number of SCUpgradeFailReq misses
 system.cpu1.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        34715                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total        34715                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        13755                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total        13755                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        68273                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total        68273                       # number of ReadSharedReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          314                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker          266                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst        13755                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data       102988                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total       117323                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          314                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker          266                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst        13755                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data       102988                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total       117323                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      6334500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5311000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total     11645500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    538209000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total    538209000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    450797500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    450797500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2212500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2212500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1336972500                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   1336972500                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    492390500                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total    492390500                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1491495000                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1491495000                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      6334500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5311000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst    492390500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data   2828467500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total   3332503500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      6334500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5311000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst    492390500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data   2828467500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total   3332503500                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         3405                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         1975                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total         5380                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks       116022                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total       116022                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29567                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        29567                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23379                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        23379                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data        34333                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total        34333                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        13368                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total        13368                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        67707                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total        67707                       # number of ReadSharedReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          323                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker          278                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst        13368                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data       102040                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total       116009                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          323                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker          278                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst        13368                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data       102040                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total       116009                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      6494000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5572000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total     12066000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    531615500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total    531615500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    445738000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    445738000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2435500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2435500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1319690000                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total   1319690000                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    440659500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total    440659500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1471913000                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1471913000                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      6494000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5572000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst    440659500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data   2791603000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total   3244328500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      6494000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5572000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst    440659500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data   2791603000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total   3244328500                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         3364                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         1965                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total         5329                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks       116740                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total       116740                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29131                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total        29131                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23283                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total        23283                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
 system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        62034                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total        62034                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       506049                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total       506049                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       167569                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total       167569                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         3405                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         1975                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst       506049                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data       229603                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total       741032                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         3405                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         1975                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst       506049                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data       229603                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total       741032                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.092217                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.134684                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.107807                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.950215                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.950215                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.963985                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.963985                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        62216                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total        62216                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       502041                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total       502041                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       168121                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total       168121                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         3364                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         1965                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst       502041                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data       230337                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total       737707                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         3364                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         1965                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst       502041                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data       230337                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total       737707                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.096017                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.141476                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.112779                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.950225                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.950225                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.962591                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.962591                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.559612                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.559612                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.027181                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.027181                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.407432                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.407432                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.092217                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.134684                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.027181                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.448548                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.158324                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.092217                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.134684                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.027181                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.448548                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.158324                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20173.566879                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19966.165414                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20078.448276                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19156.753871                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19156.753871                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20002.551360                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20002.551360                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      1106250                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1106250                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38512.818666                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38512.818666                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35797.201018                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35797.201018                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 21846.044556                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 21846.044556                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20173.566879                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19966.165414                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35797.201018                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27464.049210                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 28404.520000                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20173.566879                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19966.165414                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35797.201018                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27464.049210                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 28404.520000                       # average overall miss latency
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.551836                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.551836                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.026627                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.026627                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.402728                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.402728                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.096017                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.141476                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.026627                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.443003                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.157256                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.096017                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.141476                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.026627                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.443003                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.157256                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20105.263158                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20043.165468                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20076.539101                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19205.068459                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19205.068459                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19888.363377                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19888.363377                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      1217750                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1217750                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38437.945999                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38437.945999                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 32963.756732                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 32963.756732                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 21739.450869                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 21739.450869                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20105.263158                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20043.165468                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32963.756732                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27357.928263                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 27966.179348                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20105.263158                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20043.165468                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32963.756732                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27357.928263                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 27966.179348                       # average overall miss latency
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -2007,211 +2007,211 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        30696                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           30696                       # number of writebacks
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data           90                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total           90                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data           90                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total           90                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data           90                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total           90                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          314                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          266                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total          580                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks         2031                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::total         2031                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        23725                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total        23725                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        28095                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28095                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22537                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22537                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.writebacks::writebacks        30382                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           30382                       # number of writebacks
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data           91                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total           91                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data           91                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total           91                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data           91                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total           91                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          323                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          278                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total          601                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks         2052                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::total         2052                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        24074                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total        24074                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        27681                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        27681                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22412                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22412                       # number of SCUpgradeReq MSHR misses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeFailReq MSHR misses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        34625                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        34625                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        13755                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        13755                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        68273                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        68273                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          314                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          266                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        13755                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data       102898                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total       117233                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          314                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          266                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        13755                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data       102898                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        23725                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total       140958                       # number of overall MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        34242                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total        34242                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        13368                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        13368                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        67707                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        67707                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          323                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          278                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        13368                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data       101949                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total       115918                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          323                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          278                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        13368                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data       101949                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        24074                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total       139992                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        13773                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        13950                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        11227                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        11227                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         2508                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         2685                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2155                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2155                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        25000                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        25177                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      4450500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3715000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total      8165500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    839425646                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    839425646                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    455073500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    455073500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    349086500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    349086500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1972500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1972500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1119618000                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1119618000                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    409860500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    409860500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1081857000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1081857000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      4450500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3715000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    409860500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2201475000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   2619501000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      4450500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3715000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    409860500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2201475000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    839425646                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   3458926646                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14012500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2122532000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2136544500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1684154500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1684154500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     14012500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   3806686500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   3820699000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.092217                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.134684                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.107807                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         4663                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         4840                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      4556000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3904000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total      8460000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    852211217                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    852211217                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    446564500                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    446564500                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    346991500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    346991500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2165500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2165500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1103967000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1103967000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    360451500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    360451500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1065671000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1065671000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      4556000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3904000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    360451500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2169638000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   2538549500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      4556000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3904000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    360451500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2169638000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    852211217                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   3390760717                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13897500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    282164000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    296061500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    208391000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    208391000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     13897500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    490555000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    504452500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.096017                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.141476                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.112779                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.950215                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.950215                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.963985                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.963985                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.950225                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.950225                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.962591                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.962591                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.558162                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.558162                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.027181                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.027181                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.407432                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.407432                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.092217                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.134684                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.027181                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.448156                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.158202                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.092217                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.134684                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.027181                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.448156                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.550373                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.550373                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.026627                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.026627                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.402728                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.402728                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.096017                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.141476                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.026627                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.442608                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.157133                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.096017                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.141476                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.026627                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.442608                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.190219                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14173.566879                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13966.165414                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14078.448276                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35381.481391                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35381.481391                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16197.668624                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16197.668624                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15489.483960                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15489.483960                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       986250                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       986250                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32335.537906                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32335.537906                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29797.201018                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29797.201018                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 15846.044556                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 15846.044556                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14173.566879                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13966.165414                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29797.201018                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21394.730704                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22344.399614                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14173.566879                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13966.165414                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29797.201018                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21394.730704                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35381.481391                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24538.704054                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 79166.666667                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154108.182676                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 153157.311828                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150009.307918                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150009.307918                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 79166.666667                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 152267.460000                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 151753.544902                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.189766                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14105.263158                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14043.165468                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14076.539101                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35399.651782                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35399.651782                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16132.527727                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16132.527727                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15482.397823                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15482.397823                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data      1082750                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      1082750                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32240.143683                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32240.143683                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26963.756732                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26963.756732                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 15739.450869                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 15739.450869                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14105.263158                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14043.165468                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26963.756732                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21281.601585                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21899.528115                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14105.263158                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14043.165468                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26963.756732                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21281.601585                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35399.651782                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24221.103470                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78516.949153                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112505.582137                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 110264.990689                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 96701.160093                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 96701.160093                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78516.949153                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 105201.586961                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 104225.723140                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq         53469                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp       734633                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        30913                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        11227                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback       478531                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict       680350                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq        29761                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        73690                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41411                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        85868                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           55                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           93                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        84408                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        66733                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq       506049                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq       504061                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadReq         53417                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp       719726                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        30874                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         2155                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback       479672                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict       677908                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        29213                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        72925                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41207                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        85236                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           49                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           92                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        84437                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        66918                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq       502041                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       506824                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1509072                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       874243                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         5299                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side         9468                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          2398082                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     32387844                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24934344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7900                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        13620                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          57343708                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    1094784                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      2530004                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       1.405048                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.490902                       # Request fanout histogram
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1497175                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       834504                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         5289                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side         9415                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          2346383                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     32131332                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24936310                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7860                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        13456                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          57088958                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    1117653                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      2525896                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       1.414848                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.492696                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1           1505230     59.50%     59.50% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2           1024774     40.50%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1           1478032     58.52%     58.52% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2           1047864     41.48%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       2530004                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy     878944000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       2525896                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy     861521000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     80122000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     79810000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy    759250500                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy    753238500                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    390308000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    375346000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.cpu1.toL2Bus.respLayer2.occupancy      3324000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy      6063998                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy      6051499                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                31015                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               31015                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               59422                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              59422                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56602                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::WriteReq               59423                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              59423                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56604                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
@@ -2232,11 +2232,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       107916                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       107918                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72958                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total        72958                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  180874                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71546                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  180876                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71548                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
@@ -2257,11 +2257,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       162796                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       162798                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321272                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321272                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2484068                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             40091000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2484070                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             40093000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -2301,23 +2301,23 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           187549442                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           187554192                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            84718000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            84719000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36782000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36445                       # number of replacements
-system.iocache.tags.tagsinuse               14.390664                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse               14.390549                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36461                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         288350117000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.390664                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.899417                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.899417                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         288373025000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.390549                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.899409                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.899409                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -2331,14 +2331,14 @@ system.iocache.demand_misses::realview.ide          255                       #
 system.iocache.demand_misses::total               255                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          255                       # number of overall misses
 system.iocache.overall_misses::total              255                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     32656876                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     32656876                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4281964566                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4281964566                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     32656876                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     32656876                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     32656876                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     32656876                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     32657877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     32657877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4277536315                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4277536315                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     32657877                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     32657877                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     32657877                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     32657877                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          255                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            255                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -2355,19 +2355,19 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 128066.180392                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 128066.180392                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118207.944070                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118207.944070                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 128066.180392                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 128066.180392                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 128066.180392                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 128066.180392                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           265                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 128070.105882                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 128070.105882                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118085.697742                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118085.697742                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 128070.105882                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 128070.105882                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 128070.105882                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 128070.105882                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             7                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs   132.500000                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     3.500000                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -2381,14 +2381,14 @@ system.iocache.demand_mshr_misses::realview.ide          255
 system.iocache.demand_mshr_misses::total          255                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          255                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          255                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     19906876                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     19906876                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2470764566                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2470764566                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     19906876                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     19906876                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     19906876                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     19906876                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     19907877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     19907877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2466336315                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2466336315                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     19907877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     19907877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     19907877                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     19907877                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -2397,303 +2397,289 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78066.180392                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 78066.180392                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68207.944070                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68207.944070                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 78066.180392                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 78066.180392                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 78066.180392                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 78066.180392                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78070.105882                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 78070.105882                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68085.697742                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68085.697742                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 78070.105882                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 78070.105882                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 78070.105882                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 78070.105882                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   130439                       # number of replacements
-system.l2c.tags.tagsinuse                63983.082008                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     387954                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   194793                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     1.991622                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   130014                       # number of replacements
+system.l2c.tags.tagsinuse                63961.093315                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     392369                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   194378                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.018587                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   12138.175325                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     3.910023                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.041062                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     7215.667264                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2903.196215                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37504.021978                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.955808                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1528.247767                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      561.168860                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2127.697705                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.185214                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000060                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   12058.686901                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     3.020417                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.045313                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     7839.345721                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2905.478880                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37500.688357                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      950.717991                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      465.629828                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2237.479906                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.184001                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000046                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.110102                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.044299                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.572266                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.023319                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.008563                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.032466                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.976304                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        32301                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023            7                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        32046                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          164                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         4667                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        27470                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          231                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         1924                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        29877                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.492874                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000107                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.488983                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  5300600                       # Number of tag accesses
-system.l2c.tags.data_accesses                 5300600                       # Number of data accesses
-system.l2c.Writeback_hits::writebacks          225955                       # number of Writeback hits
-system.l2c.Writeback_hits::total               225955                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            2137                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             661                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                2798                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           135                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data           145                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               280                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data             3821                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data             1461                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                 5282                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker           91                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker           51                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst        29278                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data        45470                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        44948                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           27                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker           27                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst        11381                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data         8374                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         5310                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           144957                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker            91                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker            51                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst               29278                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data               49291                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher        44948                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker            27                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker            27                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst               11381                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data                9835                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher         5310                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  150239                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker           91                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker           51                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst              29278                       # number of overall hits
-system.l2c.overall_hits::cpu0.data              49291                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher        44948                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker           27                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker           27                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst              11381                       # number of overall hits
-system.l2c.overall_hits::cpu1.data               9835                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher         5310                       # number of overall hits
-system.l2c.overall_hits::total                 150239                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data          8391                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          2650                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             11041                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          492                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         1207                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1699                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          11580                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data           8214                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total              19794                       # number of ReadExReq misses
+system.l2c.tags.occ_percent::cpu0.inst       0.119619                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.044334                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.572215                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.014507                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.007105                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.034141                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.975969                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        32308                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        32052                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          225                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3         4677                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4        27406                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          276                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         1819                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        29951                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.492981                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.489075                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  5325589                       # Number of tag accesses
+system.l2c.tags.data_accesses                 5325589                       # Number of data accesses
+system.l2c.Writeback_hits::writebacks          226708                       # number of Writeback hits
+system.l2c.Writeback_hits::total               226708                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data            2021                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             691                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                2712                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data           141                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data           160                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total               301                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data             3915                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data             1420                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total                 5335                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker           81                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker           55                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst        30090                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data        45920                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        45888                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           41                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker           34                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst        11628                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data         8389                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         5369                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total           147495                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker            81                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker            55                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst               30090                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data               49835                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher        45888                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker            41                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker            34                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst               11628                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data                9809                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher         5369                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                  152830                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker           81                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker           55                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst              30090                       # number of overall hits
+system.l2c.overall_hits::cpu0.data              49835                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher        45888                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker           41                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker           34                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst              11628                       # number of overall hits
+system.l2c.overall_hits::cpu1.data               9809                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher         5369                       # number of overall hits
+system.l2c.overall_hits::total                 152830                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data          8373                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          2542                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             10915                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          478                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data         1195                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            1673                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          11367                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data           8062                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total              19429                       # number of ReadExReq misses
 system.l2c.ReadSharedReq_misses::cpu0.dtb.walker            7                       # number of ReadSharedReq misses
 system.l2c.ReadSharedReq_misses::cpu0.itb.walker            2                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        17402                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data         8820                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       134398                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker            1                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst         2367                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data          942                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         6249                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         170188                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.inst        17941                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data         8815                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       134305                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.inst         1735                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data          851                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         6450                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         170106                       # number of ReadSharedReq misses
 system.l2c.demand_misses::cpu0.dtb.walker            7                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             17402                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             20400                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       134398                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              2367                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data              9156                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher         6249                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                189982                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             17941                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             20182                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.l2cache.prefetcher       134305                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              1735                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data              8913                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.l2cache.prefetcher         6450                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                189535                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.dtb.walker            7                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            17402                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            20400                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       134398                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             2367                       # number of overall misses
-system.l2c.overall_misses::cpu1.data             9156                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher         6249                       # number of overall misses
-system.l2c.overall_misses::total               189982                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data      8210000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      2280000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     10490000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1358000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1106500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      2464500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   1018907000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data    666031500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   1684938500                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker       606500                       # number of ReadSharedReq miss cycles
+system.l2c.overall_misses::cpu0.inst            17941                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            20182                       # number of overall misses
+system.l2c.overall_misses::cpu0.l2cache.prefetcher       134305                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             1735                       # number of overall misses
+system.l2c.overall_misses::cpu1.data             8913                       # number of overall misses
+system.l2c.overall_misses::cpu1.l2cache.prefetcher         6450                       # number of overall misses
+system.l2c.overall_misses::total               189535                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data      7787500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data      2669500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     10457000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1236500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data       708000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      1944500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   1092065500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data    658722000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   1750787500                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker       816000                       # number of ReadSharedReq miss cycles
 system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       166000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   1402771500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data    762849500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  13087577967                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker        82500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst    194012000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data     84119500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher    729023182                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  16261208649                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker       606500                       # number of demand (read+write) miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.inst   1444848500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data    766909500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  12944226902                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst    144716500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data     75717500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher    743765397                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  16121166299                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker       816000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu0.itb.walker       166000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   1402771500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   1781756500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  13087577967                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker        82500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    194012000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data    750151000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    729023182                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     17946147149                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker       606500                       # number of overall miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   1444848500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   1858975000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  12944226902                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    144716500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data    734439500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    743765397                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     17871953799                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker       816000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu0.itb.walker       166000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   1402771500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   1781756500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  13087577967                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker        82500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    194012000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data    750151000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    729023182                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    17946147149                       # number of overall miss cycles
-system.l2c.Writeback_accesses::writebacks       225955                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           225955                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        10528                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         3311                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           13839                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          627                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data         1352                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1979                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data        15401                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data         9675                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total            25076                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker           98                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           53                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst        46680                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data        54290                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       179346                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           28                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           27                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst        13748                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data         9316                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        11559                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total       315145                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker           98                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker           53                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst           46680                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data           69691                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       179346                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker           28                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker           27                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst           13748                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data           18991                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher        11559                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              340221                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker           98                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker           53                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst          46680                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data          69691                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       179346                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker           28                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker           27                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst          13748                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          18991                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher        11559                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             340221                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.797017                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.800362                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.797818                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.784689                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.892751                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.858514                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.751899                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.848992                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.789360                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.071429                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.037736                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.372793                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.162461                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.749378                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.035714                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.172170                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.101116                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.540618                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.540031                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.071429                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.037736                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.372793                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.292721                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.749378                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.035714                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.172170                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.482123                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.540618                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.558408                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.071429                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.037736                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.372793                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.292721                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.749378                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.035714                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.172170                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.482123                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.540618                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.558408                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   978.429269                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   860.377358                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   950.095100                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2760.162602                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   916.735708                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  1450.559152                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87988.514680                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81084.915997                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 85123.699101                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 86642.857143                       # average ReadSharedReq miss latency
+system.l2c.overall_miss_latency::cpu0.inst   1444848500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   1858975000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  12944226902                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    144716500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data    734439500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    743765397                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    17871953799                       # number of overall miss cycles
+system.l2c.Writeback_accesses::writebacks       226708                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           226708                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        10394                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         3233                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           13627                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          619                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data         1355                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          1974                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data        15282                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data         9482                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            24764                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker           88                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           57                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst        48031                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data        54735                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       180193                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           41                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           34                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst        13363                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data         9240                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        11819                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       317601                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker           88                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker           57                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst           48031                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data           70017                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       180193                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker           41                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker           34                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst           13363                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           18722                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher        11819                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              342365                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker           88                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker           57                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst          48031                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data          70017                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       180193                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker           41                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker           34                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst          13363                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          18722                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher        11819                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             342365                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.805561                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.786267                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.800983                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.772213                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.881919                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.847518                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.743816                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.850243                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.784566                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.079545                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.035088                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.373530                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.161049                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.745340                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.129836                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.092100                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.545731                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.535597                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.079545                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.035088                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.373530                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.288244                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.745340                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.129836                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.476071                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.545731                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.553605                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.079545                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.035088                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.373530                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.288244                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.745340                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.129836                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.476071                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.545731                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.553605                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   930.072853                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1050.157356                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   958.039395                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2586.820084                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   592.468619                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  1162.283323                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 96073.326295                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81707.020590                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 90112.074734                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 116571.428571                       # average ReadSharedReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker        83000                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 80609.786231                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 86490.873016                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 97379.261351                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker        82500                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 81965.356992                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89298.832272                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 116662.375100                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 95548.503120                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86642.857143                       # average overall miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 80533.331475                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87000.510493                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96379.337344                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 83410.086455                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 88974.735605                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 115312.464651                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 94771.297303                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 116571.428571                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker        83000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 80609.786231                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 87341.004902                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 97379.261351                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        82500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 81965.356992                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 81929.991263                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 116662.375100                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 94462.355113                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86642.857143                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 80533.331475                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 92110.544049                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96379.337344                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 83410.086455                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 82400.931224                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 115312.464651                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 94293.686121                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 116571.428571                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker        83000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 80609.786231                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 87341.004902                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 97379.261351                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        82500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 81965.356992                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 81929.991263                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 116662.375100                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 94462.355113                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 80533.331475                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 92110.544049                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96379.337344                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 83410.086455                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 82400.931224                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 115312.464651                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 94293.686121                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2702,271 +2688,259 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              100321                       # number of writebacks
-system.l2c.writebacks::total                   100321                       # number of writebacks
+system.l2c.writebacks::writebacks               99996                       # number of writebacks
+system.l2c.writebacks::total                    99996                       # number of writebacks
 system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            2                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            4                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total            6                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst           10                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total           12                       # number of ReadSharedReq MSHR hits
 system.l2c.demand_mshr_hits::cpu0.inst              2                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                  6                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst             10                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 12                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu0.inst             2                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                 6                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks         3050                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total         3050                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         8391                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         2650                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        11041                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          492                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1207                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1699                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        11580                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         8214                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         19794                       # number of ReadExReq MSHR misses
+system.l2c.overall_mshr_hits::cpu1.inst            10                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                12                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks         2923                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total         2923                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         8373                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         2542                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        10915                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          478                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1195                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1673                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        11367                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data         8062                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         19429                       # number of ReadExReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker            7                       # number of ReadSharedReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        17400                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data         8820                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       134398                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         2363                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data          942                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         6249                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       170182                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        17939                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data         8815                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       134305                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         1725                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data          851                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         6450                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total       170094                       # number of ReadSharedReq MSHR misses
 system.l2c.demand_mshr_misses::cpu0.dtb.walker            7                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        17400                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        20400                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       134398                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         2363                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data         9156                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         6249                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           189976                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        17939                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        20182                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       134305                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         1725                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data         8913                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         6450                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           189523                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu0.dtb.walker            7                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        17400                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        20400                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       134398                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         2363                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data         9156                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         6249                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          189976                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        17939                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        20182                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       134305                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         1725                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data         8913                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         6450                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          189523                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        21110                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data        32335                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data        13769                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        44078                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        19686                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data        11227                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        30913                       # number of WriteReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data         2504                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        44038                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        28719                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2155                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        30874                       # number of WriteReq MSHR uncacheable
 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        40796                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        61054                       # number of overall MSHR uncacheable misses
 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        24996                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        74991                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    174583000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     55064000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    229647000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     10311000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     25083500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     35394500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    903107000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    583891500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   1486998500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker       536500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data         4659                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        74912                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    174263500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     52800500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    227064000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     10023500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     24840000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     34863500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    978395500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    578102000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   1556497500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker       746000                       # number of ReadSharedReq MSHR miss cycles
 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       146000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1228508000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    674649500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  11743597967                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker        72500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    170183500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data     74699500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    666533182                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  14558926649                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       536500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1265389000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    678759500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  11601176902                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    126976000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data     67207500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    679265397                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  14419666299                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       746000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       146000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   1228508000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   1577756500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  11743597967                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        72500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    170183500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    658591000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    666533182                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  16045925149                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       536500                       # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   1265389000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   1657155000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  11601176902                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    126976000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    645309500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    679265397                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  15976163799                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       746000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       146000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   1228508000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   1577756500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  11743597967                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        72500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    170183500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    658591000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    666533182                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  16045925149                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   1265389000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   1657155000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  11601176902                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    126976000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    645309500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    679265397                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  15976163799                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    570734000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3884897500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     10826500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1874631500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   6341089500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2912289500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1493293500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   4405583000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5521577000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     10711500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    237033000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   6340055500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4233141500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    171755500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   4404897000                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    570734000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   6797187000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     10826500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3367925000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  10746672500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9754718500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     10711500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    408788500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  10744952500                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.797017                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.800362                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.797818                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.784689                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.892751                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.858514                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.751899                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.848992                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.789360                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.071429                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.037736                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.372751                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.162461                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.749378                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.035714                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.171880                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.101116                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.540618                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.540012                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.071429                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.037736                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.372751                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.292721                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.749378                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.035714                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.171880                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.482123                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.540618                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.558390                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.071429                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.037736                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.372751                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.292721                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.749378                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.035714                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.171880                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.482123                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.540618                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.558390                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20805.982600                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20778.867925                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20799.474685                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20957.317073                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20781.690141                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20832.548558                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77988.514680                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71084.915997                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 75123.699101                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 76642.857143                       # average ReadSharedReq mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.805561                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.786267                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.800983                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.772213                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.881919                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.847518                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.743816                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.850243                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.784566                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.079545                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.035088                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.373488                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.161049                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.745340                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.129088                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.092100                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.545731                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.535559                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.079545                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.035088                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.373488                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.288244                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.745340                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.129088                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.476071                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.545731                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.553570                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.079545                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.035088                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.373488                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.288244                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.745340                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.129088                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.476071                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.545731                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.553570                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20812.552251                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20771.243116                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20802.931745                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20969.665272                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20786.610879                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20838.912134                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 86073.326295                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71707.020590                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 80112.074734                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 106571.428571                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker        73000                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 70603.908046                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 76490.873016                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87379.261351                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker        72500                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72020.101566                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79298.832272                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 106662.375100                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85549.157073                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76642.857143                       # average overall mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 70538.435810                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77000.510493                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86379.337344                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73609.275362                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78974.735605                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105312.464651                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 84774.691047                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 106571.428571                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        73000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70603.908046                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77341.004902                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87379.261351                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        72500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72020.101566                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71929.991263                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 106662.375100                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 84462.906625                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76642.857143                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70538.435810                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82110.544049                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86379.337344                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73609.275362                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72400.931224                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105312.464651                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 84296.701714                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 106571.428571                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        73000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70603.908046                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77341.004902                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87379.261351                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        72500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72020.101566                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71929.991263                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 106662.375100                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 84462.906625                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70538.435810                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82110.544049                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86379.337344                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73609.275362                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72400.931224                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105312.464651                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 84296.701714                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63260.252716                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184031.146376                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61166.666667                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136148.703610                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 143860.644766                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147937.087270                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133009.129776                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142515.543622                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170761.620535                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60516.949153                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 94661.741214                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 143967.834597                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147398.638532                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 79700.928074                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142673.349744                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63260.252716                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 166614.055300                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61166.666667                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 134738.558169                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 143306.163406                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 159771.980542                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60516.949153                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 87741.682765                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 143434.329613                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               44078                       # Transaction distribution
-system.membus.trans_dist::ReadResp             214515                       # Transaction distribution
-system.membus.trans_dist::WriteReq              30913                       # Transaction distribution
-system.membus.trans_dist::WriteResp             30913                       # Transaction distribution
-system.membus.trans_dist::Writeback            136511                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            15728                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            75283                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          40251                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           12822                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            4                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             40262                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            19712                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        170437                       # Transaction distribution
+system.membus.trans_dist::ReadReq               44038                       # Transaction distribution
+system.membus.trans_dist::ReadResp             214387                       # Transaction distribution
+system.membus.trans_dist::WriteReq              30874                       # Transaction distribution
+system.membus.trans_dist::WriteResp             30874                       # Transaction distribution
+system.membus.trans_dist::Writeback            136186                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            15507                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            74602                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          39992                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           12685                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            7                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             39841                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            19332                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        170349                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107916                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107918                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13732                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       672670                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       794352                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13572                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       670072                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       791596                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108921                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       108921                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 903273                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162796                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total                 900517                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162798                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27464                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18608200                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     18798528                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18557448                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     18747458                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                21115648                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           123870                       # Total snoops (count)
-system.membus.snoop_fanout::samples            589976                       # Request fanout histogram
+system.membus.pkt_size::total                21064578                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           123030                       # Total snoops (count)
+system.membus.snoop_fanout::samples            587901                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  589976    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  587901    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              589976                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            88273000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              587901                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            88280499                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               19000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            11464500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            11327500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1021914451                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           983138119                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1141120383                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1138149025                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64390592                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64374606                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -2999,46 +2973,46 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq              44082                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            479204                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             30913                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            30913                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           362509                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict           82484                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           77999                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         40531                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         118530                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           93                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           93                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            51218                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           51218                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       435137                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq              44042                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            480570                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             30874                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            30874                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           362932                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict           82945                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           77217                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         40293                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         117510                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           92                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           92                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            50721                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           50721                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       436543                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1069100                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       319954                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1389054                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     31596740                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      4900924                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               36497664                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          452334                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          1194337                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.170309                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.375904                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1115711                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       276298                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1392009                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     31905816                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      4776938                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               36682754                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          449881                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          1195846                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.169748                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.375411                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 990931     82.97%     82.97% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 203406     17.03%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 992854     83.03%     83.03% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 202992     16.97%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            1194337                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          799819351                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            1195846                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          812251839                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           360000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         609335323                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         627943021                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         239074701                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         221271516                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
index 65214b87e1b13e92eb5b171e6d90ddf382cc0889..c7177147a35d71a2827b0a9a2bc73cbd750a16c1 100644 (file)
@@ -4,10 +4,10 @@ sim_seconds                                  0.000018                       # Nu
 sim_ticks                                    17777000                       # Number of ticks simulated
 final_tick                                   17777000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  63568                       # Simulator instruction rate (inst/s)
-host_op_rate                                    74435                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              246000775                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 307848                       # Number of bytes of host memory used
+host_inst_rate                                  63242                       # Simulator instruction rate (inst/s)
+host_op_rate                                    74054                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              244740900                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 307828                       # Number of bytes of host memory used
 host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
@@ -94,16 +94,16 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       224                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       225                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                       126                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        30                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        13                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        12                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
@@ -204,12 +204,12 @@ system.physmem.bytesPerActivate::768-895            3      5.08%     79.66% # By
 system.physmem.bytesPerActivate::896-1023            2      3.39%     83.05% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151           10     16.95%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total             59                       # Bytes accessed per row activation
-system.physmem.totQLat                        3256492                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  10887742                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        3130500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  10761750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2035000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8001.21                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        7691.65                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26751.21                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  26441.65                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                        1465.26                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                     1465.26                       # Average system read bandwidth in MiByte/s
@@ -218,7 +218,7 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                          11.45                       # Data bus utilization in percentage
 system.physmem.busUtilRead                      11.45                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.77                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.81                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
 system.physmem.readRowHits                        340                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
@@ -231,28 +231,28 @@ system.physmem_0.preEnergy                     160875                       # En
 system.physmem_0.readEnergy                   2043600                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               10756755                       # Energy for active background per rank (pJ)
+system.physmem_0.actBackEnergy               10766160                       # Energy for active background per rank (pJ)
 system.physmem_0.preBackEnergy                  63750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 14336940                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              905.538607                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE         334000                       # Time in different power states
+system.physmem_0.totalEnergy                 14346345                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              905.346375                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE         321250                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        15275500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        15288250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.physmem_1.actEnergy                     128520                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                      70125                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                    795600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               10156545                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 590250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 12758160                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              805.820938                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE         942000                       # Time in different power states
+system.physmem_1.actBackEnergy               10149705                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 596250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 12757320                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              805.767883                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE         952000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        14384250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        14374250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.branchPred.lookups                    2336                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1386                       # Number of conditional branches predicted
@@ -384,80 +384,80 @@ system.cpu.workload.num_syscalls                   13                       # Nu
 system.cpu.numCycles                            35555                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               6172                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles               6171                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.Insts                          11259                       # Number of instructions fetch has processed
 system.cpu.fetch.Branches                        2336                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches                731                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          7501                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.Cycles                          7640                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.SquashCycles                    1059                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                  155                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           303                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles          318                       # Number of stall cycles due to full MSHR
 system.cpu.fetch.CacheLines                      3825                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                   176                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              14978                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.878021                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.210560                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples              15116                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.870204                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.208015                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     8782     58.63%     58.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     2458     16.41%     75.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      521      3.48%     78.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                     3217     21.48%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     8919     59.00%     59.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     2458     16.26%     75.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      521      3.45%     78.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                     3218     21.29%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                14978                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total                15116                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.branchRate                  0.065701                       # Number of branch fetches per cycle
 system.cpu.fetch.rate                        0.316664                       # Number of inst fetches per cycle
 system.cpu.decode.IdleCycles                     5920                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  3520                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      5039                       # Number of cycles decode is running
+system.cpu.decode.BlockedCycles                  3659                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      5038                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles                   131                       # Number of cycles decode is unblocking
 system.cpu.decode.SquashCycles                    368                       # Number of cycles decode is squashing
 system.cpu.decode.BranchResolved                  329                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                   164                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                   9859                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  1620                       # Number of squashed instructions handled by decode
+system.cpu.decode.DecodedInsts                   9862                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  1622                       # Number of squashed instructions handled by decode
 system.cpu.rename.SquashCycles                    368                       # Number of cycles rename is squashing
 system.cpu.rename.IdleCycles                     6989                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     960                       # Number of cycles rename is blocking
+system.cpu.rename.BlockCycles                     961                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles           1965                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      4095                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   601                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                   8880                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                   409                       # Number of squashed instructions processed by rename
+system.cpu.rename.RunCycles                      4094                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   739                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                   8883                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                   411                       # Number of squashed instructions processed by rename
 system.cpu.rename.ROBFullEvents                    15                       # Number of times rename has blocked due to ROB full
 system.cpu.rename.IQFullEvents                      1                       # Number of times rename has blocked due to IQ full
 system.cpu.rename.LQFullEvents                      9                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                    527                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands                9231                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 40283                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups             9759                       # Number of integer rename lookups
+system.cpu.rename.SQFullEvents                    665                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands                9235                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 40294                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups             9761                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                17                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  5494                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     3737                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     3741                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 30                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             28                       # count of temporary serializing insts renamed
 system.cpu.rename.skidInsts                       299                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 1806                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedLoads                 1807                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1277                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 1                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                       8347                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                       8348                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  39                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      7144                       # Number of instructions issued
+system.cpu.iq.iqInstsIssued                      7146                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued               184                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            3008                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         7841                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined            3009                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         7843                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         14978                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.476966                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.861224                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         15116                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.472744                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.858488                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               10780     71.97%     71.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1947     13.00%     84.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1601     10.69%     95.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 605      4.04%     99.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               10916     72.21%     72.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1949     12.89%     85.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1601     10.59%     95.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 605      4.00%     99.70% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::4                  45      0.30%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -466,90 +466,90 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            4                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           14978                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           15116                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                     411     28.90%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     28.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    464     32.63%     61.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                   547     38.47%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                     412     28.93%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     28.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    465     32.65%     61.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                   547     38.41%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  4467     62.53%     62.53% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    5      0.07%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.60% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  4468     62.52%     62.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    5      0.07%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.59% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.04%     62.64% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.64% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.64% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.64% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 1588     22.23%     84.87% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1589     22.24%     84.87% # Type of FU issued
 system.cpu.iq.FU_type_0::MemWrite                1081     15.13%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   7144                       # Type of FU issued
-system.cpu.iq.rate                           0.200928                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                        1422                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.199048                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              30828                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             11385                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         6550                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   7146                       # Type of FU issued
+system.cpu.iq.rate                           0.200984                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                        1424                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.199272                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              30972                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             11387                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         6551                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  44                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 16                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   8538                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   8542                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      28                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads               10                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads          779                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads          780                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation            7                       # Number of memory ordering violations
 system.cpu.iew.lsq.thread0.squashedStores          339                       # Number of stores squashed
@@ -559,11 +559,11 @@ system.cpu.iew.lsq.thread0.rescheduledLoads            5                       #
 system.cpu.iew.lsq.thread0.cacheBlocked            18                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
 system.cpu.iew.iewSquashCycles                    368                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     356                       # Number of cycles IEW is blocking
+system.cpu.iew.iewBlockCycles                     357                       # Number of cycles IEW is blocking
 system.cpu.iew.iewUnblockCycles                    10                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts                8400                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispatchedInsts                8401                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  1806                       # Number of dispatched load instructions
+system.cpu.iew.iewDispLoadInsts                  1807                       # Number of dispatched load instructions
 system.cpu.iew.iewDispStoreInsts                 1277                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 27                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      2                       # Number of times the IQ has become full, causing a stall
@@ -572,43 +572,43 @@ system.cpu.iew.memOrderViolationEvents              7                       # Nu
 system.cpu.iew.predictedTakenIncorrect             67                       # Number of branches that were predicted taken incorrectly
 system.cpu.iew.predictedNotTakenIncorrect          294                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.branchMispredicts                  361                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  6741                       # Number of executed instructions
+system.cpu.iew.iewExecutedInsts                  6742                       # Number of executed instructions
 system.cpu.iew.iewExecLoadInsts                  1404                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               403                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecSquashedInsts               404                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                            14                       # number of nop insts executed
 system.cpu.iew.exec_refs                         2427                       # number of memory reference insts executed
 system.cpu.iew.exec_branches                     1272                       # Number of branches executed
 system.cpu.iew.exec_stores                       1023                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.189594                       # Inst execution rate
-system.cpu.iew.wb_sent                           6608                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          6566                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      2973                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      5368                       # num instructions consuming a value
+system.cpu.iew.exec_rate                     0.189622                       # Inst execution rate
+system.cpu.iew.wb_sent                           6609                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          6567                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      2975                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      5372                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.184672                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.553838                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.184700                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.553797                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            2565                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            2568                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               347                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        14437                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.372515                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.021269                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples        14574                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.369013                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.017093                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        11787     81.64%     81.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1388      9.61%     91.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          602      4.17%     95.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          293      2.03%     97.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          168      1.16%     98.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5           78      0.54%     99.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           45      0.31%     99.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        11924     81.82%     81.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1388      9.52%     91.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          602      4.13%     95.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          293      2.01%     97.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          168      1.15%     98.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5           78      0.54%     99.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           45      0.31%     99.48% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::7           33      0.23%     99.70% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::8           43      0.30%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        14437                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        14574                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 4592                       # Number of instructions committed
 system.cpu.commit.committedOps                   5378                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -655,32 +655,32 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              5378                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                    43                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        22180                       # The number of ROB reads
-system.cpu.rob.rob_writes                       16432                       # The number of ROB writes
+system.cpu.rob.rob_reads                        22320                       # The number of ROB reads
+system.cpu.rob.rob_writes                       16439                       # The number of ROB writes
 system.cpu.timesIdled                             214                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           20577                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                           20439                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        4592                       # Number of Instructions Simulated
 system.cpu.committedOps                          5378                       # Number of Ops (including micro ops) Simulated
 system.cpu.cpi                               7.742814                       # CPI: Cycles Per Instruction
 system.cpu.cpi_total                         7.742814                       # CPI: Total CPI of All Threads
 system.cpu.ipc                               0.129152                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.129152                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                     6717                       # number of integer regfile reads
+system.cpu.int_regfile_reads                     6718                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    3745                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                     23956                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                     2895                       # number of cc regfile writes
+system.cpu.cc_regfile_reads                     23959                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                     2898                       # number of cc regfile writes
 system.cpu.misc_regfile_reads                    2607                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements                 1                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            84.382295                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            84.292966                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1915                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               142                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             13.485915                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    84.382295                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.164809                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.164809                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    84.292966                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.164635                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.164635                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          141                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           88                       # Occupied blocks per task id
@@ -711,14 +711,14 @@ system.cpu.dcache.overall_misses::cpu.data          358                       #
 system.cpu.dcache.overall_misses::total           358                       # number of overall misses
 system.cpu.dcache.ReadReq_miss_latency::cpu.data      9199500                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_latency::total      9199500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      7245500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      7245500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      7717500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      7717500                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       125000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       125000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     16445000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     16445000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     16445000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     16445000                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     16917000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     16917000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     16917000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     16917000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1340                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1340                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
@@ -743,20 +743,20 @@ system.cpu.dcache.overall_miss_rate::cpu.data     0.158899
 system.cpu.dcache.overall_miss_rate::total     0.158899                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55086.826347                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 55086.826347                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37934.554974                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 37934.554974                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40405.759162                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 40405.759162                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        62500                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        62500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 45935.754190                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 45935.754190                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 45935.754190                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 45935.754190                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 47254.189944                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 47254.189944                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 47254.189944                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 47254.189944                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets          731                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          829                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets              18                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    40.611111                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    46.055556                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           65                       # number of ReadReq MSHR hits
@@ -779,12 +779,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data          143
 system.cpu.dcache.overall_mshr_misses::total          143                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5829500                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_latency::total      5829500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2385500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      2385500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      8215000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      8215000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      8215000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      8215000                       # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2454500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2454500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      8284000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      8284000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      8284000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      8284000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076119                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076119                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.044907                       # mshr miss rate for WriteReq accesses
@@ -795,25 +795,25 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.063471
 system.cpu.dcache.overall_mshr_miss_rate::total     0.063471                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57151.960784                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57151.960784                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58182.926829                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58182.926829                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57447.552448                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 57447.552448                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57447.552448                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 57447.552448                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59865.853659                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59865.853659                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57930.069930                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 57930.069930                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57930.069930                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 57930.069930                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                42                       # number of replacements
-system.cpu.icache.tags.tagsinuse           136.424572                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           136.256883                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                3459                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               295                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs             11.725424                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   136.424572                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.266454                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.266454                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   136.256883                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.266127                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.266127                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          253                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          161                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          162                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           91                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.494141                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses              7941                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses             7941                       # Number of data accesses
@@ -829,12 +829,12 @@ system.cpu.icache.demand_misses::cpu.inst          364                       # n
 system.cpu.icache.demand_misses::total            364                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          364                       # number of overall misses
 system.cpu.icache.overall_misses::total           364                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     21691493                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     21691493                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     21691493                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     21691493                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     21691493                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     21691493                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     21567493                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     21567493                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     21567493                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     21567493                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     21567493                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     21567493                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         3823                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         3823                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         3823                       # number of demand (read+write) accesses
@@ -847,17 +847,17 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.095213
 system.cpu.icache.demand_miss_rate::total     0.095213                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.095213                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.095213                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59592.013736                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 59592.013736                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 59592.013736                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 59592.013736                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 59592.013736                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 59592.013736                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         8521                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59251.354396                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 59251.354396                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 59251.354396                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 59251.354396                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 59251.354396                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 59251.354396                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         8431                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets           33                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                89                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    95.741573                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    94.730337                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets           33                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
@@ -873,24 +873,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          296
 system.cpu.icache.demand_mshr_misses::total          296                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          296                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          296                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     18899993                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     18899993                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     18899993                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     18899993                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     18899993                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     18899993                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     18780993                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     18780993                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     18780993                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     18780993                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     18780993                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     18780993                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.077426                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.077426                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.077426                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.077426                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.077426                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.077426                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63851.327703                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63851.327703                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63851.327703                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 63851.327703                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63851.327703                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 63851.327703                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63449.300676                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63449.300676                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63449.300676                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 63449.300676                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63449.300676                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 63449.300676                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.prefetcher.num_hwpf_issued          112                       # number of hwpf issued
 system.cpu.l2cache.prefetcher.pfIdentified          112                       # number of prefetch candidates identified
@@ -899,24 +899,24 @@ system.cpu.l2cache.prefetcher.pfInCache             0                       # nu
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
 system.cpu.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          193.028614                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          192.829480                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 74                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              364                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.203297                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   138.716720                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    45.124038                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher     9.187855                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.008467                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.002754                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.000561                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.011782                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   138.531593                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    45.093662                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher     9.204225                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.008455                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.002752                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.000562                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.011769                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1022           16                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          348                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::0            8                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          180                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          168                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          182                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          166                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1022     0.000977                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.021240                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             7941                       # Number of tag accesses
@@ -945,18 +945,18 @@ system.cpu.l2cache.demand_misses::total           386                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          273                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          113                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          386                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2251000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      2251000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     18451000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     18451000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2320000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2320000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     18332000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     18332000                       # number of ReadCleanReq miss cycles
 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      5549000                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.ReadSharedReq_miss_latency::total      5549000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     18451000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      7800000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     26251000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     18451000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      7800000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     26251000                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     18332000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      7869000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     26201000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     18332000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      7869000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     26201000                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           41                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           41                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          296                       # number of ReadCleanReq accesses(hits+misses)
@@ -981,18 +981,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.879271                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.922297                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.790210                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.879271                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75033.333333                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75033.333333                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67586.080586                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67586.080586                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77333.333333                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77333.333333                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67150.183150                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67150.183150                       # average ReadCleanReq miss latency
 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66855.421687                       # average ReadSharedReq miss latency
 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66855.421687                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67586.080586                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69026.548673                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68007.772021                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67586.080586                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69026.548673                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68007.772021                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67150.183150                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69637.168142                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 67878.238342                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67150.183150                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69637.168142                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 67878.238342                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1026,21 +1026,21 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst          272
 system.cpu.l2cache.overall_mshr_misses::cpu.data          108                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher           48                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          428                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher      1697924                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total      1697924                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2071000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2071000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     16769500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     16769500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher      1625926                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total      1625926                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2140000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2140000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     16650500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     16650500                       # number of ReadCleanReq MSHR miss cycles
 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4788500                       # number of ReadSharedReq MSHR miss cycles
 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4788500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16769500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6859500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     23629000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16769500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6859500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher      1697924                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     25326924                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16650500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6928500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     23579000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16650500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6928500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher      1625926                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     25204926                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.731707                       # mshr miss rate for ReadExReq accesses
@@ -1056,21 +1056,21 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.918919
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.755245                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.974943                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35373.416667                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 35373.416667                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69033.333333                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69033.333333                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61652.573529                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61652.573529                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873.458333                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33873.458333                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71333.333333                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71333.333333                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61215.073529                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61215.073529                       # average ReadCleanReq mshr miss latency
 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61391.025641                       # average ReadSharedReq mshr miss latency
 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61391.025641                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61652.573529                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63513.888889                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62181.578947                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61652.573529                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63513.888889                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35373.416667                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59175.056075                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61215.073529                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64152.777778                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total        62050                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61215.073529                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64152.777778                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873.458333                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58890.014019                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadResp           396                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict           32                       # Transaction distribution
@@ -1122,9 +1122,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 407                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              510442                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              514444                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2136258                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            2136000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             12.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------