Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER

diff --git a/tests/arch/ice40/wrapcarry.ys b/tests/arch/ice40/wrapcarry.ys
index 10c029e68920baa023b3bd9e0178d14611740efc..a4b0d357aa570d7dc658ffa746be89cb9d0699c0 100644 (file)
--- a/tests/arch/ice40/wrapcarry.ys
+++ b/tests/arch/ice40/wrapcarry.ys
@@ -20,3 +20,33 @@ EOT
 
 ice40_wrapcarry
 select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
+
+design -reset
+read_verilog <<EOT
+module top(input A, B, CI, output O, CO);
+    (* foo = "bar", answer = 42 *)
+       SB_CARRY carry (
+               .I0(A),
+               .I1(B),
+               .CI(CI),
+               .CO(CO)
+       );
+    (* keep, blah="blah", answer = 43 *)
+       SB_LUT4 #(
+               .LUT_INIT(16'b 0110_1001_1001_0110)
+       ) adder (
+               .I0(1'b0),
+               .I1(A),
+               .I2(B),
+               .I3(1'b0),
+               .O(O)
+       );
+endmodule
+EOT
+
+ice40_wrapcarry
+select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
+select -assert-count 0 t:* t:$__ICE40_CARRY_WRAPPER %d
+select -assert-count 1 a:foo=bar a:answer=42 %i a:keep %i a:blah=blah %i
+techmap -map +/ice40/cells_map.v
+#TODO: Check unwrapped attributes