remove MISSING (theyre not), fix a couple of errors in pseudocode

for lmw and stmw, these are not supported but are there for spec
"completeness"

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 5a64265a84bc5358dd218c6ba3b31d1dc870c5b6..203c1f397b707a2b54cc45ccfd214aac0148dab6 100644 (file)
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -435,8 +435,6 @@ Special Registers Altered:
 
     None
 
-<!-- MISSING stq -->
-
 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 
 # Load Halfword Byte-Reverse Indexed
@@ -456,8 +454,6 @@ Special Registers Altered:
 
     None
 
-<!-- MISSING sthbrx -->
-
 # Load Word Byte-Reverse Indexed
 
 X-Form
@@ -476,8 +472,6 @@ Special Registers Altered:
 
     None
 
-<!-- MISSING stwbrx -->
-
 
 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 
@@ -501,8 +495,6 @@ Special Registers Altered:
 
     None
 
-<!-- MISSING stdbrx -->
-
 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 
 # Load Multiple Word
@@ -515,7 +507,7 @@ Pseudo-code:
 
     b <- (RA|0)
     EA <- b + EXTS(D)
-    r <- RT
+    r <- RT[0:63]
     do while r <=  31
         GPR(r) <- [0]*32 || MEM(EA, 4)
         r <- r + 1
@@ -525,6 +517,3 @@ Special Registers Altered:
 
     None
 
-<!-- MISSING stmw -->
-
-

diff --git a/openpower/isa/fixedstore.mdwn b/openpower/isa/fixedstore.mdwn
index ce64d4b9129ec3a5c3ddfc9edae459f05abf8bc8..d13fa938a651f2f270c929e9762e6d265aa6d523 100644 (file)
--- a/openpower/isa/fixedstore.mdwn
+++ b/openpower/isa/fixedstore.mdwn
@@ -12,15 +12,6 @@
 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 
-<!-- MISSING stbh -->
-<!-- MISSING stbhx -->
-<!-- MISSING stbhu -->
-<!-- MISSING stbhux -->
-<!-- MISSING stbw -->
-<!-- MISSING stbwx -->
-<!-- MISSING stbwu -->
-<!-- MISSING stbwux -->
-
 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
 
 # Store Byte
@@ -380,7 +371,7 @@ Pseudo-code:
 
     b <- (RA|0)
     EA <- b + EXTS(D)
-    r <- RS
+    r <- RS[0:63]
     do while r <= 31
         MEM(EA, 4) <- GPR(r)[32:63]
         r <-  r + 1