Do not SigSpec::extract() beyond bounds

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index f6ae3a13f4de81e4ac47417aaf2a3f90a309ebc8..5e87d6497530a6371c77dc303d07b5143a23c165 100644 (file)
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -224,11 +224,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
        pm.autoremove(st.ffH);
        pm.autoremove(st.addAB);
        if (st.ffO_lo) {
-                       SigSpec O = st.sigO.extract(0,16);
+                       SigSpec O = st.sigO.extract(0,GetSize(st.ffO_lo));
                        st.ffO_lo->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
        }
        if (st.ffO_hi) {
-                       SigSpec O = st.sigO.extract(16,16);
+                       SigSpec O = st.sigO.extract(16,GetSize(st.ffo_hi));
                        st.ffO_hi->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
        }
 }

diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index f1f53318743a4627ba6c6e712b1885801aab777e..8b1ac25631698bdc7e59fff16d2776b1c148f4b8 100644 (file)
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -156,15 +156,17 @@ endcode
 
 match ffO_lo
        select ffO_lo->type.in($dff)
-       filter nusers(sigO.extract(0,16)) == 2
-       filter includes(port(ffO_lo, \D).to_sigbit_set(), sigO.extract(0,16).to_sigbit_set())
+       filter GetSize(sigO) >= param(ffO_lo, \WIDTH).as_int()
+       filter nusers(sigO.extract(0,param(ffO_lo, \WIDTH).as_int())) == 2
+       filter includes(port(ffO_lo, \D).to_sigbit_set(), sigO.extract(0,param(ffO_lo, \WIDTH).as_int()).to_sigbit_set())
        optional
 endmatch
 
 match ffO_hi
        select ffO_hi->type.in($dff)
-       filter nusers(sigO.extract(16,16)) == 2
-       filter includes(port(ffO_hi, \D).to_sigbit_set(), sigO.extract(16,16).to_sigbit_set())
+       filter GetSize(sigO) >= 16+param(ffO_hi, \WIDTH).as_int()
+       filter nusers(sigO.extract(16,param(ffO_hi, \WIDTH).as_int())) == 2
+       filter includes(port(ffO_hi, \D).to_sigbit_set(), sigO.extract(16,param(ffO_hi, \WIDTH).as_int()).to_sigbit_set())
        optional
 endmatch
 
@@ -184,7 +186,7 @@ code clock clock_pol sigO sigCD
                        clock = c;
                        clock_pol = cp;
 
-                       if (port(ffO_lo, \Q) != sigO.extract(0,16))
+                       if (port(ffO_lo, \Q) != sigO.extract(0,param(ffO_lo, \WIDTH).as_int()))
                                sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q));
                }
 
@@ -202,7 +204,7 @@ code clock clock_pol sigO sigCD
                        clock = c;
                        clock_pol = cp;
 
-                       if (port(ffO_hi, \Q) != sigO.extract(16,16))
+                       if (port(ffO_hi, \Q) != sigO.extract(16,param(ffO_hi, \WIDTH).as_int()))
                                sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
                }