|0-5|6-10 |11|12-15|16-18|19-20|21-25 |26-30 |31|name |
|---|---- |--|-----|-----|-----|----- |----- |--|---- |
-|19 |RT | |mask |BFA | |XO[0:4]|XO[5:9]|/ | |
+|19 |RT | |fmsk |BFA | |XO[0:4]|XO[5:9]|/ | |
|19 | | | | | |1 //// |00011 | |rsvd |
-|19 |RT |M |mask |BFA | 0 0 |0 mode |00011 |Rc|crrweird |
-|19 |RT |M |mask |BFA | 0 1 |0 mode |00011 |Rc|mfcrweird |
-|19 |RA |M |mask |BF | 1 0 |0 mode |00011 |0 |mtcrrweird |
-|19 |RA |M |mask |BF | 1 0 |0 mode |00011 |1 |mtcrweird |
-|19 |BT |M |mask |BFA | 1 1 |0 mode |00011 |0 |crweirder |
-|19 |BF //|M |mask |BFA | 1 1 |0 mode |00011 |1 |mcrfm |
+|19 |RT |M |fmsk |BFA | 0 0 |0 fmap |00011 |Rc|crrweird |
+|19 |RT |M |fmsk |BFA | 0 1 |0 fmap |00011 |Rc|mfcrweird |
+|19 |RA |M |fmsk |BF | 1 0 |0 fmap |00011 |0 |mtcrrweird |
+|19 |RA |M |fmsk |BF | 1 0 |0 fmap |00011 |1 |mtcrweird |
+|19 |BT |M |fmsk |BFA | 1 1 |0 fmap |00011 |0 |crweirder |
+|19 |BF //|M |fmsk |BFA | 1 1 |0 fmap |00011 |1 |mcrfm |
**crrweird**
-mode is encoded in XO and is 4 bits
+fmap is encoded in XO and is 4 bits
- crrweird: RT,BFA,M,mask,mode
+ crrweird: RT,BFA,M,fmsk,fmap
creg = CR{BFA}
- n0 = mask[0] & (mode[0] == creg[0])
- n1 = mask[1] & (mode[1] == creg[1])
- n2 = mask[2] & (mode[2] == creg[2])
- n3 = mask[3] & (mode[3] == creg[3])
- n = (n0||n1||n2||n3) & mask
- result = (n != 0) if M else (n == mask)
+ n0 = fmsk[0] & (fmap[0] == creg[0])
+ n1 = fmsk[1] & (fmap[1] == creg[1])
+ n2 = fmsk[2] & (fmap[2] == creg[2])
+ n3 = fmsk[3] & (fmap[3] == creg[3])
+ n = (n0||n1||n2||n3) & fmsk
+ result = (n != 0) if M else (n == fmsk)
RT[63] = result # MSB0 numbering, 63 is LSB
If Rc:
CR0 = analyse(RT)
**mfcrrweird**
-mode is encoded in XO and is 4 bits
+fmap is encoded in XO and is 4 bits
- mfcrrweird: RT,BFA,mask,mode
+ mfcrrweird: RT,BFA,fmsk,fmap
creg = CR{BFA}
- n0 = mask[0] & (mode[0] == creg[0])
- n1 = mask[1] & (mode[1] == creg[1])
- n2 = mask[2] & (mode[2] == creg[2])
- n3 = mask[3] & (mode[3] == creg[3])
+ n0 = fmsk[0] & (fmap[0] == creg[0])
+ n1 = fmsk[1] & (fmap[1] == creg[1])
+ n2 = fmsk[2] & (fmap[2] == creg[2])
+ n3 = fmsk[3] & (fmap[3] == creg[3])
result = n0||n1||n2||n3
RT[60:63] = result # MSB0 numbering, 63 is LSB
If Rc:
**mtcrrweird**
-mode is encoded in XO and is 4 bits
+fmap is encoded in XO and is 4 bits
- mtcrrweird: BF,RA,M,mask,mode
+ mtcrrweird: BF,RA,M,fmsk,fmap
a = (RA|0)
- n0 = mask[0] & (mode[0] == a[63])
- n1 = mask[1] & (mode[1] == a[62])
- n2 = mask[2] & (mode[2] == a[61])
- n3 = mask[3] & (mode[3] == a[60])
+ n0 = fmsk[0] & (fmap[0] == a[63])
+ n1 = fmsk[1] & (fmap[1] == a[62])
+ n2 = fmsk[2] & (fmap[2] == a[61])
+ n3 = fmsk[3] & (fmap[3] == a[60])
result = n0 || n1 || n2 || n3
if M:
- result |= CR{BF} & ~mask
+ result |= CR{BF} & ~fmsk
CR{BF} = result
When used with SVP64 Prefixing this is a [[sv/normal]]
**mtcrweird**
- mtcrweird: BF,RA,M,mask,mode
+ mtcrweird: BF,RA,M,fmsk,fmap
reg = (RA|0)
lsb = reg[63] # MSB0 numbering
- n0 = mask[0] & (mode[0] == lsb)
- n1 = mask[1] & (mode[1] == lsb)
- n2 = mask[2] & (mode[2] == lsb)
- n3 = mask[3] & (mode[3] == lsb)
+ n0 = fmsk[0] & (fmap[0] == lsb)
+ n1 = fmsk[1] & (fmap[1] == lsb)
+ n2 = fmsk[2] & (fmap[2] == lsb)
+ n3 = fmsk[3] & (fmap[3] == lsb)
result = n0 || n1 || n2 || n3
if M:
- result |= CR{BF} & ~mask
+ result |= CR{BF} & ~fmsk
CR{BF} = result
Note that when M=1 this operation is a Read-Modify-Write on the CR Field
the EQ bit from the source may only go into the EQ bit of the
destination (optionally inverted, set, or cleared).
- mcrfm: BF,BFA,M,mask,mode
+ mcrfm: BF,BFA,M,fmsk,fmap
- result = mask & CR{BFA}
+ result = fmsk & CR{BFA}
if M:
- result |= CR{BF} & ~mask
- result ^= mode
+ result |= CR{BF} & ~fmsk
+ result ^= fmap
CR{BF} = result
When M=1 this operation is a Read-Modify-Write on the CR Field
type operation that has 3-bit Data-dependent and 3-bit Predicate-result
capability (BF is 3 bits)
-*Programmer's note: `mode` being XORed onto the result provides
+*Programmer's note: `fmap` being XORed onto the result provides
considerable flexibility. individual bits of BFA may be copied inverted
-to BF by ensuring that `mask` and `mode` have the same bit set. Also,
+to BF by ensuring that `fmsk` and `fmap` have the same bit set. Also,
individual bits in BF may be set to 1 by ensuring that the required bit of
-`mask` is set to zero and the same bit in `mode` is set to 1*
+`fmsk` is set to zero and the same bit in `fmap` is set to 1*
**crweirder**
- crweirder: BT,BFA,mask,mode
+ crweirder: BT,BFA,fmsk,fmap
creg = CR{BFA}
- n0 = mask[0] & (mode[0] == creg[0])
- n1 = mask[1] & (mode[1] == creg[1])
- n2 = mask[2] & (mode[2] == creg[2])
- n3 = mask[3] & (mode[3] == creg[3])
+ n0 = fmsk[0] & (fmap[0] == creg[0])
+ n1 = fmsk[1] & (fmap[1] == creg[1])
+ n2 = fmsk[2] & (fmap[2] == creg[2])
+ n3 = fmsk[3] & (fmap[3] == creg[3])
BF = BT[2:4] # select CR
bit = BT[0:1] # select bit of CR
- n = (n0||n1||n2||n3) & mask
- result = (n != 0) if M else (n == mask)
+ n = (n0||n1||n2||n3) & fmsk
+ result = (n != 0) if M else (n == fmsk)
CR{BF}[bit] = result
When used with SVP64 Prefixing this is a [[sv/cr_ops]] SVP64
**Example Pseudo-ops:**
- mtcri BF, mode mtcrweird BF, r0, 0, 0b1111,~mode
- mtcrset BF, mask mtcrweird BF, r0, 1, mask,0b0000
- mtcrclr BF, mask mtcrweird BF, r0, 1, mask,0b1111
+ mtcri BF, fmap mtcrweird BF, r0, 0, 0b1111,~fmap
+ mtcrset BF, fmsk mtcrweird BF, r0, 1, fmsk,0b0000
+ mtcrclr BF, fmsk mtcrweird BF, r0, 1, fmsk,0b1111
# Vectorised versions involving GPRs
operand) elwidth field still sets the Integer element size as usual
(8/16/32/default)
-**crrweird: RT, BB, mask.mode**
+**crrweird: RT, BB, fmsk.fmap**
for i in range(VL):
if BB.isvec:
creg = CR{BB+i}
else:
creg = CR{BB}
- n0 = mask[0] & (mode[0] == creg[0])
- n1 = mask[1] & (mode[1] == creg[1])
- n2 = mask[2] & (mode[2] == creg[2])
- n3 = mask[3] & (mode[3] == creg[3])
+ n0 = fmsk[0] & (fmap[0] == creg[0])
+ n1 = fmsk[1] & (fmap[1] == creg[1])
+ n2 = fmsk[2] & (fmap[2] == creg[2])
+ n3 = fmsk[3] & (fmap[3] == creg[3])
# OR or AND to a single bit
- n = (n0||n1||n2||n3) & mask
- result = (n != 0) if M else (n == mask)
+ n = (n0||n1||n2||n3) & fmsk
+ result = (n != 0) if M else (n == fmsk)
if RT.isvec:
# TODO: RT.elwidth override to be also added here
# note, yes, really, the CR's elwidth field determines
of the INT Elements, the packing arrangement depending on both
elwidth override settings.
-**mfcrrweird: RT, BFA, mask.mode**
+**mfcrrweird: RT, BFA, fmsk.fmap**
Unlike `crrweird` the results are 4-bit wide, so the packing
will begin to spill over to other destination elements. 8 results per
creg = CR{BB+i}
else:
creg = CR{BB}
- n0 = mask[0] & (mode[0] == creg[0])
- n1 = mask[1] & (mode[1] == creg[1])
- n2 = mask[2] & (mode[2] == creg[2])
- n3 = mask[3] & (mode[3] == creg[3])
+ n0 = fmsk[0] & (fmap[0] == creg[0])
+ n1 = fmsk[1] & (fmap[1] == creg[1])
+ n2 = fmsk[2] & (fmap[2] == creg[2])
+ n3 = fmsk[3] & (fmap[3] == creg[3])
result = n0||n1||n2||n3 # 4-bit result
if RT.isvec:
# RT.elwidth override can affect the packing
Here, RA is zero, so the source input is zero. The destination is CR Field
8, and the destination predicate mask indicates to target the first two
elements. Destination predicate zeroing is enabled, and the destination
-predicate is only set in the 2nd bit. mask is 0b0011, mode is all zeros.
+predicate is only set in the 2nd bit. fmsk is 0b0011, fmap is all zeros.
Let us first consider what should go into element 0 (CR Field 8):
* Bit 2 of the destination predicate, r10, is 1. Therefore the computation
of the result is relevant.
-* RA is zero therefore bit 2 is zero. mask is 0b0011 and mode is 0b0000
+* RA is zero therefore bit 2 is zero. fmsk is 0b0011 and fmap is 0b0000
* When calculating n0 thru n3 we get n0=1, n1=2, n2=0, n3=0
-* Therefore, CR9 is set (using LSB0 ordering) to 0b0011, i.e. to mask.
+* Therefore, CR9 is set (using LSB0 ordering) to 0b0011, i.e. to fmsk.
It should be clear that this instruction uses bits of the integer
-predicate to decide whether to set CR Fields to `(mask & ~mode)` or
+predicate to decide whether to set CR Fields to `(fmsk & ~fmap)` or
to zero. Thus, in effect, it is the integer predicate that has been
copied into the CR Fields.
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