add link to uart

diff --git a/shakti/m_class.mdwn b/shakti/m_class.mdwn
index 63e288b2ac0331318a3eaa9d7b23a8a9fc6036d2..a624b3eb4c96b472199b79a085e80fd498362a61 100644 (file)
--- a/shakti/m_class.mdwn
+++ b/shakti/m_class.mdwn
@@ -211,8 +211,8 @@ TBD
 * 2x 1-lane [[SPI]]
 * 1x 4-lane (quad) [[QSPI]]
 * 4x SD/MMC (1x 1/2/4/8-bit, 3x 1/2/4-bit)
-* 2x full UART incl. CTS/RTS
-* 3x UART (TX/RX only)
+* 2x full [[UART]] incl. CTS/RTS
+* 3x [[UART]] (TX/RX only)
 * 3x [[I2C]] (in case of address clashes between peripherals)
 * 8080-style AT/XT/ATI MCU Bus Interface, with multiple (8x CS#) lines
 * 3x [[PWM]]-capable GPIO

diff --git a/shakti/m_class/UART.mdwn b/shakti/m_class/UART.mdwn
new file mode 100644 (file)
index 0000000..f4db6db
--- /dev/null
+++ b/shakti/m_class/UART.mdwn
@@ -0,0 +1,3 @@
+# UART RTL
+
+* <https://git.m-labs.hk/M-Labs/HeavyX/src/branch/master/heavycomps/heavycomps/uart.py>