Implement the increment and decrement instructions, and the two operand form of signe...

--HG--
extra : convert_revision : d87df4b1b5470bed1d963dfe8e2ffa1403718342

diff --git a/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py b/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py
index c504d47ce4cdbb247c1afc4b4611501c1ba50d18..eed39c10c24c45f5ed9b155bd2d5ef1c8dab0905 100644 (file)
--- a/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py
+++ b/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py
@@ -53,7 +53,47 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
+microcode = '''
+def macroop INC_R
+{
+    addi reg, reg, 1, flags=(OF, SF, ZF, AF, PF)
+};
+
+def macroop INC_M
+{
+    ld t1, ds, [scale, index, base], disp
+    addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop INC_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    addi reg, reg, 1, flags=(OF, SF, ZF, AF, PF)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop DEC_R
+{
+    subi reg, reg, 1, flags=(OF, SF, ZF, AF, PF)
+};
+
+def macroop DEC_M
+{
+    ld t1, ds, [scale, index, base], disp
+    subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop DEC_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    subi reg, reg, 1, flags=(OF, SF, ZF, AF, PF)
+    st t1, ds, [0, t0, t7], disp
+};
+'''
 #let {{
 #    class DEC(Inst):
 #      "GenFault ${new UnimpInstFault}"

diff --git a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
index 662022e6ab20bec34c9a22beb1e46ec3c725197a..8697bef65c4309bc00f73250206e606b077628ef 100644 (file)
--- a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
+++ b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
@@ -53,7 +53,31 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
+microcode = '''
+
+#
+# Two operand signed multiply. These should set the CF and OF flags if the
+# result is too large for the destination register
+#
+
+def macroop IMUL_R_R
+{
+    mul1s reg, reg, regm
+};
+
+def macroop IMUL_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mul1s reg, reg, t1
+};
+
+def macroop IMUL_R_P
+{
+    rdip t7
+    ld t1, ds, [scale, index, base], disp
+    mul1s reg, reg, t1
+};
+'''
 #let {{
 #    class MUL(Inst):
 #      "GenFault ${new UnimpInstFault}"