(no commit message)

diff --git a/openpower/sv/rfc/001.mdwn b/openpower/sv/rfc/001.mdwn
index c6fb3de1fb5ea55ac49ae7ba8011673fb3ea10f5..6d5e61cddabfa038c349e94ceb1753b8ac39d17b 100644 (file)
--- a/openpower/sv/rfc/001.mdwn
+++ b/openpower/sv/rfc/001.mdwn
@@ -23,6 +23,21 @@ A variant of Simple-V was originally invented in 1994 by Peter Hsu
 (Architect of the MIPS R8000) but was dropped as MIPS did not have an
 Out-of-Order Microarchitecture.
 
+Simple-V is designed for Embedded Scenarios right the way through
+Audio/Visual DSPs to 3D GPUs and Supercomputing.  As it does **not**
+add actual Vector Instructions, relying solely and exclusively on the
+**Scalar** ISA, it is **Scalar** instructions that need to be added
+to the **Scalar** Power ISA before Simple-V may orthogonally Vectorise
+them. 
+
+Therefore because the goal of RED Semiconductor Ltd, an OpenPOWER Stakeholder,
+is to bring to market mass-volume general-purpose compute processors that
+are competitive in the 3D GPU Audio Visual DSP EDGE IoT markets, Simple-V
+has to be accompanied by corresponding **Scalar** instructions that bring
+the **Scalar** Power ISA up-to-date.  These include IEEE754 Transcendentals
+AV cryptographic Biginteger and bitmanipulation operations that ARM Intel
+AMD and many other ISAs have been adding over the past 12 years.
+
 # Resources