--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+library work;
+use work.wishbone_types.all;
+
+entity toplevel is
+ generic (
+ MEMORY_SIZE : integer := 16384;
+ RAM_INIT_FILE : string := "firmware.hex";
+ RESET_LOW : boolean := true;
+ CLK_FREQUENCY : positive := 100000000;
+ HAS_FPU : boolean := true;
+ HAS_BTC : boolean := true;
+ USE_LITEDRAM : boolean := false;
+ NO_BRAM : boolean := false;
+ DISABLE_FLATTEN_CORE : boolean := false;
+ SCLK_STARTUPE2 : boolean := false;
+ SPI_FLASH_OFFSET : integer := 4194304;
+ SPI_FLASH_DEF_CKDV : natural := 1;
+ SPI_FLASH_DEF_QUAD : boolean := true;
+ LOG_LENGTH : natural := 512;
+ USE_LITEETH : boolean := false;
+ UART_IS_16550 : boolean := false;
+ HAS_UART1 : boolean := true;
+ USE_LITESDCARD : boolean := false;
+ HAS_GPIO : boolean := true;
+ NGPIO : natural := 32
+ );
+ port(
+ ext_clk : in std_ulogic;
+
+ d11_led : out std_ulogic;
+ d12_led : out std_ulogic;
+ d13_led : out std_ulogic;
+
+ -- UART0 signals:
+ uart_main_tx : out std_ulogic;
+ uart_main_rx : in std_ulogic
+
+ );
+end entity toplevel;
+
+architecture behaviour of toplevel is
+ signal ext_rst_n : std_ulogic;
+
+ -- Reset signals:
+ signal soc_rst : std_ulogic;
+ signal pll_rst : std_ulogic;
+
+ -- Internal clock signals:
+ signal system_clk : std_ulogic;
+ signal system_clk_locked : std_ulogic;
+ signal eth_clk_locked : std_ulogic;
+
+ -- External IOs from the SoC
+ signal wb_ext_io_in : wb_io_master_out;
+ signal wb_ext_io_out : wb_io_slave_out;
+
+ -- DRAM main data wishbone connection
+ signal wb_dram_in : wishbone_master_out;
+ signal wb_dram_out : wishbone_slave_out;
+
+ -- DRAM control wishbone connection
+ signal wb_dram_ctrl_out : wb_io_slave_out := wb_io_slave_out_init;
+
+ -- LiteEth connection
+ signal ext_irq_eth : std_ulogic;
+ signal wb_eth_out : wb_io_slave_out := wb_io_slave_out_init;
+
+ -- LiteSDCard connection
+ signal ext_irq_sdcard : std_ulogic := '0';
+ signal wb_sdcard_out : wb_io_slave_out := wb_io_slave_out_init;
+ signal wb_sddma_out : wb_io_master_out := wb_io_master_out_init;
+ signal wb_sddma_in : wb_io_slave_out;
+ signal wb_sddma_nr : wb_io_master_out;
+ signal wb_sddma_ir : wb_io_slave_out;
+ -- for conversion from non-pipelined wishbone to pipelined
+ signal wb_sddma_stb_sent : std_ulogic;
+
+ -- Control/status
+ signal core_alt_reset : std_ulogic;
+
+ -- Status LED
+ signal led0_b_pwm : std_ulogic;
+ signal led0_r_pwm : std_ulogic;
+ signal led0_g_pwm : std_ulogic;
+
+ -- Dumb PWM for the LEDs, those RGB LEDs are too bright otherwise
+ signal pwm_counter : std_ulogic_vector(8 downto 0);
+
+ -- SPI flash
+ signal spi_sck : std_ulogic;
+ signal spi_cs_n : std_ulogic;
+ signal spi_sdat_o : std_ulogic_vector(3 downto 0);
+ signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
+ signal spi_sdat_i : std_ulogic_vector(3 downto 0);
+
+ -- GPIO
+ signal gpio_in : std_ulogic_vector(NGPIO - 1 downto 0);
+ signal gpio_out : std_ulogic_vector(NGPIO - 1 downto 0);
+ signal gpio_dir : std_ulogic_vector(NGPIO - 1 downto 0);
+
+ -- Fixup various memory sizes based on generics
+ function get_bram_size return natural is
+ begin
+ if USE_LITEDRAM and NO_BRAM then
+ return 0;
+ else
+ return MEMORY_SIZE;
+ end if;
+ end function;
+
+ function get_payload_size return natural is
+ begin
+ if USE_LITEDRAM and NO_BRAM then
+ return MEMORY_SIZE;
+ else
+ return 0;
+ end if;
+ end function;
+
+ constant BRAM_SIZE : natural := get_bram_size;
+ constant PAYLOAD_SIZE : natural := get_payload_size;
+begin
+ -- Main SoC
+ soc0: entity work.soc
+ generic map(
+ MEMORY_SIZE => BRAM_SIZE,
+ RAM_INIT_FILE => RAM_INIT_FILE,
+ SIM => false,
+ CLK_FREQ => CLK_FREQUENCY,
+ HAS_FPU => HAS_FPU,
+ HAS_BTC => HAS_BTC,
+ HAS_DRAM => USE_LITEDRAM,
+ DRAM_SIZE => 512 * 1024 * 1024,
+ DRAM_INIT_SIZE => PAYLOAD_SIZE,
+ DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
+ HAS_SPI_FLASH => false,
+ SPI_FLASH_DLINES => 4,
+ SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
+ SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
+ SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
+ LOG_LENGTH => LOG_LENGTH,
+ HAS_LITEETH => USE_LITEETH,
+ UART0_IS_16550 => UART_IS_16550,
+ HAS_UART1 => HAS_UART1,
+ HAS_SD_CARD => USE_LITESDCARD,
+ HAS_GPIO => HAS_GPIO,
+ NGPIO => NGPIO
+ )
+ port map (
+ -- System signals
+ system_clk => system_clk,
+ rst => soc_rst,
+
+ -- UART signals
+ uart0_txd => uart_main_tx,
+ uart0_rxd => uart_main_rx,
+
+ -- UART1 signals
+ --uart1_txd => uart_pmod_tx,
+ --uart1_rxd => uart_pmod_rx,
+
+ -- SPI signals
+-- spi_flash_sck => spi_sck,
+-- spi_flash_cs_n => spi_cs_n,
+ spi_flash_sdat_o => spi_sdat_o,
+ spi_flash_sdat_oe => spi_sdat_oe,
+ spi_flash_sdat_i => spi_sdat_i,
+
+ -- GPIO signals
+ gpio_in => gpio_in,
+ gpio_out => gpio_out,
+ gpio_dir => gpio_dir,
+
+ -- External interrupts
+ ext_irq_eth => ext_irq_eth,
+ ext_irq_sdcard => ext_irq_sdcard,
+
+ -- DRAM wishbone
+ wb_dram_in => wb_dram_in,
+ wb_dram_out => wb_dram_out,
+
+ -- IO wishbone
+ wb_ext_io_in => wb_ext_io_in,
+ wb_ext_io_out => wb_ext_io_out,
+-- wb_ext_is_dram_csr => ,
+-- wb_ext_is_dram_init => ,
+-- wb_ext_is_eth => ,
+-- wb_ext_is_sdcard => ,
+
+ -- DMA wishbone
+ wishbone_dma_in => wb_sddma_in,
+ wishbone_dma_out => wb_sddma_out,
+
+ alt_reset => core_alt_reset
+ );
+
+ reset_controller: entity work.soc_reset
+ generic map(
+ RESET_LOW => RESET_LOW
+ )
+ port map(
+ ext_clk => ext_clk,
+ pll_clk => system_clk,
+ pll_locked_in => system_clk_locked,
+ ext_rst_in => ext_rst_n,
+ pll_rst_out => pll_rst,
+ rst_out => soc_rst
+ );
+
+ clkgen: entity work.clock_generator
+ generic map(
+ CLK_INPUT_HZ => 100000000,
+ CLK_OUTPUT_HZ => CLK_FREQUENCY
+ )
+ port map(
+ ext_clk => ext_clk,
+ pll_rst_in => pll_rst,
+ pll_clk_out => system_clk,
+ pll_locked_out => system_clk_locked
+ );
+
+ wb_ext_io_out.dat <= (others => '0');
+ wb_ext_io_out.ack <= '0';
+ wb_ext_io_out.stall <= '0';
+
+ wb_sdcard_out.ack <= '0';
+ wb_sdcard_out.stall <= '0';
+
+ ext_irq_eth <= '0';
+ ext_irq_sdcard <= '0';
+
+ ext_rst_n <= '1';
+
+ d11_led <= '0';
+ d12_led <= soc_rst;
+ d13_led <= system_clk;
+
+end architecture behaviour;
projects / microwatt.git / commitdiff