gen/fhdl/verilog: fix signed init values

diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py
index e1bd8da4e6d9ebf2318cbd6dca405d15937f9804..f515dbfb2848779123207c080a1ccc4584def775 100644 (file)
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@@ -59,8 +59,8 @@ def _printsig(ns, s):
 
 def _printconstant(node):
     if node.signed:
-        return (str(node.nbits) + "'sd" + str(2**node.nbits + node.value),
-                True)
+        sign = "-" if node.value < 0 else ""
+        return (sign + str(node.nbits) + "'d" + str(abs(node.value)), True)
     else:
         return str(node.nbits) + "'d" + str(node.value), False