Added missing fixup_ports() calls to "rename" command

diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 1006686efe8bd45ec0b026fa6db18967928b9841..b2e10e557b65878cab4f9606bad45c89dc5833c0 100644 (file)
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -36,6 +36,8 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
                if (it.first == from_name) {
                        log("Renaming wire %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
                        module->rename(it.second, to_name);
+                       if (it.second->port_id)
+                               module->fixup_ports();
                        return;
                }
 
@@ -124,6 +126,7 @@ struct RenamePass : public Pass {
                                        new_wires[it.second->name] = it.second;
                                }
                                module->wires_.swap(new_wires);
+                               module->fixup_ports();
 
                                std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
                                for (auto &it : module->cells_) {
@@ -154,6 +157,7 @@ struct RenamePass : public Pass {
                                        new_wires[it.second->name] = it.second;
                                }
                                module->wires_.swap(new_wires);
+                               module->fixup_ports();
 
                                std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
                                for (auto &it : module->cells_) {