2010-10-25 Chao-ying Fu <fu@mips.com>

	* mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f62cb4b1ffd99475ddd180bef81aa5d02f6e2404..e8d2a72eb29c0dfcefd8d1a41953dc3bc0301b9c 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2010-10-25  Chao-ying Fu  <fu@mips.com>
+
+       * mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32.
+
 2010-10-25  Nathan Sidwell  <nathan@codesourcery.com>
 
        * tic6x-dis.c: Add attribution.

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 230d0f8c9d732a48de221d944e5b3192bb754533..8ff6435fc50673b7f0d91db9b67533ab5ce7f411 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -834,13 +834,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,                L1      },
 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,                I32|N55 },
 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,                G1      },
-{"madd",    "7,s,t",   0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33     },
+{"madd",    "7,s,t",   0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D32     },
 {"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,                G1      },
 {"maddp",   "s,t",      0x70000441, 0xfc00ffff,        RD_s|RD_t|MOD_HILO,          0,         SMT     },
 {"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,                L1      },
 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,                I32|N55 },
 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,                G1      },
-{"maddu",   "7,s,t",   0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33     },
+{"maddu",   "7,s,t",   0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D32     },
 {"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,                G1      },
 {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,    0,              N411    },
 {"max.ob",  "X,Y,Q",   0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
@@ -943,10 +943,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"msub.ps",    "D,S,T",        0x71600019,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,     0,              L1      },
 {"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,             I32|N55 },
-{"msub",    "7,s,t",   0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
+{"msub",    "7,s,t",   0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
 {"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,     0,              L1      },
 {"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,             I32|N55 },
-{"msubu",   "7,s,t",   0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
+{"msubu",   "7,s,t",   0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
 {"mtpc",    "t,P",     0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0,         0,              M1|N5   },
 {"mtps",    "t,P",     0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0,         0,              M1|N5   },
 {"mtc0",    "t,G",     0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I1|IOCT },
@@ -1035,11 +1035,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mulsl.ob", "S,k",    0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"mulsl.qh", "Y,Q",    0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
 {"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,             I1      },
-{"mult",    "7,s,t",   0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33     },
+{"mult",    "7,s,t",   0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D32     },
 {"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,                G1      },
 {"multp",   "s,t",     0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              SMT     },
 {"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,             I1      },
-{"multu",   "7,s,t",   0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33     },
+{"multu",   "7,s,t",   0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D32     },
 {"multu",   "d,s,t",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,                G1      },
 {"mulu",    "d,s,t",   0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
 {"neg",     "d,w",     0x00000022, 0xffe007ff, WR_d|RD_t,              0,              I1      }, /* sub 0 */