Fix typo
authorEddie Hung <eddie@fpgeh.com>
Sat, 28 Sep 2019 00:00:19 +0000 (17:00 -0700)
committerEddie Hung <eddie@fpgeh.com>
Mon, 30 Sep 2019 22:18:40 +0000 (15:18 -0700)
kernel/rtlil.cc

index 17be28f78277067d234eda60e3f243568bd4e760..ded1cd60e34b4ab0795ee664a0505a5766274f52 100644 (file)
@@ -1528,7 +1528,7 @@ std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
 {
        std::vector<RTLIL::Cell*> result;
-       result.reserve(wires_.size());
+       result.reserve(cells_.size());
        for (auto &it : cells_)
                if (design->selected(this, it.second))
                        result.push_back(it.second);