targets/core: generate status/BIST ios

diff --git a/targets/core.py b/targets/core.py
index d2e5865992a51c3ff6e5048c5436fdd50193c50e..e1ad7aa9cf47eda97a0448b2f8f638c79c5480a5 100644 (file)
--- a/targets/core.py
+++ b/targets/core.py
@@ -11,7 +11,7 @@ class LiteSATACore(Module):
 
                # SATA PHY/Core/Frontend
                self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "sata_gen2", clk_freq)
-               self.submodules.sata = LiteSATA(self.sata_phy)
+               self.submodules.sata = LiteSATA(self.sata_phy, with_bist=True)
 
                # Get user ports from crossbar
                self.user_ports = self.sata.crossbar.get_ports(nports)
@@ -25,6 +25,25 @@ class LiteSATACore(Module):
                        if isinstance(obj, Signal):
                                ios = ios.union({obj})
 
+               # Status
+               ios = ios.union({
+                       self.sata_phy.crg.ready,
+                       self.sata_phy.ctrl.ready
+               })
+
+               # BIST
+               if hasattr(self.sata, "bist"):
+                       for bist_unit in ["generator", "checker"]:
+                               for signal in ["start", "sector", "count", "random", "done", "aborted", "errors"]:
+                                       ios = ios.union({getattr(getattr(self.sata.bist, bist_unit), signal)})
+                       ios = ios.union({
+                               self.sata.bist.identify.start,
+                               self.sata.bist.identify.done,
+                               self.sata.bist.identify.source.stb,
+                               self.sata.bist.identify.source.data,
+                               self.sata.bist.identify.source.ack
+                       })
+
                # User ports
                def _iter_layout(layout):
                        for e in layout: