must only try to connect jtag when variant requests it

diff --git a/sim.py b/sim.py
index 306adf41d2f2b260ad47a2bfeaa9b2de6c406747..550339e46a22169fe19510da5d3032202f3f8aec 100755 (executable)
--- a/sim.py
+++ b/sim.py
@@ -165,21 +165,22 @@ class LibreSoCSim(SoCSDRAM):
             self.add_constant("MEMTEST_DATA_DEBUG", 1)
 
 
-        # add JTAG platform pins
-        platform.add_extension([
-            ("jtag", 0,
-                Subsignal("tck",  Pins(1)),
-                Subsignal("tms", Pins(1)),
-                Subsignal("tdi", Pins(1)),
-                Subsignal("tdo", Pins(1)),
-            )
-        ])
+        if "jtag" in variant:
+            # add JTAG platform pins
+            platform.add_extension([
+                ("jtag", 0,
+                    Subsignal("tck",  Pins(1)),
+                    Subsignal("tms", Pins(1)),
+                    Subsignal("tdi", Pins(1)),
+                    Subsignal("tdo", Pins(1)),
+                )
+            ])
 
-        jtagpads = platform.request("jtag")
-        self.comb += self.cpu.jtag_tck.eq(jtagpads.tck)
-        self.comb += self.cpu.jtag_tms.eq(jtagpads.tms)
-        self.comb += self.cpu.jtag_tdi.eq(jtagpads.tdi)
-        self.comb += jtagpads.tdo.eq(self.cpu.jtag_tdo)
+            jtagpads = platform.request("jtag")
+            self.comb += self.cpu.jtag_tck.eq(jtagpads.tck)
+            self.comb += self.cpu.jtag_tms.eq(jtagpads.tms)
+            self.comb += self.cpu.jtag_tdi.eq(jtagpads.tdi)
+            self.comb += jtagpads.tdo.eq(self.cpu.jtag_tdo)
 
 
         # Debug ---------------------------------------------------------------