When converting a sync transparent read port with const address to async
read port, nothing at all needs to be done other than clk_enable change,
and thus we have no FF cell to return. Handle this case correctly in
the helper and in its users.
if (port.addr[i].wire)
width++;
- if (width) {
+ if (width)
+ {
SigSpec sig_q = module->addWire(stringf("$%s$rdreg[%d]$q", memid.c_str(), idx), width);
SigSpec sig_d;
}
c = module->addDff(stringf("$%s$rdreg[%d]", memid.c_str(), idx), port.clk, sig_d, sig_q, port.clk_polarity);
+ } else {
+ c = nullptr;
}
}
else
for (auto &mem : Mem::get_selected_memories(module))
{
bool changed = false;
- for (int i = 0; i < GetSize(mem.rd_ports); i++)
- if (mem.extract_rdff(i, &initvals))
+ for (int i = 0; i < GetSize(mem.rd_ports); i++) {
+ if (mem.rd_ports[i].clk_enable) {
+ mem.extract_rdff(i, &initvals);
changed = true;
+ }
+ }
if (changed)
mem.emit();