Add $dlatch support to write_verilog

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index bdf70505677624f4e3af8e39584dde9572aed630..b50dc12afee2cf3cb2822fdee5469994e0b6ccf8 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -897,6 +897,42 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
                return true;
        }
 
+       if (cell->type == "$dlatch")
+       {
+               RTLIL::SigSpec sig_en;
+               bool pol_en = false;
+
+               sig_en = cell->getPort("\\EN");
+               pol_en = cell->parameters["\\EN_POLARITY"].as_bool();
+
+               std::string reg_name = cellname(cell);
+               bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name);
+
+               if (!out_is_reg_wire) {
+                       f << stringf("%s" "reg [%d:0] %s", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str());
+                       dump_reg_init(f, cell->getPort("\\Q"));
+                       f << ";\n";
+               }
+
+               f << stringf("%s" "always @*\n", indent.c_str());
+
+               f << stringf("%s" "  if (%s", indent.c_str(), pol_en ? "" : "!");
+               dump_sigspec(f, sig_en);
+               f << stringf(")\n");
+
+               f << stringf("%s" "    %s = ", indent.c_str(), reg_name.c_str());
+               dump_cell_expr_port(f, cell, "D", false);
+               f << stringf(";\n");
+
+               if (!out_is_reg_wire) {
+                       f << stringf("%s" "assign ", indent.c_str());
+                       dump_sigspec(f, cell->getPort("\\Q"));
+                       f << stringf(" = %s;\n", reg_name.c_str());
+               }
+
+               return true;
+       }
+
        if (cell->type == "$mem")
        {
                RTLIL::IdString memid = cell->parameters["\\MEMID"].decode_string();
@@ -1537,6 +1573,8 @@ struct VerilogBackend : public Backend {
 
                reg_ct.insert("$dff");
                reg_ct.insert("$adff");
+               reg_ct.insert("$dffe");
+               reg_ct.insert("$dlatch");
 
                reg_ct.insert("$_DFF_N_");
                reg_ct.insert("$_DFF_P_");