re PR target/64479 ([SH] wrong optimization delayed-branch)

gcc/
	PR target/64479
	* rtlanal.c (set_reg_p): Handle SEQUENCE constructs.

From-SVN: r219506

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 89e22ea7ec56148f7fca8db276cb9b761337bc76..8b86f54573de622cee096525915f33e3f352fe87 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2015-01-13  Oleg Endo  <olegendo@gcc.gnu.org>
+
+       PR target/64479
+       * rtlanal.c (set_reg_p): Handle SEQUENCE constructs.
+
 2015-01-12  Kaz Kojima  <kkojima@gcc.gnu.org>
 
        * config/sh/sh.c (sh_atomic_assign_expand_fenv): New function.

diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index a63bd400c281618f73e7fa9aa91c22ab04f6be1a..4aadac22431ad419d82b15d9d10064ff2d97f690 100644 (file)
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -1000,6 +1000,17 @@ reg_set_between_p (const_rtx reg, const rtx_insn *from_insn,
 int
 reg_set_p (const_rtx reg, const_rtx insn)
 {
+  /* After delay slot handling, call and branch insns might be in a
+     sequence.  Check all the elements there.  */
+  if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE)
+    {
+      for (int i = 0; i < XVECLEN (PATTERN (insn), 0); ++i)
+       if (reg_set_p (reg, XVECEXP (PATTERN (insn), 0, i)))
+         return true;
+
+      return false;
+    }
+
   /* We can be passed an insn or part of one.  If we are passed an insn,
      check if a side-effect of the insn clobbers REG.  */
   if (INSN_P (insn)
@@ -1011,7 +1022,7 @@ reg_set_p (const_rtx reg, const_rtx insn)
                                               GET_MODE (reg), REGNO (reg)))
                  || MEM_P (reg)
                  || find_reg_fusage (insn, CLOBBER, reg)))))
-    return 1;
+    return true;
 
   return set_of (reg, insn) != NULL_RTX;
 }