(no commit message)

diff --git a/openpower/sv/rfc/ls007.mdwn b/openpower/sv/rfc/ls007.mdwn
index c19c7b4727bdb470da26200a7d5a6b9308012f0b..9385444c4ac50095ea42792dbb87a916e6ebdfbc 100644 (file)
--- a/openpower/sv/rfc/ls007.mdwn
+++ b/openpower/sv/rfc/ls007.mdwn
@@ -52,10 +52,8 @@ Instructions added
 **Keywords**:
 
 ```
-GPR, CR-Field, bit-manipulation, ternary, binary, dynamic, look-up-table
-(LUT), FPGA, JIT
+GPR, CR-Field, bit-manipulation, ternary, binary, dynamic, look-up-table (LUT), FPGA, JIT
 ```
-
 **Motivation**
 
 * `ternlogi` is similar to existing `and`/`or`/`xor`/etc. instructions, but