+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
-clock=1
-commitToDecodeDelay=1
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-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-phase=0
-predType=tournament
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-renameToDecodeDelay=1
-renameToFetchDelay=1
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-system=system
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-wbDepth=1
-wbWidth=8
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
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-latency=1
-lifo=false
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-mshrs=10
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-prefetch_latency=10
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-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
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-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
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-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
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-opClass=IprAccess
-opLat=3
-
-[system.cpu.icache]
-type=BaseCache
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-latency=1
-lifo=false
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-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
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-compression_latency=0
-hash_delay=1
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-latency=1
-lifo=false
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-mshrs=10
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-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/o3-timing
-egid=100
-env=
-euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-zero=false
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=vortex lendian.raw
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/o3-timing
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
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-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
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-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
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-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
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-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
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-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu]
-type=DerivO3CPU
-clock=1
-phase=0
-numThreads=1
-activity=0
-workload=system.cpu.workload
-checker=null
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
-defer_registration=false
-function_trace=false
-function_trace_start=0
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
-[statsreset]
-reset_cycle=0
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 13202034 # Number of BTB hits
-global.BPredUnit.BTBLookups 22107115 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 30370 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 454360 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 16498204 # Number of conditional branches predicted
-global.BPredUnit.lookups 27047110 # Number of BP lookups
-global.BPredUnit.usedRAS 4878193 # Number of times the RAS was used to get a target.
-host_inst_rate 69520 # Simulator instruction rate (inst/s)
-host_mem_usage 239908 # Number of bytes of host memory used
-host_seconds 1144.87 # Real time elapsed on the host
-host_tick_rate 987535 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 14725847 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 11490673 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 28863760 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 16312214 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 79591756 # Number of instructions simulated
-sim_seconds 0.001131 # Number of seconds simulated
-sim_ticks 1130602014 # Number of ticks simulated
-system.cpu.commit.COM:branches 13754477 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 3893678 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 89505192
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 62882698 7025.59%
- 1 8753972 978.04%
- 2 5175203 578.20%
- 3 3243621 362.39%
- 4 2169519 242.39%
- 5 1432847 160.09%
- 6 1161882 129.81%
- 7 791772 88.46%
- 8 3893678 435.02%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 88340672 # Number of instructions committed
-system.cpu.commit.COM:loads 20379399 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 35224018 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 359967 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 21665941 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 79591756 # Number of Instructions Simulated
-system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
-system.cpu.cpi 14.205014 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 14.205014 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 19540231 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 4453.766964 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3237.815878 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 19382637 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 701886951 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.008065 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 157594 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 95950 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 199591922 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.003155 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 61644 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 4830.124895 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3999.409028 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 13942631 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 3239786953 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.045899 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 670746 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 527274 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 573803212 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.009818 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 143472 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs 3332.672727 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 3759.399862 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 162.470348 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 110 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 125901 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 366594 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 473312202 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 34153608 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 4758.521747 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 3770.525625 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 33325268 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 3941673904 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.024253 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 828340 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 623224 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 773395134 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.006006 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 205116 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 34153608 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 4758.521747 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 3770.525625 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 33325268 # number of overall hits
-system.cpu.dcache.overall_miss_latency 3941673904 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.024253 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 828340 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 623224 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 773395134 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.006006 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 205116 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 201020 # number of replacements
-system.cpu.dcache.sampled_refs 205116 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4057.039034 # Cycle average of tags in use
-system.cpu.dcache.total_refs 33325268 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 27784000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 147771 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 11948269 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 95198 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 3558048 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 131593428 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 51674084 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 25481309 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 4702945 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 281359 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 401531 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 27047110 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 22733117 # Number of cache lines fetched
-system.cpu.fetch.Cycles 51481541 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 159026 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 148267180 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 3966980 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.287100 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 22733117 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 18080227 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.573826 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 94208138
-system.cpu.fetch.rateDist.min_value 0
- 0 65459635 6948.41%
- 1 1687117 179.08%
- 2 1748812 185.63%
- 3 1938924 205.81%
- 4 6981531 741.08%
- 5 6100701 647.58%
- 6 758078 80.47%
- 7 1979150 210.08%
- 8 7554190 801.86%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 22733116 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 3345.551905 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 2359.548288 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 22631700 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 339292492 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.004461 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 101416 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 13878 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 206550138 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.003851 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 87538 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets 3731.567010 # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 258.538675 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 97 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 361962 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 22733116 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 3345.551905 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 2359.548288 # average overall mshr miss latency
-system.cpu.icache.demand_hits 22631700 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 339292492 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.004461 # miss rate for demand accesses
-system.cpu.icache.demand_misses 101416 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 13878 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 206550138 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.003851 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 87538 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 22733116 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 3345.551905 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 2359.548288 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 22631700 # number of overall hits
-system.cpu.icache.overall_miss_latency 339292492 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.004461 # miss rate for overall accesses
-system.cpu.icache.overall_misses 101416 # number of overall misses
-system.cpu.icache.overall_mshr_hits 13878 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 206550138 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.003851 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 87538 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 85490 # number of replacements
-system.cpu.icache.sampled_refs 87537 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1835.330854 # Cycle average of tags in use
-system.cpu.icache.total_refs 22631700 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 1036393877 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 14379719 # Number of branches executed
-system.cpu.iew.EXEC:nop 9265977 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.989418 # Inst execution rate
-system.cpu.iew.EXEC:refs 43156162 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 15338261 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 46157981 # num instructions consuming a value
-system.cpu.iew.WB:count 86105601 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.741496 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 34225955 # num instructions producing a value
-system.cpu.iew.WB:rate 0.913993 # insts written-back per cycle
-system.cpu.iew.WB:sent 86171133 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 389534 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 3213991 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 28863760 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 4784 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 1402526 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 16312214 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 110003367 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 27817901 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 453087 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 93211232 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 28742 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 12962 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 4702945 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 194395 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1528 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 6922047 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 1365052 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5008 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 3825 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1528 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 8484361 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 1467595 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 3825 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 102872 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 286662 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.070398 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.070398 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 93664319 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 0 0.00% # Type of FU issued
- IntAlu 49995908 53.38% # Type of FU issued
- IntMult 43196 0.05% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 123595 0.13% # Type of FU issued
- FloatCmp 86 0.00% # Type of FU issued
- FloatCvt 122386 0.13% # Type of FU issued
- FloatMult 51 0.00% # Type of FU issued
- FloatDiv 37853 0.04% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 27919833 29.81% # Type of FU issued
- MemWrite 15421411 16.46% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 1229792 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013130 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 83895 6.82% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 589327 47.92% # attempts to use FU when none available
- MemWrite 556570 45.26% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 94208138
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 54322746 5766.25%
- 1 13333515 1415.33%
- 2 10626230 1127.95%
- 3 8813553 935.54%
- 4 4440243 471.32%
- 5 1597603 169.58%
- 6 685526 72.77%
- 7 334234 35.48%
- 8 54488 5.78%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 0.994227 # Inst issue rate
-system.cpu.iq.iqInstsAdded 100732606 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 93664319 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 4784 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 20911338 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 73995 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 201 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 16334966 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 292646 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 3929.598028 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2043.469607 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 122985 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 666699531 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.579748 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 169661 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 346697097 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.579748 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 169661 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 147771 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 147307 # number of Writeback hits
-system.cpu.l2cache.Writeback_miss_rate 0.003140 # miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_misses 464 # number of Writeback misses
-system.cpu.l2cache.Writeback_mshr_miss_rate 0.003140 # mshr miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_mshr_misses 464 # number of Writeback MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 1.593139 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 292646 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 3929.598028 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2043.469607 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 122985 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 666699531 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.579748 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 169661 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 346697097 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.579748 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 169661 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 440417 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 3918.880417 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2043.469607 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 270292 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 666699531 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.386282 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 170125 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 346697097 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.385228 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 169661 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 136892 # number of replacements
-system.cpu.l2cache.sampled_refs 169660 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 30349.297230 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 270292 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 625483000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 115938 # number of writebacks
-system.cpu.numCycles 94208138 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 7563765 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 87866 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 52361095 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 3315491 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 3509 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 154857350 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 130101763 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 82913656 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 25182526 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 4702945 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 3542613 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 30366775 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 855194 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 4773 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 6398047 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 4771 # count of temporary serializing insts renamed
-system.cpu.timesIdled 275758 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-
- SYSTEM TYPE...
- __ZTC__ := False
- __UNIX__ := True
- __RISC__ := True
- SPEC_CPU2000_LP64 := True
- __MAC__ := False
- __BCC__ := False
- __BORLANDC__ := False
- __GUI__ := False
- __WTC__ := False
- __HP__ := False
-
- CODE OPTIONS...
- __MACROIZE_HM__ := True
- __MACROIZE_MEM__ := True
- ENV01 := True
- USE_HPP_STYPE_HDRS := False
- USE_H_STYPE_HDRS := False
-
- CODE INCLUSION PARAMETERS...
- INCLUDE_ALL_CODE := False
- INCLUDE_DELETE_CODE := True
- __SWAP_GRP_POS__ := True
- __INCLUDE_MTRX__ := False
- __BAD_CODE__ := False
- API_INCLUDE := False
- BE_CAREFUL := False
- OLDWAY := False
- NOTUSED := False
-
- SYSTEM PARAMETERS...
- EXT_ENUM := 999999999L
- CHUNK_CONSTANT := 55555555
- CORE_CONSTANT := 55555555
- CORE_LIMIT := 20971520
- CorePage_Size := 384000
- ALIGN_BYTES := True
- CORE_BLOCK_ALIGN := 8
- FAR_MEM := False
-
- MEMORY MANAGEMENT PARAMETERS...
- SYSTEM_ALLOC := True
- SYSTEM_FREESTORE := True
- __NO_DISKCACHE__ := False
- __FREEZE_VCHUNKS__ := True
- __FREEZE_GRP_PACKETS__ := True
- __MINIMIZE_TREE_CACHE__:= True
-
- SYSTEM STD PARAMETERS...
- __STDOUT__ := False
- NULL := 0
- LPTR := False
- False_Status := 1
- True_Status := 0
- LARGE := True
- TWOBYTE_BOOL := False
- __NOSTR__ := False
-
- MEMORY VALIDATION PARAMETERS...
- CORE_CRC_CHECK := False
- VALIDATE_MEM_CHUNKS := False
-
- SYSTEM DEBUG OPTIONS...
- DEBUG := False
- MCSTAT := False
- TRACKBACK := False
- FLUSH_FILES := False
- DEBUG_CORE0 := False
- DEBUG_RISC := False
- __TREE_BUG__ := False
- __TRACK_FILE_READS__ := False
- PAGE_SPACE := False
- LEAVE_NO_TRACE := True
- NULL_TRACE_STRS := False
-
- TIME PARAMETERS...
- CLOCK_IS_LONG := False
- __DISPLAY_TIME__ := False
- __TREE_TIME__ := False
- __DISPLAY_ERRORS__ := False
-
- API MACROS...
- __BMT01__ := True
- OPTIMIZE := True
-
- END OF DEFINES.
-
-
-
- ... IMPLODE MEMORY ...
-
- SWAP to DiskCache := False
-
- FREEZE_GRP_PACKETS:= True
-
- QueBug := 1000
-
- sizeof(boolean) = 4
- sizeof(sizetype) = 4
- sizeof(chunkstruc) = 32
-
- sizeof(shorttype ) = 2
- sizeof(idtype ) = 2
- sizeof(sizetype ) = 4
- sizeof(indextype ) = 4
- sizeof(numtype ) = 4
- sizeof(handletype) = 4
- sizeof(tokentype ) = 8
-
- sizeof(short ) = 2
- sizeof(int ) = 4
-
- sizeof(lt64 ) = 4
- sizeof(farlongtype) = 4
- sizeof(long ) = 8
- sizeof(longaddr ) = 8
-
- sizeof(float ) = 4
- sizeof(double ) = 8
-
- sizeof(addrtype ) = 8
- sizeof(char * ) = 8
- ALLOC CORE_1 :: 16
- BHOOLE NATH
-
- OPEN File ./input/lendian.rnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 2030c0
- DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
- DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
- DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
- DB Handle Chunk's StackPtr = 20797
-
- DB[ 1] LOADED; Handles= 20797
- KERNEL in CORE[ 1] Restored @ 40054800
-
- OPEN File ./input/lendian.wnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 21c40
- DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
- DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
- DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
- DB Handle Chunk's StackPtr = 17
-
- DB[ 2] LOADED; Handles= 17
- VORTEx_Status == -8 || fffffff8
-
- BE HERE NOW !!!
-
-
-
- ... VORTEx ON LINE ...
-
-
- ... END OF SESSION ...
+++ /dev/null
- CREATE Db Header and Db Primal ...
- NEW DB [ 3] Created.
-
-VORTEX INPUT PARAMETERS::
- MESSAGE FileName: smred.msg
- OUTPUT FileName: smred.out
- DISK CACHE FileName: NULL
- PART DB FileName: parts.db
- DRAW DB FileName: draw.db
- PERSON DB FileName: emp.db
- PERSONS Data FileName: ./input/persons.250
- PARTS Count : 100
- OUTER Loops : 1
- INNER Loops : 1
- LOOKUP Parts : 25
- DELETE Parts : 10
- STUFF Parts : 10
- DEPTH Traverse: 5
- % DECREASE Parts : 0
- % INCREASE LookUps : 0
- % INCREASE Deletes : 0
- % INCREASE Stuffs : 0
- FREEZE_PACKETS : 1
- ALLOC_CHUNKS : 10000
- EXTEND_CHUNKS : 5000
- DELETE Draw objects : True
- DELETE Part objects : False
- QUE_BUG : 1000
- VOID_BOUNDARY : 67108864
- VOID_RESERVE : 1048576
-
- COMMIT_DBS : False
-
-
-
- BMT TEST :: files...
- EdbName := PartLib
- EdbFileName := parts.db
- DrwName := DrawLib
- DrwFileName := draw.db
- EmpName := PersonLib
- EmpFileName := emp.db
-
- Swap to DiskCache := False
- Freeze the cache := True
-
-
- BMT TEST :: parms...
- DeBug modulo := 1000
- Create Parts count:= 100
- Outer Loops := 1
- Inner Loops := 1
- Look Ups := 25
- Delete Parts := 10
- Stuff Parts := 10
- Traverse Limit := 5
- Delete Draws := True
- Delete Parts := False
- Delete ALL Parts := after every <mod 0>Outer Loop
-
- INITIALIZE LIBRARY ::
-
- INITIALIZE SCHEMA ::
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 4] Created.
- PartLibCreate:: Db[ 4]; VpartsDir= 1
-
- Part Count= 1
-
- Initialize the Class maps
- LIST HEADS loaded ... DbListHead_Class = 207
- DbListNode_Class = 206
-
-...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
-
-
-...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
-
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 5] Created.
- DrawLibCreate:: Db[ 5]; VpartsDir= 1
-
- Initialize the Class maps of this schema.
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 6] Created.
-
- ***NOTE*** Persons Library Extended!
-
- Create <131072> Persons.
- ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
-
- LAST Person Read::
- ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
-
- BUILD <Query0> for <Part2> class::
-
- if (link[1].length >= 5) ::
-
- Build Query2 for <Address> class::
-
- if (State == CA || State == T*)
-
- Build Query1 for <Person> class::
-
- if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
-
- BUILD <Query3> for <DrawObj> class::
-
- if (Id >= 3000
- && (Id >= 3000 && Id <= 3001)
- && Id >= 3002)
-
- BUILD <Query4> for <NamedDrawObj> class::
-
- if (Nam == Pre*
- || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
- || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
- && Id <= 7)
- SEED := 1008; Swap = False; RgnEntries = 135
-
- OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
-
- Create 100 New Parts
- Create Part 1. Token[ 4: 2].
-
- < 100> Parts Created. CurrentId= 100
-
- Connect each instantiated Part TO 3 unique Parts
- Connect Part 1. Token[ 4: 2]
- Connect Part 25. Token[ 4: 26] FromList= 26.
- Connect Part 12. Token[ 4: 13] FromList= 13.
- Connect Part 59. Token[ 4: 60] FromList= 60.
-
- SET <DrawObjs> entries::
- 1. [ 5: 5] := <1 >; @[: 6]
- Iteration count = 100
-
- SET <NamedDrawObjs> entries::
- 1. [ 5: 39] := <14 >;
- Iteration count = 12
-
- SET <LibRectangles> entries::
- 1. [ 5: 23] := <8 >; @[: 24]
- Iteration count = 12
-
- LIST <DbRectangles> entries::
- 1. [ 5: 23]
- Iteration count = 12
-
- SET <PersonNames > entries::
- Iteration count = 250
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 100
- < 100> Part images' Committed.
- < 0> are Named.
- < 50> Point images' Committed.
- < 81> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. TestObj Committed.
- < 0> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
- < 0> CartesianPoint images' Committed.
-
- BEGIN Inner Loop Sequence::.
-
- INNER LOOP [ 1: 1] :
-
- LOOK UP 25 Random Parts and Export each Part.
-
- LookUp for 26 parts; Asserts = 8
- <Part2 > Asserts = 2; NULL Asserts = 3.
- <DrawObj > Asserts = 0; NULL Asserts = 5.
- <NamedObj > Asserts = 0; NULL Asserts = 0.
- <Person > Asserts = 0; NULL Asserts = 5.
- <TestObj > Asserts = 60; NULL Asserts = 0.
-
- DELETE 10 Random Parts.
-
- PartDelete :: Token[ 4: 91].
- PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
- DisConnect link [ 0]:= 50; PartToken[ 51: 51].
- DisConnect link [ 1]:= 17; PartToken[ 18: 18].
- DisConnect link [ 2]:= 72; PartToken[ 73: 73].
- DeleteFromList:: Vchunk[ 4: 91]. (* 1)
- DisConnect FromList[ 0]:= 56; Token[ 57: 57].
- Vlists[ 89] := 100;
-
- Delete for 11 parts;
-
- Traverse Count= 0
-
- TRAVERSE PartId[ 6] and all Connections to 5 Levels
- SEED In Traverse Part [ 4: 65] @ Level = 4.
-
- Traverse Count= 357
- Traverse Asserts = 5. True Tests = 1
- < 5> DrawObj objects DELETED.
- < 2> are Named.
- < 2> Point objects DELETED.
-
- CREATE 10 Additional Parts
-
- Create 10 New Parts
- Create Part 101. Token[ 4: 102].
-
- < 10> Parts Created. CurrentId= 110
-
- Connect each instantiated Part TO 3 unique Parts
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 110
- < 81> Part images' Committed.
- < 0> are Named.
- < 38> Point images' Committed.
- < 31> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Committed.
- < 15> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
- < 16> CartesianPoint images' Committed.
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Deleted.
- < 15> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
- < 16> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
-
- END INNER LOOP [ 1: 1].
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- < 0> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- < 0> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
- STATUS= -201
-V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
+++ /dev/null
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
-warn: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=workload
-clock=1
-cpu_id=0
-defer_registration=false
-function_trace=false
-function_trace_start=0
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-phase=0
-progress_interval=0
-simulate_stalls=false
-system=system
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic
-egid=100
-env=
-euid=100
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-zero=false
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=vortex lendian.raw
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu]
-type=AtomicSimpleCPU
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-system=system
-cpu_id=0
-workload=system.cpu.workload
-clock=1
-phase=0
-defer_registration=false
-width=1
-function_trace=false
-function_trace_start=0
-simulate_stalls=false
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[statsreset]
-reset_cycle=0
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1347543 # Simulator instruction rate (inst/s)
-host_mem_usage 179988 # Number of bytes of host memory used
-host_seconds 65.56 # Real time elapsed on the host
-host_tick_rate 1347535 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 88340674 # Number of instructions simulated
-sim_seconds 0.000088 # Number of seconds simulated
-sim_ticks 88340673 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 88340674 # number of cpu cycles simulated
-system.cpu.num_insts 88340674 # Number of instructions executed
-system.cpu.num_refs 35224019 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-
- SYSTEM TYPE...
- __ZTC__ := False
- __UNIX__ := True
- __RISC__ := True
- SPEC_CPU2000_LP64 := True
- __MAC__ := False
- __BCC__ := False
- __BORLANDC__ := False
- __GUI__ := False
- __WTC__ := False
- __HP__ := False
-
- CODE OPTIONS...
- __MACROIZE_HM__ := True
- __MACROIZE_MEM__ := True
- ENV01 := True
- USE_HPP_STYPE_HDRS := False
- USE_H_STYPE_HDRS := False
-
- CODE INCLUSION PARAMETERS...
- INCLUDE_ALL_CODE := False
- INCLUDE_DELETE_CODE := True
- __SWAP_GRP_POS__ := True
- __INCLUDE_MTRX__ := False
- __BAD_CODE__ := False
- API_INCLUDE := False
- BE_CAREFUL := False
- OLDWAY := False
- NOTUSED := False
-
- SYSTEM PARAMETERS...
- EXT_ENUM := 999999999L
- CHUNK_CONSTANT := 55555555
- CORE_CONSTANT := 55555555
- CORE_LIMIT := 20971520
- CorePage_Size := 384000
- ALIGN_BYTES := True
- CORE_BLOCK_ALIGN := 8
- FAR_MEM := False
-
- MEMORY MANAGEMENT PARAMETERS...
- SYSTEM_ALLOC := True
- SYSTEM_FREESTORE := True
- __NO_DISKCACHE__ := False
- __FREEZE_VCHUNKS__ := True
- __FREEZE_GRP_PACKETS__ := True
- __MINIMIZE_TREE_CACHE__:= True
-
- SYSTEM STD PARAMETERS...
- __STDOUT__ := False
- NULL := 0
- LPTR := False
- False_Status := 1
- True_Status := 0
- LARGE := True
- TWOBYTE_BOOL := False
- __NOSTR__ := False
-
- MEMORY VALIDATION PARAMETERS...
- CORE_CRC_CHECK := False
- VALIDATE_MEM_CHUNKS := False
-
- SYSTEM DEBUG OPTIONS...
- DEBUG := False
- MCSTAT := False
- TRACKBACK := False
- FLUSH_FILES := False
- DEBUG_CORE0 := False
- DEBUG_RISC := False
- __TREE_BUG__ := False
- __TRACK_FILE_READS__ := False
- PAGE_SPACE := False
- LEAVE_NO_TRACE := True
- NULL_TRACE_STRS := False
-
- TIME PARAMETERS...
- CLOCK_IS_LONG := False
- __DISPLAY_TIME__ := False
- __TREE_TIME__ := False
- __DISPLAY_ERRORS__ := False
-
- API MACROS...
- __BMT01__ := True
- OPTIMIZE := True
-
- END OF DEFINES.
-
-
-
- ... IMPLODE MEMORY ...
-
- SWAP to DiskCache := False
-
- FREEZE_GRP_PACKETS:= True
-
- QueBug := 1000
-
- sizeof(boolean) = 4
- sizeof(sizetype) = 4
- sizeof(chunkstruc) = 32
-
- sizeof(shorttype ) = 2
- sizeof(idtype ) = 2
- sizeof(sizetype ) = 4
- sizeof(indextype ) = 4
- sizeof(numtype ) = 4
- sizeof(handletype) = 4
- sizeof(tokentype ) = 8
-
- sizeof(short ) = 2
- sizeof(int ) = 4
-
- sizeof(lt64 ) = 4
- sizeof(farlongtype) = 4
- sizeof(long ) = 8
- sizeof(longaddr ) = 8
-
- sizeof(float ) = 4
- sizeof(double ) = 8
-
- sizeof(addrtype ) = 8
- sizeof(char * ) = 8
- ALLOC CORE_1 :: 16
- BHOOLE NATH
-
- OPEN File ./input/lendian.rnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 2030c0
- DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
- DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
- DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
- DB Handle Chunk's StackPtr = 20797
-
- DB[ 1] LOADED; Handles= 20797
- KERNEL in CORE[ 1] Restored @ 40054800
-
- OPEN File ./input/lendian.wnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 21c40
- DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
- DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
- DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
- DB Handle Chunk's StackPtr = 17
-
- DB[ 2] LOADED; Handles= 17
- VORTEx_Status == -8 || fffffff8
-
- BE HERE NOW !!!
-
-
-
- ... VORTEx ON LINE ...
-
-
- ... END OF SESSION ...
+++ /dev/null
- CREATE Db Header and Db Primal ...
- NEW DB [ 3] Created.
-
-VORTEX INPUT PARAMETERS::
- MESSAGE FileName: smred.msg
- OUTPUT FileName: smred.out
- DISK CACHE FileName: NULL
- PART DB FileName: parts.db
- DRAW DB FileName: draw.db
- PERSON DB FileName: emp.db
- PERSONS Data FileName: ./input/persons.250
- PARTS Count : 100
- OUTER Loops : 1
- INNER Loops : 1
- LOOKUP Parts : 25
- DELETE Parts : 10
- STUFF Parts : 10
- DEPTH Traverse: 5
- % DECREASE Parts : 0
- % INCREASE LookUps : 0
- % INCREASE Deletes : 0
- % INCREASE Stuffs : 0
- FREEZE_PACKETS : 1
- ALLOC_CHUNKS : 10000
- EXTEND_CHUNKS : 5000
- DELETE Draw objects : True
- DELETE Part objects : False
- QUE_BUG : 1000
- VOID_BOUNDARY : 67108864
- VOID_RESERVE : 1048576
-
- COMMIT_DBS : False
-
-
-
- BMT TEST :: files...
- EdbName := PartLib
- EdbFileName := parts.db
- DrwName := DrawLib
- DrwFileName := draw.db
- EmpName := PersonLib
- EmpFileName := emp.db
-
- Swap to DiskCache := False
- Freeze the cache := True
-
-
- BMT TEST :: parms...
- DeBug modulo := 1000
- Create Parts count:= 100
- Outer Loops := 1
- Inner Loops := 1
- Look Ups := 25
- Delete Parts := 10
- Stuff Parts := 10
- Traverse Limit := 5
- Delete Draws := True
- Delete Parts := False
- Delete ALL Parts := after every <mod 0>Outer Loop
-
- INITIALIZE LIBRARY ::
-
- INITIALIZE SCHEMA ::
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 4] Created.
- PartLibCreate:: Db[ 4]; VpartsDir= 1
-
- Part Count= 1
-
- Initialize the Class maps
- LIST HEADS loaded ... DbListHead_Class = 207
- DbListNode_Class = 206
-
-...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
-
-
-...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
-
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 5] Created.
- DrawLibCreate:: Db[ 5]; VpartsDir= 1
-
- Initialize the Class maps of this schema.
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 6] Created.
-
- ***NOTE*** Persons Library Extended!
-
- Create <131072> Persons.
- ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
-
- LAST Person Read::
- ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
-
- BUILD <Query0> for <Part2> class::
-
- if (link[1].length >= 5) ::
-
- Build Query2 for <Address> class::
-
- if (State == CA || State == T*)
-
- Build Query1 for <Person> class::
-
- if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
-
- BUILD <Query3> for <DrawObj> class::
-
- if (Id >= 3000
- && (Id >= 3000 && Id <= 3001)
- && Id >= 3002)
-
- BUILD <Query4> for <NamedDrawObj> class::
-
- if (Nam == Pre*
- || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
- || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
- && Id <= 7)
- SEED := 1008; Swap = False; RgnEntries = 135
-
- OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
-
- Create 100 New Parts
- Create Part 1. Token[ 4: 2].
-
- < 100> Parts Created. CurrentId= 100
-
- Connect each instantiated Part TO 3 unique Parts
- Connect Part 1. Token[ 4: 2]
- Connect Part 25. Token[ 4: 26] FromList= 26.
- Connect Part 12. Token[ 4: 13] FromList= 13.
- Connect Part 59. Token[ 4: 60] FromList= 60.
-
- SET <DrawObjs> entries::
- 1. [ 5: 5] := <1 >; @[: 6]
- Iteration count = 100
-
- SET <NamedDrawObjs> entries::
- 1. [ 5: 39] := <14 >;
- Iteration count = 12
-
- SET <LibRectangles> entries::
- 1. [ 5: 23] := <8 >; @[: 24]
- Iteration count = 12
-
- LIST <DbRectangles> entries::
- 1. [ 5: 23]
- Iteration count = 12
-
- SET <PersonNames > entries::
- Iteration count = 250
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 100
- < 100> Part images' Committed.
- < 0> are Named.
- < 50> Point images' Committed.
- < 81> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. TestObj Committed.
- < 0> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
- < 0> CartesianPoint images' Committed.
-
- BEGIN Inner Loop Sequence::.
-
- INNER LOOP [ 1: 1] :
-
- LOOK UP 25 Random Parts and Export each Part.
-
- LookUp for 26 parts; Asserts = 8
- <Part2 > Asserts = 2; NULL Asserts = 3.
- <DrawObj > Asserts = 0; NULL Asserts = 5.
- <NamedObj > Asserts = 0; NULL Asserts = 0.
- <Person > Asserts = 0; NULL Asserts = 5.
- <TestObj > Asserts = 60; NULL Asserts = 0.
-
- DELETE 10 Random Parts.
-
- PartDelete :: Token[ 4: 91].
- PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
- DisConnect link [ 0]:= 50; PartToken[ 51: 51].
- DisConnect link [ 1]:= 17; PartToken[ 18: 18].
- DisConnect link [ 2]:= 72; PartToken[ 73: 73].
- DeleteFromList:: Vchunk[ 4: 91]. (* 1)
- DisConnect FromList[ 0]:= 56; Token[ 57: 57].
- Vlists[ 89] := 100;
-
- Delete for 11 parts;
-
- Traverse Count= 0
-
- TRAVERSE PartId[ 6] and all Connections to 5 Levels
- SEED In Traverse Part [ 4: 65] @ Level = 4.
-
- Traverse Count= 357
- Traverse Asserts = 5. True Tests = 1
- < 5> DrawObj objects DELETED.
- < 2> are Named.
- < 2> Point objects DELETED.
-
- CREATE 10 Additional Parts
-
- Create 10 New Parts
- Create Part 101. Token[ 4: 102].
-
- < 10> Parts Created. CurrentId= 110
-
- Connect each instantiated Part TO 3 unique Parts
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 110
- < 81> Part images' Committed.
- < 0> are Named.
- < 38> Point images' Committed.
- < 31> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Committed.
- < 15> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
- < 16> CartesianPoint images' Committed.
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Deleted.
- < 15> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
- < 16> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
-
- END INNER LOOP [ 1: 1].
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- < 0> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- < 0> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
- STATUS= -201
-V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
+++ /dev/null
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
-warn: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus workload
-clock=1
-cpu_id=0
-defer_registration=false
-function_trace=false
-function_trace_start=0
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-phase=0
-progress_interval=0
-system=system
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing
-egid=100
-env=
-euid=100
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-zero=false
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=vortex lendian.raw
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu]
-type=TimingSimpleCPU
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-system=system
-cpu_id=0
-workload=system.cpu.workload
-clock=1
-phase=0
-defer_registration=false
-// width not specified
-function_trace=false
-function_trace_start=0
-// simulate_stalls not specified
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[statsreset]
-reset_cycle=0
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 704446 # Simulator instruction rate (inst/s)
-host_mem_usage 275648 # Number of bytes of host memory used
-host_seconds 125.40 # Real time elapsed on the host
-host_tick_rate 9716991 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 88340674 # Number of instructions simulated
-sim_seconds 0.001219 # Number of seconds simulated
-sim_ticks 1218558003 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3613.021476 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2613.021476 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 219545250 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 158780250 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 4540.238491 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3540.238491 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 651878362 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 508300362 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 169.742404 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 4264.514136 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 34685672 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 871423612 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 204343 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 667080612 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 204343 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 4264.514136 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 34685672 # number of overall hits
-system.cpu.dcache.overall_miss_latency 871423612 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 204343 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 667080612 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 204343 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 200247 # number of replacements
-system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4056.438323 # Cycle average of tags in use
-system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 28900000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 147714 # number of writebacks
-system.cpu.icache.ReadReq_accesses 88340675 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2932.969818 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1932.969818 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 88264239 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 224184481 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000865 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 147748481 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000865 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 1154.746965 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 88340675 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2932.969818 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency
-system.cpu.icache.demand_hits 88264239 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 224184481 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000865 # miss rate for demand accesses
-system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 147748481 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000865 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 88340675 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2932.969818 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 88264239 # number of overall hits
-system.cpu.icache.overall_miss_latency 224184481 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000865 # miss rate for overall accesses
-system.cpu.icache.overall_misses 76436 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 147748481 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000865 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 74391 # number of replacements
-system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1796.106842 # Cycle average of tags in use
-system.cpu.icache.total_refs 88264239 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses 280779 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 3650.218185 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1972.851350 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 112101 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 615711503 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.600750 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 168678 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 332776620 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.600750 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 168678 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 147276 # number of Writeback hits
-system.cpu.l2cache.Writeback_miss_rate 0.002965 # miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_misses 438 # number of Writeback misses
-system.cpu.l2cache.Writeback_mshr_miss_rate 0.002965 # mshr miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_mshr_misses 438 # number of Writeback MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 1.537705 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 3650.218185 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 112101 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 615711503 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.600750 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 168678 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 332776620 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.600750 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 168678 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 428493 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 3640.764345 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 259377 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 615711503 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.394676 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 169116 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 332776620 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.393654 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 168678 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 135910 # number of replacements
-system.cpu.l2cache.sampled_refs 168678 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 30401.731729 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 259377 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 667816000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 115911 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1218558003 # number of cpu cycles simulated
-system.cpu.num_insts 88340674 # Number of instructions executed
-system.cpu.num_refs 35224019 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-
- SYSTEM TYPE...
- __ZTC__ := False
- __UNIX__ := True
- __RISC__ := True
- SPEC_CPU2000_LP64 := True
- __MAC__ := False
- __BCC__ := False
- __BORLANDC__ := False
- __GUI__ := False
- __WTC__ := False
- __HP__ := False
-
- CODE OPTIONS...
- __MACROIZE_HM__ := True
- __MACROIZE_MEM__ := True
- ENV01 := True
- USE_HPP_STYPE_HDRS := False
- USE_H_STYPE_HDRS := False
-
- CODE INCLUSION PARAMETERS...
- INCLUDE_ALL_CODE := False
- INCLUDE_DELETE_CODE := True
- __SWAP_GRP_POS__ := True
- __INCLUDE_MTRX__ := False
- __BAD_CODE__ := False
- API_INCLUDE := False
- BE_CAREFUL := False
- OLDWAY := False
- NOTUSED := False
-
- SYSTEM PARAMETERS...
- EXT_ENUM := 999999999L
- CHUNK_CONSTANT := 55555555
- CORE_CONSTANT := 55555555
- CORE_LIMIT := 20971520
- CorePage_Size := 384000
- ALIGN_BYTES := True
- CORE_BLOCK_ALIGN := 8
- FAR_MEM := False
-
- MEMORY MANAGEMENT PARAMETERS...
- SYSTEM_ALLOC := True
- SYSTEM_FREESTORE := True
- __NO_DISKCACHE__ := False
- __FREEZE_VCHUNKS__ := True
- __FREEZE_GRP_PACKETS__ := True
- __MINIMIZE_TREE_CACHE__:= True
-
- SYSTEM STD PARAMETERS...
- __STDOUT__ := False
- NULL := 0
- LPTR := False
- False_Status := 1
- True_Status := 0
- LARGE := True
- TWOBYTE_BOOL := False
- __NOSTR__ := False
-
- MEMORY VALIDATION PARAMETERS...
- CORE_CRC_CHECK := False
- VALIDATE_MEM_CHUNKS := False
-
- SYSTEM DEBUG OPTIONS...
- DEBUG := False
- MCSTAT := False
- TRACKBACK := False
- FLUSH_FILES := False
- DEBUG_CORE0 := False
- DEBUG_RISC := False
- __TREE_BUG__ := False
- __TRACK_FILE_READS__ := False
- PAGE_SPACE := False
- LEAVE_NO_TRACE := True
- NULL_TRACE_STRS := False
-
- TIME PARAMETERS...
- CLOCK_IS_LONG := False
- __DISPLAY_TIME__ := False
- __TREE_TIME__ := False
- __DISPLAY_ERRORS__ := False
-
- API MACROS...
- __BMT01__ := True
- OPTIMIZE := True
-
- END OF DEFINES.
-
-
-
- ... IMPLODE MEMORY ...
-
- SWAP to DiskCache := False
-
- FREEZE_GRP_PACKETS:= True
-
- QueBug := 1000
-
- sizeof(boolean) = 4
- sizeof(sizetype) = 4
- sizeof(chunkstruc) = 32
-
- sizeof(shorttype ) = 2
- sizeof(idtype ) = 2
- sizeof(sizetype ) = 4
- sizeof(indextype ) = 4
- sizeof(numtype ) = 4
- sizeof(handletype) = 4
- sizeof(tokentype ) = 8
-
- sizeof(short ) = 2
- sizeof(int ) = 4
-
- sizeof(lt64 ) = 4
- sizeof(farlongtype) = 4
- sizeof(long ) = 8
- sizeof(longaddr ) = 8
-
- sizeof(float ) = 4
- sizeof(double ) = 8
-
- sizeof(addrtype ) = 8
- sizeof(char * ) = 8
- ALLOC CORE_1 :: 16
- BHOOLE NATH
-
- OPEN File ./input/lendian.rnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 2030c0
- DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
- DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
- DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
- DB Handle Chunk's StackPtr = 20797
-
- DB[ 1] LOADED; Handles= 20797
- KERNEL in CORE[ 1] Restored @ 40054800
-
- OPEN File ./input/lendian.wnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 21c40
- DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
- DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
- DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
- DB Handle Chunk's StackPtr = 17
-
- DB[ 2] LOADED; Handles= 17
- VORTEx_Status == -8 || fffffff8
-
- BE HERE NOW !!!
-
-
-
- ... VORTEx ON LINE ...
-
-
- ... END OF SESSION ...
+++ /dev/null
- CREATE Db Header and Db Primal ...
- NEW DB [ 3] Created.
-
-VORTEX INPUT PARAMETERS::
- MESSAGE FileName: smred.msg
- OUTPUT FileName: smred.out
- DISK CACHE FileName: NULL
- PART DB FileName: parts.db
- DRAW DB FileName: draw.db
- PERSON DB FileName: emp.db
- PERSONS Data FileName: ./input/persons.250
- PARTS Count : 100
- OUTER Loops : 1
- INNER Loops : 1
- LOOKUP Parts : 25
- DELETE Parts : 10
- STUFF Parts : 10
- DEPTH Traverse: 5
- % DECREASE Parts : 0
- % INCREASE LookUps : 0
- % INCREASE Deletes : 0
- % INCREASE Stuffs : 0
- FREEZE_PACKETS : 1
- ALLOC_CHUNKS : 10000
- EXTEND_CHUNKS : 5000
- DELETE Draw objects : True
- DELETE Part objects : False
- QUE_BUG : 1000
- VOID_BOUNDARY : 67108864
- VOID_RESERVE : 1048576
-
- COMMIT_DBS : False
-
-
-
- BMT TEST :: files...
- EdbName := PartLib
- EdbFileName := parts.db
- DrwName := DrawLib
- DrwFileName := draw.db
- EmpName := PersonLib
- EmpFileName := emp.db
-
- Swap to DiskCache := False
- Freeze the cache := True
-
-
- BMT TEST :: parms...
- DeBug modulo := 1000
- Create Parts count:= 100
- Outer Loops := 1
- Inner Loops := 1
- Look Ups := 25
- Delete Parts := 10
- Stuff Parts := 10
- Traverse Limit := 5
- Delete Draws := True
- Delete Parts := False
- Delete ALL Parts := after every <mod 0>Outer Loop
-
- INITIALIZE LIBRARY ::
-
- INITIALIZE SCHEMA ::
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 4] Created.
- PartLibCreate:: Db[ 4]; VpartsDir= 1
-
- Part Count= 1
-
- Initialize the Class maps
- LIST HEADS loaded ... DbListHead_Class = 207
- DbListNode_Class = 206
-
-...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
-
-
-...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
-
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 5] Created.
- DrawLibCreate:: Db[ 5]; VpartsDir= 1
-
- Initialize the Class maps of this schema.
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 6] Created.
-
- ***NOTE*** Persons Library Extended!
-
- Create <131072> Persons.
- ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
-
- LAST Person Read::
- ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
-
- BUILD <Query0> for <Part2> class::
-
- if (link[1].length >= 5) ::
-
- Build Query2 for <Address> class::
-
- if (State == CA || State == T*)
-
- Build Query1 for <Person> class::
-
- if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
-
- BUILD <Query3> for <DrawObj> class::
-
- if (Id >= 3000
- && (Id >= 3000 && Id <= 3001)
- && Id >= 3002)
-
- BUILD <Query4> for <NamedDrawObj> class::
-
- if (Nam == Pre*
- || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
- || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
- && Id <= 7)
- SEED := 1008; Swap = False; RgnEntries = 135
-
- OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
-
- Create 100 New Parts
- Create Part 1. Token[ 4: 2].
-
- < 100> Parts Created. CurrentId= 100
-
- Connect each instantiated Part TO 3 unique Parts
- Connect Part 1. Token[ 4: 2]
- Connect Part 25. Token[ 4: 26] FromList= 26.
- Connect Part 12. Token[ 4: 13] FromList= 13.
- Connect Part 59. Token[ 4: 60] FromList= 60.
-
- SET <DrawObjs> entries::
- 1. [ 5: 5] := <1 >; @[: 6]
- Iteration count = 100
-
- SET <NamedDrawObjs> entries::
- 1. [ 5: 39] := <14 >;
- Iteration count = 12
-
- SET <LibRectangles> entries::
- 1. [ 5: 23] := <8 >; @[: 24]
- Iteration count = 12
-
- LIST <DbRectangles> entries::
- 1. [ 5: 23]
- Iteration count = 12
-
- SET <PersonNames > entries::
- Iteration count = 250
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 100
- < 100> Part images' Committed.
- < 0> are Named.
- < 50> Point images' Committed.
- < 81> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. TestObj Committed.
- < 0> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
- < 0> CartesianPoint images' Committed.
-
- BEGIN Inner Loop Sequence::.
-
- INNER LOOP [ 1: 1] :
-
- LOOK UP 25 Random Parts and Export each Part.
-
- LookUp for 26 parts; Asserts = 8
- <Part2 > Asserts = 2; NULL Asserts = 3.
- <DrawObj > Asserts = 0; NULL Asserts = 5.
- <NamedObj > Asserts = 0; NULL Asserts = 0.
- <Person > Asserts = 0; NULL Asserts = 5.
- <TestObj > Asserts = 60; NULL Asserts = 0.
-
- DELETE 10 Random Parts.
-
- PartDelete :: Token[ 4: 91].
- PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
- DisConnect link [ 0]:= 50; PartToken[ 51: 51].
- DisConnect link [ 1]:= 17; PartToken[ 18: 18].
- DisConnect link [ 2]:= 72; PartToken[ 73: 73].
- DeleteFromList:: Vchunk[ 4: 91]. (* 1)
- DisConnect FromList[ 0]:= 56; Token[ 57: 57].
- Vlists[ 89] := 100;
-
- Delete for 11 parts;
-
- Traverse Count= 0
-
- TRAVERSE PartId[ 6] and all Connections to 5 Levels
- SEED In Traverse Part [ 4: 65] @ Level = 4.
-
- Traverse Count= 357
- Traverse Asserts = 5. True Tests = 1
- < 5> DrawObj objects DELETED.
- < 2> are Named.
- < 2> Point objects DELETED.
-
- CREATE 10 Additional Parts
-
- Create 10 New Parts
- Create Part 101. Token[ 4: 102].
-
- < 10> Parts Created. CurrentId= 110
-
- Connect each instantiated Part TO 3 unique Parts
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 110
- < 81> Part images' Committed.
- < 0> are Named.
- < 38> Point images' Committed.
- < 31> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Committed.
- < 15> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
- < 16> CartesianPoint images' Committed.
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Deleted.
- < 15> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
- < 16> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
-
- END INNER LOOP [ 1: 1].
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- < 0> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- < 0> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
- STATUS= -201
-V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
+++ /dev/null
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
-warn: Entering event queue @ 0. Starting simulation...
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[exetrace]
+intel_format=false
+legion_lockstep=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
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+children=dcache fuPool icache l2cache toL2Bus workload
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+issueToExecuteDelay=1
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+localHistoryTableSize=2048
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+numPhysIntRegs=256
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+renameToROBDelay=1
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+squashWidth=8
+system=system
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
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+hash_delay=1
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+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
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+opList=system.cpu.fuPool.FUList0.opList0
+
+[system.cpu.fuPool.FUList0.opList0]
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+
+[system.cpu.fuPool.FUList1]
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+
+[system.cpu.fuPool.FUList1.opList0]
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+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
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+
+[system.cpu.fuPool.FUList2]
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+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
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+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
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+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList4.opList0
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList5.opList0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
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+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0
+count=1
+opList=system.cpu.fuPool.FUList7.opList0
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
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+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
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+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/o3-timing
+egid=100
+env=
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
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+width=64
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/o3-timing
+system=system
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+
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+[system.cpu.fuPool.FUList7]
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+
+[system.cpu.fuPool]
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+
+[system.cpu]
+type=DerivO3CPU
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+checker=null
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+numROBEntries=192
+smtNumFetchingThreads=1
+smtFetchPolicy=SingleThread
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+smtCommitPolicy=RoundRobin
+instShiftAmt=2
+defer_registration=false
+function_trace=false
+function_trace_start=0
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+print_reg_delta=false
+pc_symbol=true
+intel_format=false
+legion_lockstep=false
+trace_system=client
+
+[statsreset]
+reset_cycle=0
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 13202034 # Number of BTB hits
+global.BPredUnit.BTBLookups 22107115 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 30370 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 454360 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 16498204 # Number of conditional branches predicted
+global.BPredUnit.lookups 27047110 # Number of BP lookups
+global.BPredUnit.usedRAS 4878193 # Number of times the RAS was used to get a target.
+host_inst_rate 69520 # Simulator instruction rate (inst/s)
+host_mem_usage 239908 # Number of bytes of host memory used
+host_seconds 1144.87 # Real time elapsed on the host
+host_tick_rate 987535 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 14725847 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 11490673 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 28863760 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 16312214 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 79591756 # Number of instructions simulated
+sim_seconds 0.001131 # Number of seconds simulated
+sim_ticks 1130602014 # Number of ticks simulated
+system.cpu.commit.COM:branches 13754477 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 3893678 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 89505192
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 62882698 7025.59%
+ 1 8753972 978.04%
+ 2 5175203 578.20%
+ 3 3243621 362.39%
+ 4 2169519 242.39%
+ 5 1432847 160.09%
+ 6 1161882 129.81%
+ 7 791772 88.46%
+ 8 3893678 435.02%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 88340672 # Number of instructions committed
+system.cpu.commit.COM:loads 20379399 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 35224018 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 359967 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 21665941 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 79591756 # Number of Instructions Simulated
+system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
+system.cpu.cpi 14.205014 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 14.205014 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 19540231 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 4453.766964 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3237.815878 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 19382637 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 701886951 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.008065 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 157594 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 95950 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 199591922 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.003155 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 61644 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 4830.124895 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3999.409028 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 13942631 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 3239786953 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.045899 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 670746 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 527274 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 573803212 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.009818 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 143472 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 3332.672727 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 3759.399862 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 162.470348 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 110 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 125901 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 366594 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 473312202 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 34153608 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 4758.521747 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 3770.525625 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 33325268 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 3941673904 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.024253 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 828340 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 623224 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 773395134 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.006006 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 205116 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 34153608 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 4758.521747 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 3770.525625 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 33325268 # number of overall hits
+system.cpu.dcache.overall_miss_latency 3941673904 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.024253 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 828340 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 623224 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 773395134 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.006006 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 205116 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 201020 # number of replacements
+system.cpu.dcache.sampled_refs 205116 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4057.039034 # Cycle average of tags in use
+system.cpu.dcache.total_refs 33325268 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 27784000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 147771 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 11948269 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 95198 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 3558048 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 131593428 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 51674084 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 25481309 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 4702945 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 281359 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 401531 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 27047110 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 22733117 # Number of cache lines fetched
+system.cpu.fetch.Cycles 51481541 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 159026 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 148267180 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 3966980 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.287100 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 22733117 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 18080227 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.573826 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 94208138
+system.cpu.fetch.rateDist.min_value 0
+ 0 65459635 6948.41%
+ 1 1687117 179.08%
+ 2 1748812 185.63%
+ 3 1938924 205.81%
+ 4 6981531 741.08%
+ 5 6100701 647.58%
+ 6 758078 80.47%
+ 7 1979150 210.08%
+ 8 7554190 801.86%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 22733116 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 3345.551905 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2359.548288 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 22631700 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 339292492 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.004461 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 101416 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 13878 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 206550138 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.003851 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 87538 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets 3731.567010 # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 258.538675 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 97 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 361962 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 22733116 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 3345.551905 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2359.548288 # average overall mshr miss latency
+system.cpu.icache.demand_hits 22631700 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 339292492 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.004461 # miss rate for demand accesses
+system.cpu.icache.demand_misses 101416 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 13878 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 206550138 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.003851 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 87538 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 22733116 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 3345.551905 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2359.548288 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 22631700 # number of overall hits
+system.cpu.icache.overall_miss_latency 339292492 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.004461 # miss rate for overall accesses
+system.cpu.icache.overall_misses 101416 # number of overall misses
+system.cpu.icache.overall_mshr_hits 13878 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 206550138 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.003851 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 87538 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 85490 # number of replacements
+system.cpu.icache.sampled_refs 87537 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1835.330854 # Cycle average of tags in use
+system.cpu.icache.total_refs 22631700 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 1036393877 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 14379719 # Number of branches executed
+system.cpu.iew.EXEC:nop 9265977 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.989418 # Inst execution rate
+system.cpu.iew.EXEC:refs 43156162 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 15338261 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 46157981 # num instructions consuming a value
+system.cpu.iew.WB:count 86105601 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.741496 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 34225955 # num instructions producing a value
+system.cpu.iew.WB:rate 0.913993 # insts written-back per cycle
+system.cpu.iew.WB:sent 86171133 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 389534 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 3213991 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 28863760 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 4784 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 1402526 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 16312214 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 110003367 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 27817901 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 453087 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 93211232 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 28742 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 12962 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 4702945 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 194395 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 1528 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 6922047 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 1365052 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 5008 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 3825 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 1528 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 8484361 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 1467595 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 3825 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 102872 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 286662 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.070398 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.070398 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 93664319 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ (null) 0 0.00% # Type of FU issued
+ IntAlu 49995908 53.38% # Type of FU issued
+ IntMult 43196 0.05% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 123595 0.13% # Type of FU issued
+ FloatCmp 86 0.00% # Type of FU issued
+ FloatCvt 122386 0.13% # Type of FU issued
+ FloatMult 51 0.00% # Type of FU issued
+ FloatDiv 37853 0.04% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 27919833 29.81% # Type of FU issued
+ MemWrite 15421411 16.46% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 1229792 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.013130 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ (null) 0 0.00% # attempts to use FU when none available
+ IntAlu 83895 6.82% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 589327 47.92% # attempts to use FU when none available
+ MemWrite 556570 45.26% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 94208138
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 54322746 5766.25%
+ 1 13333515 1415.33%
+ 2 10626230 1127.95%
+ 3 8813553 935.54%
+ 4 4440243 471.32%
+ 5 1597603 169.58%
+ 6 685526 72.77%
+ 7 334234 35.48%
+ 8 54488 5.78%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 0.994227 # Inst issue rate
+system.cpu.iq.iqInstsAdded 100732606 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 93664319 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 4784 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 20911338 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 73995 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 201 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 16334966 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 292646 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 3929.598028 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2043.469607 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 122985 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 666699531 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.579748 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 169661 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 346697097 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.579748 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 169661 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 147771 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 147307 # number of Writeback hits
+system.cpu.l2cache.Writeback_miss_rate 0.003140 # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses 464 # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate 0.003140 # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses 464 # number of Writeback MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 1.593139 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 292646 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 3929.598028 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2043.469607 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 122985 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 666699531 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.579748 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 169661 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 346697097 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.579748 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 169661 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 440417 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 3918.880417 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2043.469607 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 270292 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 666699531 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.386282 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 170125 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 346697097 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.385228 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 169661 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 136892 # number of replacements
+system.cpu.l2cache.sampled_refs 169660 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 30349.297230 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 270292 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 625483000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 115938 # number of writebacks
+system.cpu.numCycles 94208138 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 7563765 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 87866 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 52361095 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 3315491 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 3509 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 154857350 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 130101763 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 82913656 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 25182526 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 4702945 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 3542613 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 30366775 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 855194 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 4773 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 6398047 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 4771 # count of temporary serializing insts renamed
+system.cpu.timesIdled 275758 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+
+ SYSTEM TYPE...
+ __ZTC__ := False
+ __UNIX__ := True
+ __RISC__ := True
+ SPEC_CPU2000_LP64 := True
+ __MAC__ := False
+ __BCC__ := False
+ __BORLANDC__ := False
+ __GUI__ := False
+ __WTC__ := False
+ __HP__ := False
+
+ CODE OPTIONS...
+ __MACROIZE_HM__ := True
+ __MACROIZE_MEM__ := True
+ ENV01 := True
+ USE_HPP_STYPE_HDRS := False
+ USE_H_STYPE_HDRS := False
+
+ CODE INCLUSION PARAMETERS...
+ INCLUDE_ALL_CODE := False
+ INCLUDE_DELETE_CODE := True
+ __SWAP_GRP_POS__ := True
+ __INCLUDE_MTRX__ := False
+ __BAD_CODE__ := False
+ API_INCLUDE := False
+ BE_CAREFUL := False
+ OLDWAY := False
+ NOTUSED := False
+
+ SYSTEM PARAMETERS...
+ EXT_ENUM := 999999999L
+ CHUNK_CONSTANT := 55555555
+ CORE_CONSTANT := 55555555
+ CORE_LIMIT := 20971520
+ CorePage_Size := 384000
+ ALIGN_BYTES := True
+ CORE_BLOCK_ALIGN := 8
+ FAR_MEM := False
+
+ MEMORY MANAGEMENT PARAMETERS...
+ SYSTEM_ALLOC := True
+ SYSTEM_FREESTORE := True
+ __NO_DISKCACHE__ := False
+ __FREEZE_VCHUNKS__ := True
+ __FREEZE_GRP_PACKETS__ := True
+ __MINIMIZE_TREE_CACHE__:= True
+
+ SYSTEM STD PARAMETERS...
+ __STDOUT__ := False
+ NULL := 0
+ LPTR := False
+ False_Status := 1
+ True_Status := 0
+ LARGE := True
+ TWOBYTE_BOOL := False
+ __NOSTR__ := False
+
+ MEMORY VALIDATION PARAMETERS...
+ CORE_CRC_CHECK := False
+ VALIDATE_MEM_CHUNKS := False
+
+ SYSTEM DEBUG OPTIONS...
+ DEBUG := False
+ MCSTAT := False
+ TRACKBACK := False
+ FLUSH_FILES := False
+ DEBUG_CORE0 := False
+ DEBUG_RISC := False
+ __TREE_BUG__ := False
+ __TRACK_FILE_READS__ := False
+ PAGE_SPACE := False
+ LEAVE_NO_TRACE := True
+ NULL_TRACE_STRS := False
+
+ TIME PARAMETERS...
+ CLOCK_IS_LONG := False
+ __DISPLAY_TIME__ := False
+ __TREE_TIME__ := False
+ __DISPLAY_ERRORS__ := False
+
+ API MACROS...
+ __BMT01__ := True
+ OPTIMIZE := True
+
+ END OF DEFINES.
+
+
+
+ ... IMPLODE MEMORY ...
+
+ SWAP to DiskCache := False
+
+ FREEZE_GRP_PACKETS:= True
+
+ QueBug := 1000
+
+ sizeof(boolean) = 4
+ sizeof(sizetype) = 4
+ sizeof(chunkstruc) = 32
+
+ sizeof(shorttype ) = 2
+ sizeof(idtype ) = 2
+ sizeof(sizetype ) = 4
+ sizeof(indextype ) = 4
+ sizeof(numtype ) = 4
+ sizeof(handletype) = 4
+ sizeof(tokentype ) = 8
+
+ sizeof(short ) = 2
+ sizeof(int ) = 4
+
+ sizeof(lt64 ) = 4
+ sizeof(farlongtype) = 4
+ sizeof(long ) = 8
+ sizeof(longaddr ) = 8
+
+ sizeof(float ) = 4
+ sizeof(double ) = 8
+
+ sizeof(addrtype ) = 8
+ sizeof(char * ) = 8
+ ALLOC CORE_1 :: 16
+ BHOOLE NATH
+
+ OPEN File ./input/lendian.rnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 2030c0
+ DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
+ DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
+ DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+ DB[ 1] LOADED; Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 40054800
+
+ OPEN File ./input/lendian.wnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 21c40
+ DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
+ DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
+ DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+ DB[ 2] LOADED; Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+ BE HERE NOW !!!
+
+
+
+ ... VORTEx ON LINE ...
+
+
+ ... END OF SESSION ...
--- /dev/null
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
--- /dev/null
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0. Starting simulation...
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+simulate_stalls=false
+system=system
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic
+egid=100
+env=
+euid=100
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=AtomicSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+width=1
+function_trace=false
+function_trace_start=0
+simulate_stalls=false
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[statsreset]
+reset_cycle=0
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1347543 # Simulator instruction rate (inst/s)
+host_mem_usage 179988 # Number of bytes of host memory used
+host_seconds 65.56 # Real time elapsed on the host
+host_tick_rate 1347535 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 88340674 # Number of instructions simulated
+sim_seconds 0.000088 # Number of seconds simulated
+sim_ticks 88340673 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 88340674 # number of cpu cycles simulated
+system.cpu.num_insts 88340674 # Number of instructions executed
+system.cpu.num_refs 35224019 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+
+ SYSTEM TYPE...
+ __ZTC__ := False
+ __UNIX__ := True
+ __RISC__ := True
+ SPEC_CPU2000_LP64 := True
+ __MAC__ := False
+ __BCC__ := False
+ __BORLANDC__ := False
+ __GUI__ := False
+ __WTC__ := False
+ __HP__ := False
+
+ CODE OPTIONS...
+ __MACROIZE_HM__ := True
+ __MACROIZE_MEM__ := True
+ ENV01 := True
+ USE_HPP_STYPE_HDRS := False
+ USE_H_STYPE_HDRS := False
+
+ CODE INCLUSION PARAMETERS...
+ INCLUDE_ALL_CODE := False
+ INCLUDE_DELETE_CODE := True
+ __SWAP_GRP_POS__ := True
+ __INCLUDE_MTRX__ := False
+ __BAD_CODE__ := False
+ API_INCLUDE := False
+ BE_CAREFUL := False
+ OLDWAY := False
+ NOTUSED := False
+
+ SYSTEM PARAMETERS...
+ EXT_ENUM := 999999999L
+ CHUNK_CONSTANT := 55555555
+ CORE_CONSTANT := 55555555
+ CORE_LIMIT := 20971520
+ CorePage_Size := 384000
+ ALIGN_BYTES := True
+ CORE_BLOCK_ALIGN := 8
+ FAR_MEM := False
+
+ MEMORY MANAGEMENT PARAMETERS...
+ SYSTEM_ALLOC := True
+ SYSTEM_FREESTORE := True
+ __NO_DISKCACHE__ := False
+ __FREEZE_VCHUNKS__ := True
+ __FREEZE_GRP_PACKETS__ := True
+ __MINIMIZE_TREE_CACHE__:= True
+
+ SYSTEM STD PARAMETERS...
+ __STDOUT__ := False
+ NULL := 0
+ LPTR := False
+ False_Status := 1
+ True_Status := 0
+ LARGE := True
+ TWOBYTE_BOOL := False
+ __NOSTR__ := False
+
+ MEMORY VALIDATION PARAMETERS...
+ CORE_CRC_CHECK := False
+ VALIDATE_MEM_CHUNKS := False
+
+ SYSTEM DEBUG OPTIONS...
+ DEBUG := False
+ MCSTAT := False
+ TRACKBACK := False
+ FLUSH_FILES := False
+ DEBUG_CORE0 := False
+ DEBUG_RISC := False
+ __TREE_BUG__ := False
+ __TRACK_FILE_READS__ := False
+ PAGE_SPACE := False
+ LEAVE_NO_TRACE := True
+ NULL_TRACE_STRS := False
+
+ TIME PARAMETERS...
+ CLOCK_IS_LONG := False
+ __DISPLAY_TIME__ := False
+ __TREE_TIME__ := False
+ __DISPLAY_ERRORS__ := False
+
+ API MACROS...
+ __BMT01__ := True
+ OPTIMIZE := True
+
+ END OF DEFINES.
+
+
+
+ ... IMPLODE MEMORY ...
+
+ SWAP to DiskCache := False
+
+ FREEZE_GRP_PACKETS:= True
+
+ QueBug := 1000
+
+ sizeof(boolean) = 4
+ sizeof(sizetype) = 4
+ sizeof(chunkstruc) = 32
+
+ sizeof(shorttype ) = 2
+ sizeof(idtype ) = 2
+ sizeof(sizetype ) = 4
+ sizeof(indextype ) = 4
+ sizeof(numtype ) = 4
+ sizeof(handletype) = 4
+ sizeof(tokentype ) = 8
+
+ sizeof(short ) = 2
+ sizeof(int ) = 4
+
+ sizeof(lt64 ) = 4
+ sizeof(farlongtype) = 4
+ sizeof(long ) = 8
+ sizeof(longaddr ) = 8
+
+ sizeof(float ) = 4
+ sizeof(double ) = 8
+
+ sizeof(addrtype ) = 8
+ sizeof(char * ) = 8
+ ALLOC CORE_1 :: 16
+ BHOOLE NATH
+
+ OPEN File ./input/lendian.rnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 2030c0
+ DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
+ DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
+ DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+ DB[ 1] LOADED; Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 40054800
+
+ OPEN File ./input/lendian.wnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 21c40
+ DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
+ DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
+ DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+ DB[ 2] LOADED; Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+ BE HERE NOW !!!
+
+
+
+ ... VORTEx ON LINE ...
+
+
+ ... END OF SESSION ...
--- /dev/null
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
--- /dev/null
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0. Starting simulation...
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache icache l2cache toL2Bus workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+system=system
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing
+egid=100
+env=
+euid=100
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[statsreset]
+reset_cycle=0
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 704446 # Simulator instruction rate (inst/s)
+host_mem_usage 275648 # Number of bytes of host memory used
+host_seconds 125.40 # Real time elapsed on the host
+host_tick_rate 9716991 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 88340674 # Number of instructions simulated
+sim_seconds 0.001219 # Number of seconds simulated
+sim_ticks 1218558003 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3613.021476 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2613.021476 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 219545250 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 158780250 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 4540.238491 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3540.238491 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 651878362 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 508300362 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 169.742404 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 4264.514136 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 34685672 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 871423612 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 204343 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 667080612 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 204343 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 4264.514136 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 34685672 # number of overall hits
+system.cpu.dcache.overall_miss_latency 871423612 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 204343 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 667080612 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 204343 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 200247 # number of replacements
+system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4056.438323 # Cycle average of tags in use
+system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 28900000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 147714 # number of writebacks
+system.cpu.icache.ReadReq_accesses 88340675 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 2932.969818 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 1932.969818 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 88264239 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 224184481 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000865 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 147748481 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000865 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 1154.746965 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 88340675 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 2932.969818 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency
+system.cpu.icache.demand_hits 88264239 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 224184481 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000865 # miss rate for demand accesses
+system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 147748481 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000865 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 88340675 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 2932.969818 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 88264239 # number of overall hits
+system.cpu.icache.overall_miss_latency 224184481 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000865 # miss rate for overall accesses
+system.cpu.icache.overall_misses 76436 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 147748481 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000865 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 74391 # number of replacements
+system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1796.106842 # Cycle average of tags in use
+system.cpu.icache.total_refs 88264239 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses 280779 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 3650.218185 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1972.851350 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 112101 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 615711503 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.600750 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 168678 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 332776620 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.600750 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 168678 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 147276 # number of Writeback hits
+system.cpu.l2cache.Writeback_miss_rate 0.002965 # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses 438 # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate 0.002965 # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses 438 # number of Writeback MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 1.537705 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 3650.218185 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 112101 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 615711503 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.600750 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 168678 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 332776620 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.600750 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 168678 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 428493 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 3640.764345 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 259377 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 615711503 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.394676 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 169116 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 332776620 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.393654 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 168678 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 135910 # number of replacements
+system.cpu.l2cache.sampled_refs 168678 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 30401.731729 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 259377 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 667816000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 115911 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 1218558003 # number of cpu cycles simulated
+system.cpu.num_insts 88340674 # Number of instructions executed
+system.cpu.num_refs 35224019 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+
+ SYSTEM TYPE...
+ __ZTC__ := False
+ __UNIX__ := True
+ __RISC__ := True
+ SPEC_CPU2000_LP64 := True
+ __MAC__ := False
+ __BCC__ := False
+ __BORLANDC__ := False
+ __GUI__ := False
+ __WTC__ := False
+ __HP__ := False
+
+ CODE OPTIONS...
+ __MACROIZE_HM__ := True
+ __MACROIZE_MEM__ := True
+ ENV01 := True
+ USE_HPP_STYPE_HDRS := False
+ USE_H_STYPE_HDRS := False
+
+ CODE INCLUSION PARAMETERS...
+ INCLUDE_ALL_CODE := False
+ INCLUDE_DELETE_CODE := True
+ __SWAP_GRP_POS__ := True
+ __INCLUDE_MTRX__ := False
+ __BAD_CODE__ := False
+ API_INCLUDE := False
+ BE_CAREFUL := False
+ OLDWAY := False
+ NOTUSED := False
+
+ SYSTEM PARAMETERS...
+ EXT_ENUM := 999999999L
+ CHUNK_CONSTANT := 55555555
+ CORE_CONSTANT := 55555555
+ CORE_LIMIT := 20971520
+ CorePage_Size := 384000
+ ALIGN_BYTES := True
+ CORE_BLOCK_ALIGN := 8
+ FAR_MEM := False
+
+ MEMORY MANAGEMENT PARAMETERS...
+ SYSTEM_ALLOC := True
+ SYSTEM_FREESTORE := True
+ __NO_DISKCACHE__ := False
+ __FREEZE_VCHUNKS__ := True
+ __FREEZE_GRP_PACKETS__ := True
+ __MINIMIZE_TREE_CACHE__:= True
+
+ SYSTEM STD PARAMETERS...
+ __STDOUT__ := False
+ NULL := 0
+ LPTR := False
+ False_Status := 1
+ True_Status := 0
+ LARGE := True
+ TWOBYTE_BOOL := False
+ __NOSTR__ := False
+
+ MEMORY VALIDATION PARAMETERS...
+ CORE_CRC_CHECK := False
+ VALIDATE_MEM_CHUNKS := False
+
+ SYSTEM DEBUG OPTIONS...
+ DEBUG := False
+ MCSTAT := False
+ TRACKBACK := False
+ FLUSH_FILES := False
+ DEBUG_CORE0 := False
+ DEBUG_RISC := False
+ __TREE_BUG__ := False
+ __TRACK_FILE_READS__ := False
+ PAGE_SPACE := False
+ LEAVE_NO_TRACE := True
+ NULL_TRACE_STRS := False
+
+ TIME PARAMETERS...
+ CLOCK_IS_LONG := False
+ __DISPLAY_TIME__ := False
+ __TREE_TIME__ := False
+ __DISPLAY_ERRORS__ := False
+
+ API MACROS...
+ __BMT01__ := True
+ OPTIMIZE := True
+
+ END OF DEFINES.
+
+
+
+ ... IMPLODE MEMORY ...
+
+ SWAP to DiskCache := False
+
+ FREEZE_GRP_PACKETS:= True
+
+ QueBug := 1000
+
+ sizeof(boolean) = 4
+ sizeof(sizetype) = 4
+ sizeof(chunkstruc) = 32
+
+ sizeof(shorttype ) = 2
+ sizeof(idtype ) = 2
+ sizeof(sizetype ) = 4
+ sizeof(indextype ) = 4
+ sizeof(numtype ) = 4
+ sizeof(handletype) = 4
+ sizeof(tokentype ) = 8
+
+ sizeof(short ) = 2
+ sizeof(int ) = 4
+
+ sizeof(lt64 ) = 4
+ sizeof(farlongtype) = 4
+ sizeof(long ) = 8
+ sizeof(longaddr ) = 8
+
+ sizeof(float ) = 4
+ sizeof(double ) = 8
+
+ sizeof(addrtype ) = 8
+ sizeof(char * ) = 8
+ ALLOC CORE_1 :: 16
+ BHOOLE NATH
+
+ OPEN File ./input/lendian.rnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 2030c0
+ DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
+ DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
+ DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+ DB[ 1] LOADED; Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 40054800
+
+ OPEN File ./input/lendian.wnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 21c40
+ DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
+ DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
+ DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+ DB[ 2] LOADED; Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+ BE HERE NOW !!!
+
+
+
+ ... VORTEx ON LINE ...
+
+
+ ... END OF SESSION ...
--- /dev/null
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
--- /dev/null
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0. Starting simulation...