Merge remote-tracking branch 'origin/master' into clifford/specify
authorEddie Hung <eddie@fpgeh.com>
Fri, 3 May 2019 22:05:57 +0000 (15:05 -0700)
committerEddie Hung <eddie@fpgeh.com>
Fri, 3 May 2019 22:05:57 +0000 (15:05 -0700)
1  2 
frontends/ast/genrtlil.cc
frontends/verilog/verilog_frontend.cc
kernel/rtlil.cc
passes/opt/opt_clean.cc

Simple merge
index 8202ab9d75b91f5fe3d7de5e016aede4a758cf92,9e624d355d52a3efa95f9430bc8871c3746f99a2..01e589efbca60c443e1c6b9c08854b2a4a5ec00c
@@@ -242,12 -237,11 +242,10 @@@ struct VerilogFrontend : public Fronten
                formal_mode = false;
                norestrict_mode = false;
                assume_asserts_mode = false;
 -              noblackbox_mode = false;
                lib_mode = false;
 -              nowb_mode = false;
 +              specify_mode = false;
                default_nettype_wire = true;
  
-               log_header(design, "Executing Verilog-2005 frontend.\n");
                args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end());
  
                size_t argidx;
diff --cc kernel/rtlil.cc
Simple merge
Simple merge