Move clean from aigerparse to abc9

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index b9ab6fc099a2e85911339076860f0bb046c968ba..904a1079d1ad8a8f598af833b4caaca7657d0c99 100644 (file)
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -598,8 +598,6 @@ next_line:
     module->fixup_ports();
     design->add(module);
 
-    Pass::call(design, "clean");
-
     for (auto cell : module->cells().to_vector()) {
         if (cell->type != "$lut") continue;
         auto y_port = cell->getPort("\\Y").as_bit();

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 67d0981f4c3c24df189cb00927a5730872391ec8..2aa19b348fec78afd508e751642b0a3185215d13 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -548,6 +548,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"];
                if (mapped_mod == NULL)
                        log_error("ABC output file does not contain a module `netlist'.\n");
+               Pass::call(mapped_design, "clean");
 
                pool<RTLIL::SigBit> output_bits;
                for (auto &it : mapped_mod->wires_) {