Simplify RV32 comparisons

No need to eliminate the upper 32 bits of the 64-bit x-register, as all
RV32 instructions should sign-extend their results to 64 bits.

diff --git a/riscv/decode.h b/riscv/decode.h
index 5d304a123a7c404e75ec3d43d8562114c1de4ff3..55f03ffcdfb6d7260cf35d11603b2042a952f19d 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -180,7 +180,6 @@ private:
 #endif
 #define require_accelerator if (unlikely((STATE.mstatus & MSTATUS_XS) == 0)) throw trap_illegal_instruction()
 
-#define cmp_trunc(reg) (reg_t(reg) << (64-xlen))
 #define set_fp_exceptions ({ STATE.fflags |= softfloat_exceptionFlags; \
                              softfloat_exceptionFlags = 0; })
 

diff --git a/riscv/insns/beq.h b/riscv/insns/beq.h
index 7b26488e434d77715390b54ff5e478949154ecd9..fd7e0614955879ef8a31ed978b9081e20a9da593 100644 (file)
--- a/riscv/insns/beq.h
+++ b/riscv/insns/beq.h
@@ -1,2 +1,2 @@
-if(cmp_trunc(RS1) == cmp_trunc(RS2))
+if(RS1 == RS2)
   set_pc(BRANCH_TARGET);

diff --git a/riscv/insns/bge.h b/riscv/insns/bge.h
index dca544b45381855f4232d9da4b2d67ba83de9616..da0c68e6a41fc8c048330b5473ffcf06343cde4f 100644 (file)
--- a/riscv/insns/bge.h
+++ b/riscv/insns/bge.h
@@ -1,2 +1,2 @@
-if(sreg_t(cmp_trunc(RS1)) >= sreg_t(cmp_trunc(RS2)))
+if(sreg_t(RS1) >= sreg_t(RS2))
   set_pc(BRANCH_TARGET);

diff --git a/riscv/insns/bgeu.h b/riscv/insns/bgeu.h
index 63254669ecda56361211afc80a7990dc59f3d481..d764a347ef9223f0c9c2e87c14ac974e1f837b35 100644 (file)
--- a/riscv/insns/bgeu.h
+++ b/riscv/insns/bgeu.h
@@ -1,2 +1,2 @@
-if(cmp_trunc(RS1) >= cmp_trunc(RS2))
+if(RS1 >= RS2)
   set_pc(BRANCH_TARGET);

diff --git a/riscv/insns/blt.h b/riscv/insns/blt.h
index d84fd7a38f1c4d9845327308f13af43b79fd1381..c54fb7693a01e5c8e57c47f2e41faa77fb35fe87 100644 (file)
--- a/riscv/insns/blt.h
+++ b/riscv/insns/blt.h
@@ -1,2 +1,2 @@
-if(sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2)))
+if(sreg_t(RS1) < sreg_t(RS2))
   set_pc(BRANCH_TARGET);

diff --git a/riscv/insns/bltu.h b/riscv/insns/bltu.h
index 250fd4f9d9dd66bf6cb3e032403ba5219cf333d9..ff75e8a6da36a1e7b6f662685499b53aaf7b997f 100644 (file)
--- a/riscv/insns/bltu.h
+++ b/riscv/insns/bltu.h
@@ -1,2 +1,2 @@
-if(cmp_trunc(RS1) < cmp_trunc(RS2))
+if(RS1 < RS2)
   set_pc(BRANCH_TARGET);

diff --git a/riscv/insns/bne.h b/riscv/insns/bne.h
index f7757214b494939480ed348b7a06d92feea5073b..1e6cb7c7ac2ffd3dfbdf34c6ab58cf27c69a2139 100644 (file)
--- a/riscv/insns/bne.h
+++ b/riscv/insns/bne.h
@@ -1,2 +1,2 @@
-if(cmp_trunc(RS1) != cmp_trunc(RS2))
+if(RS1 != RS2)
   set_pc(BRANCH_TARGET);

diff --git a/riscv/insns/slt.h b/riscv/insns/slt.h
index dd6e58ec8ea7e7e44a68c8373f7fbc17a3b17063..25ccd45ee8958be21ae69f8507705032ec9fad1b 100644 (file)
--- a/riscv/insns/slt.h
+++ b/riscv/insns/slt.h
@@ -1 +1 @@
-WRITE_RD(sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2)));
+WRITE_RD(sreg_t(RS1) < sreg_t(RS2));

diff --git a/riscv/insns/slti.h b/riscv/insns/slti.h
index 18d32daed429634c035bc0c27ecf9a05cf739b9a..3671d2418fbbd3771f6f412cf301748a4eac2a4c 100644 (file)
--- a/riscv/insns/slti.h
+++ b/riscv/insns/slti.h
@@ -1 +1 @@
-WRITE_RD(sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(insn.i_imm())));
+WRITE_RD(sreg_t(RS1) < sreg_t(insn.i_imm()));

diff --git a/riscv/insns/sltiu.h b/riscv/insns/sltiu.h
index ff4eae1586b7ff5d75029472982389e248e7baba..c4478fda14a76d56adebc86c17cd7c4672ec7626 100644 (file)
--- a/riscv/insns/sltiu.h
+++ b/riscv/insns/sltiu.h
@@ -1 +1 @@
-WRITE_RD(cmp_trunc(RS1) < cmp_trunc(insn.i_imm()));
+WRITE_RD(RS1 < insn.i_imm());

diff --git a/riscv/insns/sltu.h b/riscv/insns/sltu.h
index 3a353fd05977de64e8d88e3325ebee6f90b15f45..84d97a2a3d2f89c6d3c59654cf86492b84b22cf3 100644 (file)
--- a/riscv/insns/sltu.h
+++ b/riscv/insns/sltu.h
@@ -1 +1 @@
-WRITE_RD(cmp_trunc(RS1) < cmp_trunc(RS2));
+WRITE_RD(RS1 < RS2);