[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be...
authorbugzilla-daemon <bugzilla-daemon@libre-soc.org>
Mon, 25 May 2020 15:14:34 +0000 (15:14 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Mon, 25 May 2020 15:14:36 +0000 (16:14 +0100)
b9/a5c1b482a872319d8a3c9c1834d4ef28cc610e [new file with mode: 0644]

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+Date: Mon, 25 May 2020 15:14:34 +0000
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+X-Bugzilla-Component: Source Code
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: cestrauss@gmail.com
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+Message-ID: <bug-336-13-O8lbIuAecv@https.bugs.libre-soc.org/>
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+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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